From: Animesh Manna <animesh.manna@intel.com>
Date: Tue, 4 Aug 2015 16:32:42 +0000 (+0530)
Subject: drm/i915/bxt: Modified HAS_CSR, added support for BXT
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7b403ffba8ed8636f3467a9008bd2e060792b2e4;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/i915/bxt: Modified HAS_CSR, added support for BXT

Modified HAS_CSR macro defination which earlier only supported
for skl, now added support for BXT.

v1: Initial version.

v2: Instaed of skylake/broxton check added gen9 check alone based
on review comment from Sunil.

Cc: Vetter, Daniel <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 677faa8be228..3795fdfcd1c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2578,7 +2578,7 @@ struct drm_i915_cmd_table {
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
-#define HAS_CSR(dev)	(IS_SKYLAKE(dev))
+#define HAS_CSR(dev)	(IS_GEN9(dev))
 
 #define HAS_GUC_UCODE(dev)	(IS_GEN9(dev))
 #define HAS_GUC_SCHED(dev)	(IS_GEN9(dev))