From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon, 25 Jun 2012 17:06:12 +0000 (+0200)
Subject: Merge tag 'v3.5-rc4' into drm-intel-next-queued
X-Git-Tag: MMI-PSA29.97-13-9~16260^2~42^2
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7b0cfee1a24efdfe0235bac62e53f686fe8a8e24;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git

Merge tag 'v3.5-rc4' into drm-intel-next-queued

I want to merge the "no more fake agp on gen6+" patches into
drm-intel-next (well, the last pieces). But a patch in 3.5-rc4 also
adds a new use of dev->agp. Hence the backmarge to sort this out, for
otherwise drm-intel-next merged into Linus' tree would conflict in the
relevant code, things would compile but nicely OOPS at driver load :(

Conflicts in this merge are just simple cases of "both branches
changed/added lines at the same place". The only tricky part is to
keep the order correct wrt the unwind code in case of errors in
intel_ringbuffer.c (and the MI_DISPLAY_FLIP #defines in i915_reg.h
together, obviously).

Conflicts:
	drivers/gpu/drm/i915/i915_reg.h
	drivers/gpu/drm/i915/intel_ringbuffer.c

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

7b0cfee1a24efdfe0235bac62e53f686fe8a8e24
diff --cc drivers/gpu/drm/i915/i915_drv.c
index 05adbf23951a,9fe9ebe52a7a..a378c0800304
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -1144,89 -1145,10 +1150,88 @@@ MODULE_LICENSE("GPL and additional righ
  
  /* We give fast paths for the really cool registers */
  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
-        (((dev_priv)->info->gen >= 6) && \
-         ((reg) < 0x40000) &&            \
-         ((reg) != FORCEWAKE)) && \
-        (!IS_VALLEYVIEW((dev_priv)->dev))
+ 	((HAS_FORCE_WAKE((dev_priv)->dev)) && \
+ 	 ((reg) < 0x40000) &&            \
+ 	 ((reg) != FORCEWAKE))
  
 +static bool IS_DISPLAYREG(u32 reg)
 +{
 +	/*
 +	 * This should make it easier to transition modules over to the
 +	 * new register block scheme, since we can do it incrementally.
 +	 */
 +	if (reg >= 0x180000)
 +		return false;
 +
 +	if (reg >= RENDER_RING_BASE &&
 +	    reg < RENDER_RING_BASE + 0xff)
 +		return false;
 +	if (reg >= GEN6_BSD_RING_BASE &&
 +	    reg < GEN6_BSD_RING_BASE + 0xff)
 +		return false;
 +	if (reg >= BLT_RING_BASE &&
 +	    reg < BLT_RING_BASE + 0xff)
 +		return false;
 +
 +	if (reg == PGTBL_ER)
 +		return false;
 +
 +	if (reg >= IPEIR_I965 &&
 +	    reg < HWSTAM)
 +		return false;
 +
 +	if (reg == MI_MODE)
 +		return false;
 +
 +	if (reg == GFX_MODE_GEN7)
 +		return false;
 +
 +	if (reg == RENDER_HWS_PGA_GEN7 ||
 +	    reg == BSD_HWS_PGA_GEN7 ||
 +	    reg == BLT_HWS_PGA_GEN7)
 +		return false;
 +
 +	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
 +	    reg == GEN6_BSD_RNCID)
 +		return false;
 +
 +	if (reg == GEN6_BLITTER_ECOSKPD)
 +		return false;
 +
 +	if (reg >= 0x4000c &&
 +	    reg <= 0x4002c)
 +		return false;
 +
 +	if (reg >= 0x4f000 &&
 +	    reg <= 0x4f08f)
 +		return false;
 +
 +	if (reg >= 0x4f100 &&
 +	    reg <= 0x4f11f)
 +		return false;
 +
 +	if (reg >= VLV_MASTER_IER &&
 +	    reg <= GEN6_PMIER)
 +		return false;
 +
 +	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
 +	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
 +		return false;
 +
 +	if (reg >= VLV_IIR_RW &&
 +	    reg <= VLV_ISR)
 +		return false;
 +
 +	if (reg == FORCEWAKE_VLV ||
 +	    reg == FORCEWAKE_ACK_VLV)
 +		return false;
 +
 +	if (reg == GEN6_GDRST)
 +		return false;
 +
 +	return true;
 +}
 +
  #define __i915_read(x, y) \
  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
  	u##x val = 0; \
diff --cc drivers/gpu/drm/i915/i915_reg.h
index 0a61481cd2c2,48d5e8e051cf..9dfc4c5ff31e
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -210,9 -210,14 +210,17 @@@
  #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
  #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
  #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+ /* IVB has funny definitions for which plane to flip. */
+ #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
+ #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
+ #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
+ #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
+ #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
+ #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
 +#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
 +#define   MI_ARB_ENABLE			(1<<0)
 +#define   MI_ARB_DISABLE		(0<<0)
+ 
  #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
  #define   MI_MM_SPACE_GTT		(1<<8)
  #define   MI_MM_SPACE_PHYSICAL		(0<<8)
diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
index 7a16f16371e6,e5b84ff89ca5..f30a53a8917e
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@@ -1006,9 -998,12 +1017,13 @@@ static int intel_init_ring_buffer(struc
  	if (ret)
  		goto err_unref;
  
+ 	ret = i915_gem_object_set_to_gtt_domain(obj, true);
+ 	if (ret)
+ 		goto err_unpin;
+ 
 -	ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
 -					 ring->size);
 +	ring->virtual_start =
 +		ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
 +			   ring->size);
  	if (ring->virtual_start == NULL) {
  		DRM_ERROR("Failed to map ringbuffer.\n");
  		ret = -EINVAL;