From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Fri, 17 Jan 2014 15:51:13 +0000 (-0200)
Subject: drm/i915: WARN in case we're enabling the pipe and it's enabled
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7ad25d488faf2622d5c1c3c04e42e8efe9539da0;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

drm/i915: WARN in case we're enabling the pipe and it's enabled

... and QUIRK_PIPEA_FORCE is not present.

I initially thought that case was impossible and just added a WARN on
it, but then I was told this case is possible due to
QUIRK_PIPEA_FORCE. So let's add a WARN that serves two purposes:
  - tell us in case we have done something wrong;
  - document the only case where we expect this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b040bd43bfd7..43b4281daf25 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1793,8 +1793,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 
 	reg = PIPECONF(cpu_transcoder);
 	val = I915_READ(reg);
-	if (val & PIPECONF_ENABLE)
+	if (val & PIPECONF_ENABLE) {
+		WARN_ON(!(pipe == PIPE_A &&
+			  dev_priv->quirks & QUIRK_PIPEA_FORCE));
 		return;
+	}
 
 	I915_WRITE(reg, val | PIPECONF_ENABLE);
 	POSTING_READ(reg);