From: Tom St Denis <tom.stdenis@amd.com>
Date: Thu, 28 Jul 2016 13:44:14 +0000 (-0400)
Subject: drm/amd/amdgpu: don't set clockgating in uvd_v6_0_start()
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7acc83d4df77d2ed0153db2583f00a34e31fce92;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/amd/amdgpu: don't set clockgating in uvd_v6_0_start()

This is handled properly by both DPM and PP externally.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 4fa50918e886..4dbd5ab29bba 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -396,15 +396,10 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
 
 	uvd_v6_0_mc_resume(adev);
 
-	/* Set dynamic clock gating in S/W control mode */
-	if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
-		uvd_v6_0_set_sw_clock_gating(adev);
-	} else {
-		/* disable clock gating */
-		uint32_t data = RREG32(mmUVD_CGC_CTRL);
-		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
-		WREG32(mmUVD_CGC_CTRL, data);
-	}
+	/* disable clock gating */
+	tmp = RREG32(mmUVD_CGC_CTRL);
+	tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+	WREG32(mmUVD_CGC_CTRL, tmp);
 
 	/* disable interupt */
 	WREG32_P(mmUVD_MASTINT_EN, 0, ~UVD_MASTINT_EN__VCPU_EN_MASK);