From: Scott Wood <oss@buserror.net>
Date: Tue, 15 Mar 2016 06:47:38 +0000 (-0500)
Subject: powerpc/book3e-64: Use hardcoded mttmr opcode
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7a25d91214cb22e642b9ed6e4434bfaf74adad28;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

powerpc/book3e-64: Use hardcoded mttmr opcode

This preserves the ability to build using older binutils (reportedly <=
2.22).

Fixes: 6becef7ea04a ("powerpc/mpc85xx: Add CPU hotplug support for E6500")
Signed-off-by: Scott Wood <oss@buserror.net>
Cc: chenhui.zhao@freescale.com
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 291628320fbe..4286775cbde9 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -41,6 +41,7 @@
 #include <asm/ptrace.h>
 #include <asm/hw_irq.h>
 #include <asm/cputhreads.h>
+#include <asm/ppc-opcode.h>
 
 /* The physical memory is laid out such that the secondary processor
  * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -207,12 +208,12 @@ _GLOBAL(book3e_start_thread)
 	/* If the thread id is invalid, just exit. */
 	b	13f
 10:
-	mttmr	TMRN_IMSR0, r5
-	mttmr	TMRN_INIA0, r4
+	MTTMR(TMRN_IMSR0, 5)
+	MTTMR(TMRN_INIA0, 4)
 	b	12f
 11:
-	mttmr	TMRN_IMSR1, r5
-	mttmr	TMRN_INIA1, r4
+	MTTMR(TMRN_IMSR1, 5)
+	MTTMR(TMRN_INIA1, 4)
 12:
 	isync
 	li	r6, 1