From: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Date: Sat, 25 Feb 2012 15:56:30 +0000 (+0800)
Subject: powerpc/usb: fix usb CTRL_PHY_CLK_VALID breaks on some platform
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=79857e8e7b1ba740f8025b540f1e171c9a0a5d31;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

powerpc/usb: fix usb CTRL_PHY_CLK_VALID breaks on some platform

Fix checking of CTRL_PHY_CLK_VALID bit break on some platform on which
there is not USB CTRL_PHY_CLK_VALID bit.
  - P1023/P3041/P5020 etc,have this bit
  - P3060/4080/PSC913x do have this bit, but not mentioned in RM.
  - P1022(perhaps and other) has no this bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 7a15c2235758..e9d8a0cca47b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -248,7 +248,11 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 	struct usb_hcd *hcd = ehci_to_hcd(ehci);
 	struct fsl_usb2_platform_data *pdata;
 	void __iomem *non_ehci = hcd->regs;
-	u32 temp;
+	u32 temp, chip, rev, svr;
+
+	svr = mfspr(SPRN_SVR);
+	chip = svr >> 16;
+	rev = (svr >> 4) & 0xf;
 
 	pdata = hcd->self.controller->platform_data;
 
@@ -274,12 +278,6 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 		ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
 
 	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
-		unsigned int chip, rev, svr;
-
-		svr = mfspr(SPRN_SVR);
-		chip = svr >> 16;
-		rev = (svr >> 4) & 0xf;
-
 		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
 		if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
 			ehci->has_fsl_port_bug = 1;
@@ -301,9 +299,15 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 		out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
 	}
 
-	if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
-		printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
-		return -ENODEV;
+	/* There is no CTRL_PHY_CLK_VALID bit on some platforms, e.g. P1022 */
+#define SVR_P1022_N_ID 0x80E6
+#define SVR_P1022_S_ID 0x80EE
+	if (chip != SVR_P1022_N_ID && chip != SVR_P1022_S_ID) {
+		if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
+					CTRL_PHY_CLK_VALID)) {
+			printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
+			return -ENODEV;
+		}
 	}
 	return 0;
 }