From: Kisang Lee Date: Thu, 17 May 2018 12:00:34 +0000 (+0900) Subject: [9610] arm64: dts: add usb driver X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=77a280aaef08e8bd7856d0e9268754bd73376e0f;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [9610] arm64: dts: add usb driver Change-Id: I5ade443fb7ad286a3cd19a498f1e712bffa0f408 Signed-off-by: Kisang Lee --- diff --git a/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts b/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts index dff304275ce4..1f0715cf9d92 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts +++ b/arch/arm64/boot/dts/exynos/exynos9610-erd9610.dts @@ -872,6 +872,230 @@ synaptics,regulator_avdd = "vdd_ldo41"; }; }; + + usb@13200000 { + status = "okay"; + dwc3 { + dr_mode = "otg"; + maximum-speed = "super-speed"; + }; + }; + + usbdrd_phy:phy@131D0000 { + status = "okay"; + + hs_tune_param = <&usb_hs_tune>; + }; + + usbdrd3_phy:phy@131F0000 { + status = "okay"; + + hs_tune_param = <&usb3_hs_tune>; + ss_tune_param = <&usb3_ss_tune>; + }; + + usb_hs_tune:hs_tune { + hs_tune_cnt = <12>; + + /* value = */ + hs_tune1 { + tune_name = "tx_vref"; + tune_value = <0xf 0xf>; + }; + + hs_tune2 { + tune_name = "tx_pre_emp"; + tune_value = <0x3 0x3>; + }; + + hs_tune3 { + tune_name = "tx_pre_emp_plus"; + tune_value = <0x0 0x0>; + }; + + hs_tune4 { + tune_name = "tx_res"; + tune_value = <0x3 0x3>; + }; + + hs_tune5 { + tune_name = "tx_rise"; + tune_value = <0x3 0x3>; + }; + + hs_tune6 { + tune_name = "tx_hsxv"; + tune_value = <0x3 0x3>; + }; + + hs_tune7 { + tune_name = "tx_fsls"; + tune_value = <0x3 0x3>; + }; + + hs_tune8 { + tune_name = "rx_sqrx"; + tune_value = <0x7 0x7>; + }; + + hs_tune9 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune10 { + tune_name = "otg"; + tune_value = <0x2 0x2>; + }; + + hs_tune11 { + /* true : 1, false: 0 */ + /* */ + tune_name = "enable_user_imp"; + tune_value = <0x0 0x0>; + }; + + hs_tune12 { + /* PHY clk : 1 , FREE clk : 0 */ + tune_name = "is_phyclock"; + tune_value = <0x1 0x1>; + }; + }; + + usb3_ss_tune:ss_tune { + ss_tune_cnt = <15>; + + /* value = */ + ss_tune1 { + tune_name = "tx0_term_offset"; + tune_value = <0x0 0x0>; + }; + + ss_tune2 { + tune_name = "pcs_tx_swing_full"; + tune_value = <0x7f 0x7f>; + }; + + ss_tune3 { + tune_name = "pcs_tx_deemph_6db"; + tune_value = <0x1c 0x1c>; + }; + + ss_tune4 { + tune_name = "pcs_tx_deemph_3p5db"; + tune_value = <0x1c 0x1c>; + }; + + ss_tune5 { + tune_name = "tx_vboost_lvl_sstx"; + tune_value = <0x7 0x7>; + }; + + ss_tune6 { + tune_name = "tx_vboost_lvl"; + tune_value = <0x4 0x4>; + }; + + ss_tune7 { + tune_name = "los_level"; + tune_value = <0x9 0x9>; + }; + + ss_tune8 { + tune_name = "los_bias"; + tune_value = <0x5 0x5>; + }; + + ss_tune9 { + tune_name = "pcs_rx_los_mask_val"; + tune_value = <0x104 0x104>; + }; + + ss_tune10 { + tune_name = "tx_eye_height_cntl_en"; + tune_value = <0x1 0x1>; + }; + + ss_tune11 { + tune_name = "pipe_tx_deemph_update_delay"; + tune_value = <0x2 0x2>; + }; + + ss_tune12 { + tune_name = "pcs_tx_swing_full_sstx"; + tune_value = <0x7f 0x7f>; + }; + ss_tune13 { + tune_name = "rx_eq_fix_val"; + tune_value = <0x2 0x2>; + }; + + ss_tune14 { + tune_name = "rx_decode_mode"; + tune_value = <0x1 0x1>; + }; + + ss_tune15 { + tune_name = "decrese_ss_tx_imp"; + tune_value = <0x1 0x1>; + }; + }; + + usb3_hs_tune:hs_tune { + hs_tune_cnt = <10>; + + /* value = */ + hs_tune1 { + tune_name = "tx_pre_emp"; + tune_value = <0x3 0x3>; + }; + + hs_tune2 { + tune_name = "tx_pre_emp_plus"; + tune_value = <0x0 0x0>; + }; + + hs_tune3 { + tune_name = "tx_vref"; + tune_value = <0x7 0x7>; + }; + + hs_tune4 { + tune_name = "rx_sqrx"; + tune_value = <0x7 0x7>; + }; + + hs_tune5 { + tune_name = "tx_rise"; + tune_value = <0x3 0x3>; + }; + + hs_tune6 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune7 { + tune_name = "tx_hsxv"; + tune_value = <0x3 0x3>; + }; + + hs_tune8 { + tune_name = "tx_fsls"; + tune_value = <0x3 0x3>; + }; + + hs_tune9 { + tune_name = "tx_res"; + tune_value = <0x3 0x3>; + }; + + hs_tune10 { + tune_name = "utim_clk"; + tune_value = <0x1 0x1>; + }; + }; + }; &pinctrl_0 { diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi index 5b1ba8e4b80b..0cba2e4def89 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -1608,6 +1608,153 @@ }; }; + udc: usb@13200000 { + compatible = "samsung,exynos-dwusb"; + clocks = <&clock GATE_USB30DRD_QCH_USB30>; + clock-names = "hsdrd"; + reg = <0x0 0x13200000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3 { + compatible = "synopsys,dwc3"; + reg = <0x0 0x13200000 0x10000>; + interrupts = <0 186 0>; + //suspend_clk_freq = <66000000>; + tx-fifo-resize = <0>; + adj-sof-accuracy = <0>; + is_not_vbus_pad = <1>; + enable_sprs_transfer = <1>; + qos_int_level = <100000 200000>; + phys = <&usbdrd_phy 0>, <&usbdrd3_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* check susphy support */ + xhci_l2_support = <0>; + /* support usb audio offloading: 1, if not: 0 */ + usb_audio_offloading = <0>; + /* don't support USB L2 sleep */ + ldos = <0>; + /* + * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative. + * One of them should be selected + */ + snps,dis-u2-freeclk-exists-quirk; + /* snps,dis_u2_susphy_quirk; */ + }; + }; + + usbdrd_phy: phy@131D0000 { + compatible = "samsung,exynos-usbdrd-phy"; + reg = <0x0 0x131D0000 0x200>; + clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>, + <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>, + <&clock OSCCLK>; + clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + pmu_mask = <0x3>; + pmu_offset = <0x704>; + //pmu_offset_dp = <0x66c>; + + /* USBDP combo phy version - 0x200 */ + phy_version = <0x300>; + /* if it doesn't need phy user mux, */ + /* you should write "none" */ + /* but refclk shouldn't be omitted */ + phyclk_mux = "none"; + phy_refclk = "oscclk"; + + /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */ + has_other_phy = <0>; + /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */ + has_combo_phy = <0>; + sub_phy_version = <0x300>; + + /* ip type */ + /* USB3DRD = 0 */ + /* USB3HOST = 1 */ + /* USB2DRD = 2 */ + /* USB2HOST = 3 */ + ip_type = <0x2>; + + /* for PHY CAL */ + /* choice only one item */ + phy_refsel_clockcore = <1>; + phy_refsel_ext_osc = <0>; + phy_refsel_xtal = <0>; + phy_refsel_diff_pad = <0>; + phy_refsel_diff_internal = <0>; + phy_refsel_diff_single = <0>; + + /* true : 1 , false : 0 */ + use_io_for_ovc = <0>; + common_block_disable = <1>; + is_not_vbus_pad = <1>; + used_phy_port = <0>; + + status = "disabled"; + + #phy-cells = <1>; + ranges; + }; + + usbdrd3_phy: phy@131F0000 { + compatible = "samsung,exynos-usbdrd-phy"; + reg = <0x0 0x131F0000 0x1000>, + <0x0 0x131E0000 0x800>; + clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>, + <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>, + <&clock OSCCLK>; + clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + pmu_mask = <0x3>; + pmu_offset = <0x704>; + //pmu_offset_dp = <0x66c>; + + /* USBDP combo phy version - 0x200 */ + phy_version = <0x530>; + /* if it doesn't need phy user mux, */ + /* you should write "none" */ + /* but refclk shouldn't be omitted */ + phyclk_mux = "none"; + phy_refclk = "oscclk"; + + /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */ + has_other_phy = <1>; + /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */ + has_combo_phy = <0>; + sub_phy_version = <0x300>; + + /* ip type */ + /* USB3DRD = 0 */ + /* USB3HOST = 1 */ + /* USB2DRD = 2 */ + /* USB2HOST = 3 */ + ip_type = <0x0>; + + /* for PHY CAL */ + /* choice only one item */ + phy_refsel_clockcore = <1>; + phy_refsel_ext_osc = <0>; + phy_refsel_xtal = <0>; + phy_refsel_diff_pad = <0>; + phy_refsel_diff_internal = <0>; + phy_refsel_diff_single = <0>; + + /* true : 1 , false : 0 */ + use_io_for_ovc = <0>; + common_block_disable = <1>; + is_not_vbus_pad = <1>; + used_phy_port = <0>; + + status = "disabled"; + + #phy-cells = <1>; + ranges; + }; + + iommu-domain_dpu { compatible = "samsung,exynos-iommu-bus"; #address-cells = <2>;