From: David S. Miller <davem@davemloft.net>
Date: Fri, 29 Feb 2008 05:53:20 +0000 (-0800)
Subject: [SPARC]: Add reboot_command[] extern decl to asm/system.h
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7729d74ed5099021f79ee8ecfa676829b5bac796;p=GitHub%2FLineageOS%2Fandroid_kernel_samsung_universal7580.git

[SPARC]: Add reboot_command[] extern decl to asm/system.h

Kill off some sparse warnings.

Signed-off-by: David S. Miller <davem@davemloft.net>
---

diff --git a/arch/sparc/kernel/process.c b/arch/sparc/kernel/process.c
index 0bd69d0b5cd..70c0dd22491 100644
--- a/arch/sparc/kernel/process.c
+++ b/arch/sparc/kernel/process.c
@@ -139,8 +139,6 @@ void cpu_idle(void)
 
 #endif
 
-extern char reboot_command [];
-
 /* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
 void machine_halt(void)
 {
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index 2aafce7dfc0..e116e38b160 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -114,8 +114,6 @@ void cpu_idle(void)
 	}
 }
 
-extern char reboot_command [];
-
 void machine_halt(void)
 {
 	sstate_halt();
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 45e47c159a6..4e08210cd4c 100644
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -44,6 +44,8 @@ extern enum sparc_cpu sparc_cpu_model;
 
 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
 
+extern char reboot_command[];
+
 extern struct thread_info *current_set[NR_CPUS];
 
 extern unsigned long empty_bad_page;
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index ed91a5d8d4f..53eae091a17 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -30,6 +30,8 @@ enum sparc_cpu {
 #define ARCH_SUN4C_SUN4 0
 #define ARCH_SUN4 0
 
+extern char reboot_command[];
+
 /* These are here in an effort to more fully work around Spitfire Errata
  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
  * branch, the chip can stop executing instructions until a trap occurs.