From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Wed, 22 Jun 2016 09:15:55 +0000 (+0200)
Subject: ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=73ba3a1c64a4c5a1a4b87c773714814eecb84877;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate

In order to be able to properly generate its pixel clock, the pll3-2x fixed
factor needs to be able to change the PLL3 rate too.

Add the needed extra compatible so that it behaves that way.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612b5ed6..e374f4fc8073 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -130,7 +130,7 @@
 		};
 
 		pll3x2: pll3x2_clk {
-			compatible = "fixed-factor-clock";
+			compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
 			#clock-cells = <0>;
 			clock-div = <1>;
 			clock-mult = <2>;