From: Takeshi Kihara Date: Tue, 7 Mar 2017 18:03:22 +0000 (+0100) Subject: arm64: dts: r8a7796: Add Cortex-A57 CPU cores X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7328be4a03b10c19e49a564f4c2e3a9ebcf34ca7;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git arm64: dts: r8a7796: Add Cortex-A57 CPU cores This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of 2 x Cortex-A57. Signed-off-by: Takeshi Kihara [geert: Rebased] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 27f7dd9bd988..d2a2110fc7fc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -37,7 +37,6 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; @@ -47,6 +46,15 @@ enable-method = "psci"; }; + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A7796_PD_CA57_SCU>; @@ -100,7 +108,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -109,13 +117,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; wdt0: watchdog@e6020000 {