From: Chris Dearman Date: Thu, 1 Feb 2007 19:54:13 +0000 (+0000) Subject: [MIPS] Check FCSR for pending interrupts before restoring from a context. X-Git-Tag: MMI-PSA29.97-13-9~44985^2~24^2~6 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6d6671066a311703bca1b91645bb1e04cc983387;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git [MIPS] Check FCSR for pending interrupts before restoring from a context. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 880fa6e841ee..8b5ccfa99dd1 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -114,6 +114,14 @@ LEAF(_save_fp_context32) */ LEAF(_restore_fp_context) EX lw t0, SC_FPC_CSR(a0) + + /* Fail if the CSR has exceptions pending */ + srl t1, t0, 5 + and t1, t0 + andi t1, 0x1f << 7 + bnez t1, fault + nop + #ifdef CONFIG_64BIT EX ldc1 $f1, SC_FPREGS+8(a0) EX ldc1 $f3, SC_FPREGS+24(a0) @@ -157,6 +165,14 @@ LEAF(_restore_fp_context) LEAF(_restore_fp_context32) /* Restore an o32 sigcontext. */ EX lw t0, SC32_FPC_CSR(a0) + + /* Fail if the CSR has exceptions pending */ + srl t1, t0, 5 + and t1, t0 + andi t1, 0x1f << 7 + bnez t1, fault + nop + EX ldc1 $f0, SC32_FPREGS+0(a0) EX ldc1 $f2, SC32_FPREGS+16(a0) EX ldc1 $f4, SC32_FPREGS+32(a0)