From: Ben Skeggs Date: Sun, 1 Apr 2012 11:09:13 +0000 (+1000) Subject: drm/nouveau: use the same packet header macros as userspace X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6d597027755b2eed4298b85ebe3cb5c93b29d1a9;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git drm/nouveau: use the same packet header macros as userspace Cosmetic cleanup only. Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 1da403123eca..c45c7bce9ebd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -495,7 +495,7 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct nouveau_mem *node = old_mem->mm_node; int ret = RING_SPACE(chan, 10); if (ret == 0) { - BEGIN_NVC0(chan, 2, NvSubCopy, 0x0400, 8); + BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); OUT_RING (chan, upper_32_bits(node->vma[0].offset)); OUT_RING (chan, lower_32_bits(node->vma[0].offset)); OUT_RING (chan, upper_32_bits(node->vma[1].offset)); @@ -504,7 +504,7 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, OUT_RING (chan, PAGE_SIZE); OUT_RING (chan, PAGE_SIZE); OUT_RING (chan, new_mem->num_pages); - BEGIN_NVC0(chan, 8, NvSubCopy, 0x0300, 0x0386); + BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); } return ret; } @@ -527,17 +527,17 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2); + BEGIN_NVC0(chan, NvSubM2MF, 0x0238, 2); OUT_RING (chan, upper_32_bits(dst_offset)); OUT_RING (chan, lower_32_bits(dst_offset)); - BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6); + BEGIN_NVC0(chan, NvSubM2MF, 0x030c, 6); OUT_RING (chan, upper_32_bits(src_offset)); OUT_RING (chan, lower_32_bits(src_offset)); OUT_RING (chan, PAGE_SIZE); /* src_pitch */ OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ OUT_RING (chan, PAGE_SIZE); /* line_length */ OUT_RING (chan, line_count); - BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1); + BEGIN_NVC0(chan, NvSubM2MF, 0x0300, 1); OUT_RING (chan, 0x00100110); page_count -= line_count; @@ -572,7 +572,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, 0x0200, 7); + BEGIN_NV04(chan, NvSubM2MF, 0x0200, 7); OUT_RING (chan, 0); OUT_RING (chan, 0); OUT_RING (chan, stride); @@ -585,7 +585,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); + BEGIN_NV04(chan, NvSubM2MF, 0x0200, 1); OUT_RING (chan, 1); } if (old_mem->mem_type == TTM_PL_VRAM && @@ -594,7 +594,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, 0x021c, 7); + BEGIN_NV04(chan, NvSubM2MF, 0x021c, 7); OUT_RING (chan, 0); OUT_RING (chan, 0); OUT_RING (chan, stride); @@ -607,7 +607,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); + BEGIN_NV04(chan, NvSubM2MF, 0x021c, 1); OUT_RING (chan, 1); } @@ -615,10 +615,10 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); + BEGIN_NV04(chan, NvSubM2MF, 0x0238, 2); OUT_RING (chan, upper_32_bits(src_offset)); OUT_RING (chan, upper_32_bits(dst_offset)); - BEGIN_RING(chan, NvSubM2MF, 0x030c, 8); + BEGIN_NV04(chan, NvSubM2MF, 0x030c, 8); OUT_RING (chan, lower_32_bits(src_offset)); OUT_RING (chan, lower_32_bits(dst_offset)); OUT_RING (chan, stride); @@ -627,7 +627,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, OUT_RING (chan, height); OUT_RING (chan, 0x00000101); OUT_RING (chan, 0x00000000); - BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); OUT_RING (chan, 0); length -= amount; @@ -660,7 +660,7 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); @@ -672,7 +672,7 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - BEGIN_RING(chan, NvSubM2MF, + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); OUT_RING (chan, src_offset); OUT_RING (chan, dst_offset); @@ -682,7 +682,7 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, OUT_RING (chan, line_count); OUT_RING (chan, 0x00000101); OUT_RING (chan, 0x00000000); - BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); OUT_RING (chan, 0); page_count -= line_count; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 4b1cf7457983..b670b0d34233 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -446,13 +446,13 @@ nouveau_page_flip_emit(struct nouveau_channel *chan, goto fail; if (dev_priv->card_type < NV_C0) { - BEGIN_RING(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); + BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); OUT_RING (chan, 0x00000000); OUT_RING (chan, 0x00000000); } else { - BEGIN_NVC0(chan, 2, 0, NV10_SUBCHAN_REF_CNT, 1); + BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1); OUT_RING (chan, ++chan->fence.sequence); - BEGIN_NVC0(chan, 8, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000); + BEGIN_IMC0(chan, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000); } FIRE_RING (chan); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index f776b6af9640..b8838592d4e9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -128,15 +128,33 @@ extern void OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); static inline void -BEGIN_NVC0(struct nouveau_channel *chan, int op, int subc, int mthd, int size) +BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) { - OUT_RING(chan, (op << 28) | (size << 16) | (subc << 13) | (mthd >> 2)); + OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); } static inline void -BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) +BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) { - OUT_RING(chan, (subc << 13) | (size << 18) | mthd); + OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); +} + +static inline void +BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) +{ + OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); +} + +static inline void +BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) +{ + OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); +} + +static inline void +BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) +{ + OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); } #define WRITE_PUT(val) do { \ diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 8113e9201ed9..bce2e73b9ebd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -171,14 +171,14 @@ nouveau_fbcon_sync(struct fb_info *info) } if (dev_priv->card_type >= NV_C0) { - BEGIN_NVC0(chan, 2, NvSub2D, 0x010c, 1); + BEGIN_NVC0(chan, NvSub2D, 0x010c, 1); OUT_RING (chan, 0); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0100, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0100, 1); OUT_RING (chan, 0); } else { - BEGIN_RING(chan, 0, 0x0104, 1); + BEGIN_NV04(chan, 0, 0x0104, 1); OUT_RING (chan, 0); - BEGIN_RING(chan, 0, 0x0100, 1); + BEGIN_NV04(chan, 0, 0x0100, 1); OUT_RING (chan, 0); } diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 965e3d2e8a7d..cb19bf447952 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -164,11 +164,11 @@ nouveau_fence_emit(struct nouveau_fence *fence) if (USE_REFCNT(dev)) { if (dev_priv->card_type < NV_C0) - BEGIN_RING(chan, 0, NV10_SUBCHAN_REF_CNT, 1); + BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); else - BEGIN_NVC0(chan, 2, 0, NV10_SUBCHAN_REF_CNT, 1); + BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1); } else { - BEGIN_RING(chan, NvSubSw, 0x0150, 1); + BEGIN_NV04(chan, NvSubSw, 0x0150, 1); } OUT_RING (chan, fence->sequence); FIRE_RING(chan); @@ -343,7 +343,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 3); + BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 3); OUT_RING (chan, NvSema); OUT_RING (chan, offset); OUT_RING (chan, 1); @@ -353,9 +353,9 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); + BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); OUT_RING (chan, chan->vram_handle); - BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); @@ -365,7 +365,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); @@ -396,10 +396,10 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); + BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); OUT_RING (chan, NvSema); OUT_RING (chan, offset); - BEGIN_RING(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); + BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); OUT_RING (chan, 1); } else if (dev_priv->chipset < 0xc0) { @@ -407,9 +407,9 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); + BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); OUT_RING (chan, chan->vram_handle); - BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); @@ -419,7 +419,7 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) if (ret) return ret; - BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); @@ -509,7 +509,7 @@ nouveau_fence_channel_init(struct nouveau_channel *chan) if (ret) return ret; - BEGIN_RING(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1); + BEGIN_NV04(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1); OUT_RING (chan, NvSw); FIRE_RING (chan); } diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 78fb2cbeea23..e76edb51373d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -639,9 +639,9 @@ nouveau_card_channel_init(struct drm_device *dev) if (ret) goto error; - BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); OUT_RING (chan, NvM2MF); - BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3); + BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3); OUT_RING (chan, NvNotify0); OUT_RING (chan, chan->vram_handle); OUT_RING (chan, chan->gart_handle); @@ -655,7 +655,7 @@ nouveau_card_channel_init(struct drm_device *dev) if (ret) goto error; - BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1); + BEGIN_NVC0(chan, NvSubM2MF, 0x0000, 1); OUT_RING (chan, 0x00009039); } else if (dev_priv->card_type <= NV_E0) { @@ -669,7 +669,7 @@ nouveau_card_channel_init(struct drm_device *dev) if (ret) goto error; - BEGIN_NVC0(chan, 2, NvSubCopy, 0x0000, 1); + BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); OUT_RING (chan, 0x0000a0b5); } diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 7a1189371096..7cd7857347ef 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -41,7 +41,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) if (ret) return ret; - BEGIN_RING(chan, NvSubImageBlit, 0x0300, 3); + BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3); OUT_RING(chan, (region->sy << 16) | region->sx); OUT_RING(chan, (region->dy << 16) | region->dx); OUT_RING(chan, (region->height << 16) | region->width); @@ -62,15 +62,15 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) if (ret) return ret; - BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); - BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); else OUT_RING(chan, rect->color); - BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2); + BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2); OUT_RING(chan, (rect->dx << 16) | rect->dy); OUT_RING(chan, (rect->width << 16) | rect->height); FIRE_RING(chan); @@ -110,7 +110,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) bg = image->bg_color; } - BEGIN_RING(chan, NvSubGdiRect, 0x0be4, 7); + BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7); OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); OUT_RING(chan, ((image->dy + image->height) << 16) | ((image->dx + image->width) & 0xffff)); @@ -127,7 +127,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) if (ret) return ret; - BEGIN_RING(chan, NvSubGdiRect, 0x0c00, iter_len); + BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len); OUT_RINGp(chan, data, iter_len); data += iter_len; dsize -= iter_len; @@ -209,25 +209,25 @@ nv04_fbcon_accel_init(struct fb_info *info) return 0; } - BEGIN_RING(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, sub, 0x0000, 1); OUT_RING(chan, NvCtxSurf2D); - BEGIN_RING(chan, sub, 0x0184, 2); + BEGIN_NV04(chan, sub, 0x0184, 2); OUT_RING(chan, NvDmaFB); OUT_RING(chan, NvDmaFB); - BEGIN_RING(chan, sub, 0x0300, 4); + BEGIN_NV04(chan, sub, 0x0300, 4); OUT_RING(chan, surface_fmt); OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); - BEGIN_RING(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, sub, 0x0000, 1); OUT_RING(chan, NvRop); - BEGIN_RING(chan, sub, 0x0300, 1); + BEGIN_NV04(chan, sub, 0x0300, 1); OUT_RING(chan, 0x55); - BEGIN_RING(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, sub, 0x0000, 1); OUT_RING(chan, NvImagePatt); - BEGIN_RING(chan, sub, 0x0300, 8); + BEGIN_NV04(chan, sub, 0x0300, 8); OUT_RING(chan, pattern_fmt); #ifdef __BIG_ENDIAN OUT_RING(chan, 2); @@ -241,31 +241,31 @@ nv04_fbcon_accel_init(struct fb_info *info) OUT_RING(chan, ~0); OUT_RING(chan, ~0); - BEGIN_RING(chan, sub, 0x0000, 1); + BEGIN_NV04(chan, sub, 0x0000, 1); OUT_RING(chan, NvClipRect); - BEGIN_RING(chan, sub, 0x0300, 2); + BEGIN_NV04(chan, sub, 0x0300, 2); OUT_RING(chan, 0); OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); - BEGIN_RING(chan, NvSubImageBlit, 0x0000, 1); + BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); OUT_RING(chan, NvImageBlit); - BEGIN_RING(chan, NvSubImageBlit, 0x019c, 1); + BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); OUT_RING(chan, NvCtxSurf2D); - BEGIN_RING(chan, NvSubImageBlit, 0x02fc, 1); + BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); OUT_RING(chan, 3); - BEGIN_RING(chan, NvSubGdiRect, 0x0000, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); OUT_RING(chan, NvGdiRect); - BEGIN_RING(chan, NvSubGdiRect, 0x0198, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); OUT_RING(chan, NvCtxSurf2D); - BEGIN_RING(chan, NvSubGdiRect, 0x0188, 2); + BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); OUT_RING(chan, NvImagePatt); OUT_RING(chan, NvRop); - BEGIN_RING(chan, NvSubGdiRect, 0x0304, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSubGdiRect, 0x0300, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); OUT_RING(chan, rect_fmt); - BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); + BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); OUT_RING(chan, 3); FIRE_RING(chan); diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index cad2abd11756..7eb3aa3b099e 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c @@ -79,15 +79,15 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) NV_ERROR(dev, "no space while blanking crtc\n"); return ret; } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); OUT_RING(evo, 0); if (dev_priv->chipset != 0x50) { - BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); + BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); } else { if (nv_crtc->cursor.visible) @@ -100,20 +100,20 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) NV_ERROR(dev, "no space while unblanking crtc\n"); return ret; } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); OUT_RING(evo, nv_crtc->lut.depth == 8 ? NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); if (dev_priv->chipset != 0x50) { - BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); + BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); OUT_RING(evo, NvEvoVRAM); } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); OUT_RING(evo, nv_crtc->fb.offset >> 8); OUT_RING(evo, 0); - BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); if (dev_priv->chipset != 0x50) if (nv_crtc->fb.tile_flags == 0x7a00 || nv_crtc->fb.tile_flags == 0xfe00) @@ -158,10 +158,10 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); if (ret == 0) { - BEGIN_RING(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1); OUT_RING (evo, mode); if (update) { - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING (evo, 0); FIRE_RING (evo); } @@ -193,11 +193,11 @@ nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); OUT_RING (evo, (hue << 20) | (vib << 8)); if (update) { - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING (evo, 0); FIRE_RING (evo); } @@ -311,9 +311,9 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) if (ret) return ret; - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); OUT_RING (evo, ctrl); - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); OUT_RING (evo, oY << 16 | oX); OUT_RING (evo, oY << 16 | oX); @@ -593,7 +593,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, if (ret) return ret; - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); OUT_RING (evo, fb->r_dma); } @@ -601,18 +601,18 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, if (ret) return ret; - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); OUT_RING (evo, nv_crtc->fb.offset >> 8); OUT_RING (evo, 0); OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); OUT_RING (evo, fb->r_pitch); OUT_RING (evo, fb->r_format); - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); OUT_RING (evo, fb->base.depth == 8 ? NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); OUT_RING (evo, (y << 16) | x); if (nv_crtc->lut.depth != fb->base.depth) { @@ -672,23 +672,23 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, ret = RING_SPACE(evo, 18); if (ret == 0) { - BEGIN_RING(evo, 0, 0x0804 + head, 2); + BEGIN_NV04(evo, 0, 0x0804 + head, 2); OUT_RING (evo, 0x00800000 | mode->clock); OUT_RING (evo, (ilace == 2) ? 2 : 0); - BEGIN_RING(evo, 0, 0x0810 + head, 6); + BEGIN_NV04(evo, 0, 0x0810 + head, 6); OUT_RING (evo, 0x00000000); /* border colour */ OUT_RING (evo, (vactive << 16) | hactive); OUT_RING (evo, ( vsynce << 16) | hsynce); OUT_RING (evo, (vblanke << 16) | hblanke); OUT_RING (evo, (vblanks << 16) | hblanks); OUT_RING (evo, (vblan2e << 16) | vblan2s); - BEGIN_RING(evo, 0, 0x082c + head, 1); + BEGIN_NV04(evo, 0, 0x082c + head, 1); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x0900 + head, 1); + BEGIN_NV04(evo, 0, 0x0900 + head, 1); OUT_RING (evo, 0x00000311); /* makes sync channel work */ - BEGIN_RING(evo, 0, 0x08c8 + head, 1); + BEGIN_NV04(evo, 0, 0x08c8 + head, 1); OUT_RING (evo, (umode->vdisplay << 16) | umode->hdisplay); - BEGIN_RING(evo, 0, 0x08d4 + head, 1); + BEGIN_NV04(evo, 0, 0x08d4 + head, 1); OUT_RING (evo, 0x00000000); /* screen position */ } diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c index adfc9b607a50..af4ec7bf3670 100644 --- a/drivers/gpu/drm/nouveau/nv50_cursor.c +++ b/drivers/gpu/drm/nouveau/nv50_cursor.c @@ -53,15 +53,15 @@ nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update) } if (dev_priv->chipset != 0x50) { - BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); + BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); OUT_RING(evo, NvEvoVRAM); } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_SHOW); OUT_RING(evo, nv_crtc->cursor.offset >> 8); if (update) { - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING(evo, 0); FIRE_RING(evo); nv_crtc->cursor.visible = true; @@ -86,16 +86,16 @@ nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) NV_ERROR(dev, "no space while hiding cursor\n"); return; } - BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); + BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE); OUT_RING(evo, 0); if (dev_priv->chipset != 0x50) { - BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); + BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE); } if (update) { - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING(evo, 0); FIRE_RING(evo); nv_crtc->cursor.visible = false; diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c index 55c56330be6d..eb216a446b89 100644 --- a/drivers/gpu/drm/nouveau/nv50_dac.c +++ b/drivers/gpu/drm/nouveau/nv50_dac.c @@ -55,9 +55,9 @@ nv50_dac_disconnect(struct drm_encoder *encoder) NV_ERROR(dev, "no space while disconnecting DAC\n"); return; } - BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1); OUT_RING (evo, 0); - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING (evo, 0); nv_encoder->crtc = NULL; @@ -240,7 +240,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, NV_ERROR(dev, "no space while connecting DAC\n"); return; } - BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2); + BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2); OUT_RING(evo, mode_ctl); OUT_RING(evo, mode_ctl2); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 8b78b9cfa383..211e5e9565ce 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -140,11 +140,11 @@ nv50_display_sync(struct drm_device *dev) ret = RING_SPACE(evo, 6); if (ret == 0) { - BEGIN_RING(evo, 0, 0x0084, 1); + BEGIN_NV04(evo, 0, 0x0084, 1); OUT_RING (evo, 0x80000000); - BEGIN_RING(evo, 0, 0x0080, 1); + BEGIN_NV04(evo, 0, 0x0080, 1); OUT_RING (evo, 0); - BEGIN_RING(evo, 0, 0x0084, 1); + BEGIN_NV04(evo, 0, 0x0084, 1); OUT_RING (evo, 0x00000000); nv_wo32(disp->ntfy, 0x000, 0x00000000); @@ -267,7 +267,7 @@ nv50_display_init(struct drm_device *dev) ret = RING_SPACE(evo, 3); if (ret) return ret; - BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2); + BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2); OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); OUT_RING (evo, NvEvoSync); @@ -292,7 +292,7 @@ nv50_display_fini(struct drm_device *dev) ret = RING_SPACE(evo, 2); if (ret == 0) { - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING(evo, 0); } FIRE_RING(evo); @@ -438,13 +438,13 @@ nv50_display_flip_stop(struct drm_crtc *crtc) return; } - BEGIN_RING(evo, 0, 0x0084, 1); + BEGIN_NV04(evo, 0, 0x0084, 1); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x0094, 1); + BEGIN_NV04(evo, 0, 0x0094, 1); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x00c0, 1); + BEGIN_NV04(evo, 0, 0x00c0, 1); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x0080, 1); + BEGIN_NV04(evo, 0, 0x0080, 1); OUT_RING (evo, 0x00000000); FIRE_RING (evo); } @@ -474,15 +474,15 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, } if (dev_priv->chipset < 0xc0) { - BEGIN_RING(chan, 0, 0x0060, 2); + BEGIN_NV04(chan, 0, 0x0060, 2); OUT_RING (chan, NvEvoSema0 + nv_crtc->index); OUT_RING (chan, dispc->sem.offset); - BEGIN_RING(chan, 0, 0x006c, 1); + BEGIN_NV04(chan, 0, 0x006c, 1); OUT_RING (chan, 0xf00d0000 | dispc->sem.value); - BEGIN_RING(chan, 0, 0x0064, 2); + BEGIN_NV04(chan, 0, 0x0064, 2); OUT_RING (chan, dispc->sem.offset ^ 0x10); OUT_RING (chan, 0x74b1e000); - BEGIN_RING(chan, 0, 0x0060, 1); + BEGIN_NV04(chan, 0, 0x0060, 1); if (dev_priv->chipset < 0x84) OUT_RING (chan, NvSema); else @@ -490,12 +490,12 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, } else { u64 offset = chan->dispc_vma[nv_crtc->index].offset; offset += dispc->sem.offset; - BEGIN_NVC0(chan, 2, 0, 0x0010, 4); + BEGIN_NVC0(chan, 0, 0x0010, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 0xf00d0000 | dispc->sem.value); OUT_RING (chan, 0x1002); - BEGIN_NVC0(chan, 2, 0, 0x0010, 4); + BEGIN_NVC0(chan, 0, 0x0010, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset ^ 0x10)); OUT_RING (chan, 0x74b1e000); @@ -508,40 +508,40 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, } /* queue the flip on the crtc's "display sync" channel */ - BEGIN_RING(evo, 0, 0x0100, 1); + BEGIN_NV04(evo, 0, 0x0100, 1); OUT_RING (evo, 0xfffe0000); if (chan) { - BEGIN_RING(evo, 0, 0x0084, 1); + BEGIN_NV04(evo, 0, 0x0084, 1); OUT_RING (evo, 0x00000100); } else { - BEGIN_RING(evo, 0, 0x0084, 1); + BEGIN_NV04(evo, 0, 0x0084, 1); OUT_RING (evo, 0x00000010); /* allows gamma somehow, PDISP will bitch at you if * you don't wait for vblank before changing this.. */ - BEGIN_RING(evo, 0, 0x00e0, 1); + BEGIN_NV04(evo, 0, 0x00e0, 1); OUT_RING (evo, 0x40000000); } - BEGIN_RING(evo, 0, 0x0088, 4); + BEGIN_NV04(evo, 0, 0x0088, 4); OUT_RING (evo, dispc->sem.offset); OUT_RING (evo, 0xf00d0000 | dispc->sem.value); OUT_RING (evo, 0x74b1e000); OUT_RING (evo, NvEvoSync); - BEGIN_RING(evo, 0, 0x00a0, 2); + BEGIN_NV04(evo, 0, 0x00a0, 2); OUT_RING (evo, 0x00000000); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x00c0, 1); + BEGIN_NV04(evo, 0, 0x00c0, 1); OUT_RING (evo, nv_fb->r_dma); - BEGIN_RING(evo, 0, 0x0110, 2); + BEGIN_NV04(evo, 0, 0x0110, 2); OUT_RING (evo, 0x00000000); OUT_RING (evo, 0x00000000); - BEGIN_RING(evo, 0, 0x0800, 5); + BEGIN_NV04(evo, 0, 0x0800, 5); OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8); OUT_RING (evo, 0); OUT_RING (evo, (fb->height << 16) | fb->width); OUT_RING (evo, nv_fb->r_pitch); OUT_RING (evo, nv_fb->r_format); - BEGIN_RING(evo, 0, 0x0080, 1); + BEGIN_NV04(evo, 0, 0x0080, 1); OUT_RING (evo, 0x00000000); FIRE_RING (evo); diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index dc75a7206524..61747e0d1180 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -43,22 +43,22 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) return ret; if (rect->rop != ROP_COPY) { - BEGIN_RING(chan, NvSub2D, 0x02ac, 1); + BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); OUT_RING(chan, 1); } - BEGIN_RING(chan, NvSub2D, 0x0588, 1); + BEGIN_NV04(chan, NvSub2D, 0x0588, 1); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); else OUT_RING(chan, rect->color); - BEGIN_RING(chan, NvSub2D, 0x0600, 4); + BEGIN_NV04(chan, NvSub2D, 0x0600, 4); OUT_RING(chan, rect->dx); OUT_RING(chan, rect->dy); OUT_RING(chan, rect->dx + rect->width); OUT_RING(chan, rect->dy + rect->height); if (rect->rop != ROP_COPY) { - BEGIN_RING(chan, NvSub2D, 0x02ac, 1); + BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); OUT_RING(chan, 3); } FIRE_RING(chan); @@ -78,14 +78,14 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) if (ret) return ret; - BEGIN_RING(chan, NvSub2D, 0x0110, 1); + BEGIN_NV04(chan, NvSub2D, 0x0110, 1); OUT_RING(chan, 0); - BEGIN_RING(chan, NvSub2D, 0x08b0, 4); + BEGIN_NV04(chan, NvSub2D, 0x08b0, 4); OUT_RING(chan, region->dx); OUT_RING(chan, region->dy); OUT_RING(chan, region->width); OUT_RING(chan, region->height); - BEGIN_RING(chan, NvSub2D, 0x08d0, 4); + BEGIN_NV04(chan, NvSub2D, 0x08d0, 4); OUT_RING(chan, 0); OUT_RING(chan, region->sx); OUT_RING(chan, 0); @@ -116,7 +116,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) width = ALIGN(image->width, 32); dwords = (width * image->height) >> 5; - BEGIN_RING(chan, NvSub2D, 0x0814, 2); + BEGIN_NV04(chan, NvSub2D, 0x0814, 2); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) { OUT_RING(chan, palette[image->bg_color] | mask); @@ -125,10 +125,10 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) OUT_RING(chan, image->bg_color); OUT_RING(chan, image->fg_color); } - BEGIN_RING(chan, NvSub2D, 0x0838, 2); + BEGIN_NV04(chan, NvSub2D, 0x0838, 2); OUT_RING(chan, image->width); OUT_RING(chan, image->height); - BEGIN_RING(chan, NvSub2D, 0x0850, 4); + BEGIN_NV04(chan, NvSub2D, 0x0850, 4); OUT_RING(chan, 0); OUT_RING(chan, image->dx); OUT_RING(chan, 0); @@ -143,7 +143,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) dwords -= push; - BEGIN_RING(chan, NvSub2D, 0x40000860, push); + BEGIN_NI04(chan, NvSub2D, 0x0860, push); OUT_RINGp(chan, data, push); data += push; } @@ -199,60 +199,60 @@ nv50_fbcon_accel_init(struct fb_info *info) return ret; } - BEGIN_RING(chan, NvSub2D, 0x0000, 1); + BEGIN_NV04(chan, NvSub2D, 0x0000, 1); OUT_RING(chan, Nv2D); - BEGIN_RING(chan, NvSub2D, 0x0180, 4); + BEGIN_NV04(chan, NvSub2D, 0x0180, 4); OUT_RING(chan, NvNotify0); OUT_RING(chan, chan->vram_handle); OUT_RING(chan, chan->vram_handle); OUT_RING(chan, chan->vram_handle); - BEGIN_RING(chan, NvSub2D, 0x0290, 1); + BEGIN_NV04(chan, NvSub2D, 0x0290, 1); OUT_RING(chan, 0); - BEGIN_RING(chan, NvSub2D, 0x0888, 1); + BEGIN_NV04(chan, NvSub2D, 0x0888, 1); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x02ac, 1); + BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); OUT_RING(chan, 3); - BEGIN_RING(chan, NvSub2D, 0x02a0, 1); + BEGIN_NV04(chan, NvSub2D, 0x02a0, 1); OUT_RING(chan, 0x55); - BEGIN_RING(chan, NvSub2D, 0x08c0, 4); + BEGIN_NV04(chan, NvSub2D, 0x08c0, 4); OUT_RING(chan, 0); OUT_RING(chan, 1); OUT_RING(chan, 0); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0580, 2); + BEGIN_NV04(chan, NvSub2D, 0x0580, 2); OUT_RING(chan, 4); OUT_RING(chan, format); - BEGIN_RING(chan, NvSub2D, 0x02e8, 2); + BEGIN_NV04(chan, NvSub2D, 0x02e8, 2); OUT_RING(chan, 2); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0804, 1); + BEGIN_NV04(chan, NvSub2D, 0x0804, 1); OUT_RING(chan, format); - BEGIN_RING(chan, NvSub2D, 0x0800, 1); + BEGIN_NV04(chan, NvSub2D, 0x0800, 1); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0808, 3); + BEGIN_NV04(chan, NvSub2D, 0x0808, 3); OUT_RING(chan, 0); OUT_RING(chan, 0); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x081c, 1); + BEGIN_NV04(chan, NvSub2D, 0x081c, 1); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0840, 4); + BEGIN_NV04(chan, NvSub2D, 0x0840, 4); OUT_RING(chan, 0); OUT_RING(chan, 1); OUT_RING(chan, 0); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0200, 2); + BEGIN_NV04(chan, NvSub2D, 0x0200, 2); OUT_RING(chan, format); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0214, 5); + BEGIN_NV04(chan, NvSub2D, 0x0214, 5); OUT_RING(chan, info->fix.line_length); OUT_RING(chan, info->var.xres_virtual); OUT_RING(chan, info->var.yres_virtual); OUT_RING(chan, upper_32_bits(fb->vma.offset)); OUT_RING(chan, lower_32_bits(fb->vma.offset)); - BEGIN_RING(chan, NvSub2D, 0x0230, 2); + BEGIN_NV04(chan, NvSub2D, 0x0230, 2); OUT_RING(chan, format); OUT_RING(chan, 1); - BEGIN_RING(chan, NvSub2D, 0x0244, 5); + BEGIN_NV04(chan, NvSub2D, 0x0244, 5); OUT_RING(chan, info->fix.line_length); OUT_RING(chan, info->var.xres_virtual); OUT_RING(chan, info->var.yres_virtual); diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index 274640212475..a9514eaa74c1 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c @@ -242,9 +242,9 @@ nv50_sor_disconnect(struct drm_encoder *encoder) NV_ERROR(dev, "no space while disconnecting SOR\n"); return; } - BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); OUT_RING (evo, 0); - BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); + BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING (evo, 0); nouveau_hdmi_mode_set(encoder, NULL); @@ -430,7 +430,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, nv_encoder->crtc = NULL; return; } - BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); + BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); OUT_RING(evo, mode_ctl); } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index a495e48197ca..797159e7b7a6 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -43,22 +43,22 @@ nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) return ret; if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1); + BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); OUT_RING (chan, 1); } - BEGIN_NVC0(chan, 2, NvSub2D, 0x0588, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0588, 1); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); else OUT_RING (chan, rect->color); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0600, 4); + BEGIN_NVC0(chan, NvSub2D, 0x0600, 4); OUT_RING (chan, rect->dx); OUT_RING (chan, rect->dy); OUT_RING (chan, rect->dx + rect->width); OUT_RING (chan, rect->dy + rect->height); if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1); + BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); OUT_RING (chan, 3); } FIRE_RING(chan); @@ -78,14 +78,14 @@ nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) if (ret) return ret; - BEGIN_NVC0(chan, 2, NvSub2D, 0x0110, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0110, 1); OUT_RING (chan, 0); - BEGIN_NVC0(chan, 2, NvSub2D, 0x08b0, 4); + BEGIN_NVC0(chan, NvSub2D, 0x08b0, 4); OUT_RING (chan, region->dx); OUT_RING (chan, region->dy); OUT_RING (chan, region->width); OUT_RING (chan, region->height); - BEGIN_NVC0(chan, 2, NvSub2D, 0x08d0, 4); + BEGIN_NVC0(chan, NvSub2D, 0x08d0, 4); OUT_RING (chan, 0); OUT_RING (chan, region->sx); OUT_RING (chan, 0); @@ -116,7 +116,7 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) width = ALIGN(image->width, 32); dwords = (width * image->height) >> 5; - BEGIN_NVC0(chan, 2, NvSub2D, 0x0814, 2); + BEGIN_NVC0(chan, NvSub2D, 0x0814, 2); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) { OUT_RING (chan, palette[image->bg_color] | mask); @@ -125,10 +125,10 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) OUT_RING (chan, image->bg_color); OUT_RING (chan, image->fg_color); } - BEGIN_NVC0(chan, 2, NvSub2D, 0x0838, 2); + BEGIN_NVC0(chan, NvSub2D, 0x0838, 2); OUT_RING (chan, image->width); OUT_RING (chan, image->height); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0850, 4); + BEGIN_NVC0(chan, NvSub2D, 0x0850, 4); OUT_RING (chan, 0); OUT_RING (chan, image->dx); OUT_RING (chan, 0); @@ -143,7 +143,7 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) dwords -= push; - BEGIN_NVC0(chan, 6, NvSub2D, 0x0860, push); + BEGIN_NIC0(chan, NvSub2D, 0x0860, push); OUT_RINGp(chan, data, push); data += push; } @@ -200,47 +200,47 @@ nvc0_fbcon_accel_init(struct fb_info *info) return ret; } - BEGIN_NVC0(chan, 2, NvSub2D, 0x0000, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); OUT_RING (chan, 0x0000902d); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0104, 2); + BEGIN_NVC0(chan, NvSub2D, 0x0104, 2); OUT_RING (chan, upper_32_bits(chan->notifier_vma.offset)); OUT_RING (chan, lower_32_bits(chan->notifier_vma.offset)); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0290, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); OUT_RING (chan, 0); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0888, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1); + BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); OUT_RING (chan, 3); - BEGIN_NVC0(chan, 2, NvSub2D, 0x02a0, 1); + BEGIN_NVC0(chan, NvSub2D, 0x02a0, 1); OUT_RING (chan, 0x55); - BEGIN_NVC0(chan, 2, NvSub2D, 0x08c0, 4); + BEGIN_NVC0(chan, NvSub2D, 0x08c0, 4); OUT_RING (chan, 0); OUT_RING (chan, 1); OUT_RING (chan, 0); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0580, 2); + BEGIN_NVC0(chan, NvSub2D, 0x0580, 2); OUT_RING (chan, 4); OUT_RING (chan, format); - BEGIN_NVC0(chan, 2, NvSub2D, 0x02e8, 2); + BEGIN_NVC0(chan, NvSub2D, 0x02e8, 2); OUT_RING (chan, 2); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0804, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0804, 1); OUT_RING (chan, format); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0800, 1); + BEGIN_NVC0(chan, NvSub2D, 0x0800, 1); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0808, 3); + BEGIN_NVC0(chan, NvSub2D, 0x0808, 3); OUT_RING (chan, 0); OUT_RING (chan, 0); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x081c, 1); + BEGIN_NVC0(chan, NvSub2D, 0x081c, 1); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0840, 4); + BEGIN_NVC0(chan, NvSub2D, 0x0840, 4); OUT_RING (chan, 0); OUT_RING (chan, 1); OUT_RING (chan, 0); OUT_RING (chan, 1); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0200, 10); + BEGIN_NVC0(chan, NvSub2D, 0x0200, 10); OUT_RING (chan, format); OUT_RING (chan, 1); OUT_RING (chan, 0); @@ -251,7 +251,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) OUT_RING (chan, info->var.yres_virtual); OUT_RING (chan, upper_32_bits(fb->vma.offset)); OUT_RING (chan, lower_32_bits(fb->vma.offset)); - BEGIN_NVC0(chan, 2, NvSub2D, 0x0230, 10); + BEGIN_NVC0(chan, NvSub2D, 0x0230, 10); OUT_RING (chan, format); OUT_RING (chan, 1); OUT_RING (chan, 0); diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c index 1f3a9b1240e8..ccc20dc1b6cb 100644 --- a/drivers/gpu/drm/nouveau/nvd0_display.c +++ b/drivers/gpu/drm/nouveau/nvd0_display.c @@ -303,12 +303,12 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, offset = chan->dispc_vma[nv_crtc->index].offset; offset += evo->sem.offset; - BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 0xf00d0000 | evo->sem.value); OUT_RING (chan, 0x1002); - BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset ^ 0x10)); OUT_RING (chan, 0x74b1e000);