From: Sonny Rao Date: Wed, 19 Nov 2014 07:15:19 +0000 (-0800) Subject: clk: rockchip: rk3288 export i2s0_clkout for use in DT X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6d288b169bdfbed28d308b077af3d9196025cd8b;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git clk: rockchip: rk3288 export i2s0_clkout for use in DT This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by: Sonny Rao [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 232809725c55..a43045b05d98 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -308,7 +308,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(4), 2, GFLAGS), MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0, + COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 8e19ed58db33..edf011039b07 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -71,6 +71,7 @@ #define SCLK_HDMI_CEC 110 #define SCLK_HEVC_CABAC 111 #define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 #define DCLK_VOP0 190 #define DCLK_VOP1 191