From: Eugeni Dodonov Date: Wed, 9 May 2012 18:37:23 +0000 (-0300) Subject: drm/i915: define Haswell watermarks and clock gating X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6b8a5eeb9f428becc88adef148518ed07bf06d02;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915: define Haswell watermarks and clock gating For now, we simple reuse the Ivy Bridge routines here. Signed-off-by: Eugeni Dodonov Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bd9549de4a3b..452a9bce8162 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3685,6 +3685,17 @@ void intel_init_pm(struct drm_device *dev) } dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; dev_priv->display.sanitize_pm = gen6_sanitize_pm; + } else if (IS_HASWELL(dev)) { + if (SNB_READ_WM0_LATENCY()) { + dev_priv->display.update_wm = sandybridge_update_wm; + dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; + } else { + DRM_DEBUG_KMS("Failed to read display plane latency. " + "Disable CxSR\n"); + dev_priv->display.update_wm = NULL; + } + dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; + dev_priv->display.sanitize_pm = gen6_sanitize_pm; } else dev_priv->display.update_wm = NULL; } else if (IS_VALLEYVIEW(dev)) {