From: Matt Roper Date: Thu, 12 May 2016 14:06:10 +0000 (-0700) Subject: drm/i915/gen9: Reject display updates that exceed wm limitations (v2) X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6b6bada7d476b586d85b1f9df43125804877e09f;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915/gen9: Reject display updates that exceed wm limitations (v2) If we can't find any valid level 0 watermark values for the requested atomic transaction, reject the configuration before we try to start programming the hardware. v2: - Add extra debugging output when we reject level 0 watermarks so that we can more easily debug how/why they were rejected. Cc: Lyude Paul Signed-off-by: Matt Roper Reviewed-by: Maarten Lankhorst Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-17-git-send-email-matthew.d.roper@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f9dff5e2e0e7..fcf925b31575 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3306,7 +3306,22 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (res_blocks >= ddb_allocation || res_lines > 31) { *enabled = false; - return 0; + + /* + * If there are no valid level 0 watermarks, then we can't + * support this display configuration. + */ + if (level) { + return 0; + } else { + DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); + DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n", + to_intel_crtc(cstate->base.crtc)->pipe, + skl_wm_plane_id(to_intel_plane(pstate->plane)), + res_blocks, ddb_allocation, res_lines); + + return -EINVAL; + } } *out_blocks = res_blocks;