From: Daniel Vetter Date: Sat, 20 Oct 2012 18:57:44 +0000 (+0200) Subject: drm/i915/dp: compute the pch dp aux divider from the rawclk X-Git-Tag: MMI-PSA29.97-13-9~15304^2~193^2~134 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6b3ec1c9fb73cca38842d030b171ffd16a686949;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git drm/i915/dp: compute the pch dp aux divider from the rawclk Otherwise dp aux won't work on some hsw platforms, since they use a different rawclk than the 125MHz clock used thus far. To absolutely not change anything, round up: That way we get the old 63 divider for the default 125MHz clock. Reviewed-by: Jesse Barnes Tested-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index adfb98cb7ba9..c1ed1aff2750 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -377,7 +377,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else aux_clock_divider = 225; /* eDP input clock at 450Mhz */ } else if (HAS_PCH_SPLIT(dev)) - aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ + aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); else aux_clock_divider = intel_hrawclk(dev) / 2;