From: Russell King Date: Tue, 18 Jun 2013 16:20:32 +0000 (+0100) Subject: Watchdog: fix clearing of the watchdog interrupt X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6910ceb5cababfefffc4ddc58a085a71c0ab9f22;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Watchdog: fix clearing of the watchdog interrupt The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to clear. If we read the register, mask off the watchdog bit, and write it back, we're actually clearing every interrupt which wasn't pending at the time we read the register - and that is racy. Fix this to only write ~WATCHDOG_BIT to the register, which means we write as zero only the watchdog bit. Signed-off-by: Russell King Acked-by: Jason Cooper Tested-by: Andrew Lunn Signed-off-by: Wim Van Sebroeck --- diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4074244c7183..4ea5fcccac02 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -70,9 +70,7 @@ static int orion_wdt_start(struct watchdog_device *wdt_dev) writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); /* Clear watchdog timer interrupt */ - reg = readl(BRIDGE_CAUSE); - reg &= ~WDT_INT_REQ; - writel(reg, BRIDGE_CAUSE); + writel(~WDT_INT_REQ, BRIDGE_CAUSE); /* Enable watchdog timer */ reg = readl(wdt_reg + TIMER_CTRL);