From: Russell King Date: Sun, 17 Apr 2005 14:51:02 +0000 (+0100) Subject: [PATCH] ARM: bitops X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=684f970e2fd2dc0eb8292500903f54f1ebda0e75;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git [PATCH] ARM: bitops Convert ARM bitop assembly to a macro. All bitops follow the same format, so it's silly duplicating the code when only one or two instructions are different. Signed-off-by: Russell King --- diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S index 3af45cab70e1..389567c24090 100644 --- a/arch/arm/lib/changebit.S +++ b/arch/arm/lib/changebit.S @@ -9,6 +9,7 @@ */ #include #include +#include "bitops.h" .text /* Purpose : Function to change a bit @@ -17,12 +18,4 @@ ENTRY(_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_change_bit_le) - and r2, r0, #7 - mov r3, #1 - mov r3, r3, lsl r2 - save_and_disable_irqs ip, r2 - ldrb r2, [r1, r0, lsr #3] - eor r2, r2, r3 - strb r2, [r1, r0, lsr #3] - restore_irqs ip - RETINSTR(mov,pc,lr) + bitop eor diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S index 069a2ce413f0..347516533025 100644 --- a/arch/arm/lib/clearbit.S +++ b/arch/arm/lib/clearbit.S @@ -9,6 +9,7 @@ */ #include #include +#include "bitops.h" .text /* @@ -18,14 +19,4 @@ ENTRY(_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_clear_bit_le) - and r2, r0, #7 - mov r3, #1 - mov r3, r3, lsl r2 - save_and_disable_irqs ip, r2 - ldrb r2, [r1, r0, lsr #3] - bic r2, r2, r3 - strb r2, [r1, r0, lsr #3] - restore_irqs ip - RETINSTR(mov,pc,lr) - - + bitop bic diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S index 8f337df5d99b..83bc23d5b037 100644 --- a/arch/arm/lib/setbit.S +++ b/arch/arm/lib/setbit.S @@ -9,6 +9,7 @@ */ #include #include +#include "bitops.h" .text /* @@ -18,12 +19,4 @@ ENTRY(_set_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_set_bit_le) - and r2, r0, #7 - mov r3, #1 - mov r3, r3, lsl r2 - save_and_disable_irqs ip, r2 - ldrb r2, [r1, r0, lsr #3] - orr r2, r2, r3 - strb r2, [r1, r0, lsr #3] - restore_irqs ip - RETINSTR(mov,pc,lr) + bitop orr diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S index 4aba4676b984..b25dcd2be53e 100644 --- a/arch/arm/lib/testchangebit.S +++ b/arch/arm/lib/testchangebit.S @@ -9,21 +9,10 @@ */ #include #include +#include "bitops.h" .text ENTRY(_test_and_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_change_bit_le) - add r1, r1, r0, lsr #3 - and r3, r0, #7 - mov r0, #1 - save_and_disable_irqs ip, r2 - ldrb r2, [r1] - tst r2, r0, lsl r3 - eor r2, r2, r0, lsl r3 - strb r2, [r1] - restore_irqs ip - moveq r0, #0 - RETINSTR(mov,pc,lr) - - + testop eor, strb diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S index e07c5bd24307..2dcc4b16b68e 100644 --- a/arch/arm/lib/testclearbit.S +++ b/arch/arm/lib/testclearbit.S @@ -9,21 +9,10 @@ */ #include #include +#include "bitops.h" .text ENTRY(_test_and_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_clear_bit_le) - add r1, r1, r0, lsr #3 @ Get byte offset - and r3, r0, #7 @ Get bit offset - mov r0, #1 - save_and_disable_irqs ip, r2 - ldrb r2, [r1] - tst r2, r0, lsl r3 - bic r2, r2, r0, lsl r3 - strb r2, [r1] - restore_irqs ip - moveq r0, #0 - RETINSTR(mov,pc,lr) - - + testop bicne, strneb diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S index a570fc74cddd..9011c969761a 100644 --- a/arch/arm/lib/testsetbit.S +++ b/arch/arm/lib/testsetbit.S @@ -9,21 +9,10 @@ */ #include #include +#include "bitops.h" .text ENTRY(_test_and_set_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_set_bit_le) - add r1, r1, r0, lsr #3 @ Get byte offset - and r3, r0, #7 @ Get bit offset - mov r0, #1 - save_and_disable_irqs ip, r2 - ldrb r2, [r1] - tst r2, r0, lsl r3 - orr r2, r2, r0, lsl r3 - strb r2, [r1] - restore_irqs ip - moveq r0, #0 - RETINSTR(mov,pc,lr) - - + testop orreq, streqb