From: Atsushi Nemoto Date: Tue, 4 Apr 2006 08:34:14 +0000 (+0900) Subject: [MIPS] Fix tx49_blast_icache32_page_indexed. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=67a3f6de939a5f52e0aea6dcff7778d4bcca0734;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git [MIPS] Fix tx49_blast_icache32_page_indexed. Fix the cache index value in tx49_blast_icache32_page_indexed(). This is a damage by de62893bc0725f8b5f0445250577cd7a10b2d8f8 commit. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 32b7f6aeb983..c4c208449d87 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -154,7 +154,8 @@ static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) static inline void tx49_blast_icache32_page_indexed(unsigned long page) { - unsigned long start = page; + unsigned long indexmask = current_cpu_data.icache.waysize - 1; + unsigned long start = INDEX_BASE + (page & indexmask); unsigned long end = start + PAGE_SIZE; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways <<