From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 3 Apr 2006 22:32:39 +0000 (+0100)
Subject: [MIPS] Use "R" constraint for cache_op.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=675055bfb5f99be56a20a6a214439adf23591786;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[MIPS] Use "R" constraint for cache_op.

Gcc might emit an absolute address for the the "m" constraint which
gas unfortunately does not permit.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 90c374700977..2f2eb95387f6 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -37,7 +37,7 @@
 	"	cache	%0, %1					\n"	\
 	"	.set	pop					\n"	\
 	:								\
-	: "i" (op), "m" (*(unsigned char *)(addr)))
+	: "i" (op), "R" (*(unsigned char *)(addr)))
 
 static inline void flush_icache_line_indexed(unsigned long addr)
 {