From: Jiyu Yang Date: Fri, 4 Dec 2015 03:29:19 +0000 (+0800) Subject: PD#115943 905m clk check X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=6582173f9345bcc585215909c00b100412250e92;p=GitHub%2FLineageOS%2FG12%2Fandroid_hardware_amlogic_kernel-modules_mali-driver.git PD#115943 905m clk check Change-Id: I27f84e943d3425316e5ac630bc1a6c63e48cf789 --- diff --git a/mali/platform/meson_bu/mali_clock.c b/mali/platform/meson_bu/mali_clock.c index 1f526cd..3f15dc3 100644 --- a/mali/platform/meson_bu/mali_clock.c +++ b/mali/platform/meson_bu/mali_clock.c @@ -4,12 +4,14 @@ #include #include #include +#include #include "mali_scaling.h" #include "mali_clock.h" #ifndef AML_CLK_LOCK_ERROR #define AML_CLK_LOCK_ERROR 1 #endif +#define GXBBM_MAX_GPU_FREQ 700000000UL static unsigned gpu_dbg_level = 0; module_param(gpu_dbg_level, uint, 0644); @@ -26,6 +28,9 @@ MODULE_PARM_DESC(gpu_dbg_level, "gpu debug level"); gpu_dbg(1, "line(%d), clk_cntl=0x%08x\n" fmt, __LINE__, mplt_read(HHI_MALI_CLK_CNTL), ## arg);\ } while (0) +//disable print +#define _dev_info(...) + //static DEFINE_SPINLOCK(lock); static mali_plat_info_t* pmali_plat = NULL; //static u32 mali_extr_backup = 0; @@ -249,35 +254,7 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) of_get_property(gpu_dn, "tbl", &length); length = length /sizeof(u32); - _dev_info(&pdev->dev, "clock dvfs table size is %d\n", length); - - ret = of_property_read_u32(gpu_dn,"max_clk", - &mpdata->cfg_clock); - if (ret) { - dev_notice(&pdev->dev, "max clk set %d\n", length-2); - mpdata->cfg_clock = length-2; - } - - mpdata->maxclk_sysfs = mpdata->cfg_clock; - mpdata->cfg_clock_bkup = mpdata->cfg_clock; - mpdata->scale_info.maxclk = mpdata->cfg_clock; - _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk); - - ret = of_property_read_u32(gpu_dn,"turbo_clk", - &mpdata->turbo_clock); - if (ret) { - dev_notice(&pdev->dev, "turbo clk set to %d\n", length-1); - mpdata->turbo_clock = length-1; - } - _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock); - - ret = of_property_read_u32(gpu_dn,"def_clk", - &mpdata->def_clock); - if (ret) { - dev_notice(&pdev->dev, "default clk set to %d\n", length/2-1); - mpdata->def_clock = length/2 - 1; - } - _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock); + _dev_info(&pdev->dev, "clock dvfs cfg table size is %d\n", length); mpdata->dvfs_table = devm_kzalloc(&pdev->dev, sizeof(struct mali_dvfs_threshold_table)*length, @@ -287,7 +264,6 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) dev_err(&pdev->dev, "failed to alloc dvfs table\n"); return -ENOMEM; } - mpdata->dvfs_table_size = length; mpdata->clk_sample = devm_kzalloc(&pdev->dev, sizeof(u32)*length, GFP_KERNEL); if (mpdata->clk_sample == NULL) { dev_err(&pdev->dev, "failed to alloc clk_sample table\n"); @@ -302,7 +278,6 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) } clk_item = mpdata->clk_items; // - of_property_for_each_u32(gpu_dn, "tbl", prop, p, u) { dvfs_clk_hdl = (phandle) u; gpu_clk_dn = of_find_node_by_phandle(dvfs_clk_hdl); @@ -310,6 +285,12 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) if (ret) { dev_notice(&pdev->dev, "read clk_freq failed\n"); } +#ifdef MESON_CPU_VERSION_OPS + if (is_meson_gxbbm_cpu()) { + if (dvfs_tbl->clk_freq >= GXBBM_MAX_GPU_FREQ) + continue; + } +#endif ret = of_property_read_string(gpu_clk_dn,"clk_parent", &dvfs_tbl->clk_parent); if (ret) { @@ -347,11 +328,40 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) clk_item ++; clk_sample ++; i++; + mpdata->dvfs_table_size ++; + } + + ret = of_property_read_u32(gpu_dn,"max_clk", + &mpdata->cfg_clock); + if (ret) { + dev_notice(&pdev->dev, "max clk set %d\n", mpdata->dvfs_table_size-2); + mpdata->cfg_clock = mpdata->dvfs_table_size-2; + } + + mpdata->cfg_clock_bkup = mpdata->cfg_clock; + mpdata->maxclk_sysfs = mpdata->cfg_clock; + mpdata->scale_info.maxclk = mpdata->cfg_clock; + _dev_info(&pdev->dev, "max clk is %d\n", mpdata->scale_info.maxclk); + + ret = of_property_read_u32(gpu_dn,"turbo_clk", + &mpdata->turbo_clock); + if (ret) { + dev_notice(&pdev->dev, "turbo clk set to %d\n", mpdata->dvfs_table_size-1); + mpdata->turbo_clock = mpdata->dvfs_table_size-1; + } + _dev_info(&pdev->dev, "turbo clk is %d\n", mpdata->turbo_clock); + + ret = of_property_read_u32(gpu_dn,"def_clk", + &mpdata->def_clock); + if (ret) { + dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1); + mpdata->def_clock = mpdata->dvfs_table_size/2 - 1; } + _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock); dvfs_tbl = mpdata->dvfs_table; clk_sample = mpdata->clk_sample; - for (i = 0; i< length; i++) { + for (i = 0; i< mpdata->dvfs_table_size; i++) { _dev_info(&pdev->dev, "====================%d====================\n" "clk_freq=%10d, clk_parent=%9s, voltage=%d, keep_count=%d, threshod=<%d %d>, clk_sample=%d\n", i, @@ -361,6 +371,7 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) dvfs_tbl ++; clk_sample ++; } + _dev_info(&pdev->dev, "clock dvfs table size is %d\n", mpdata->dvfs_table_size); mpdata->clk_mali = devm_clk_get(&pdev->dev, "clk_mali"); mpdata->clk_mali_0 = devm_clk_get(&pdev->dev, "clk_mali_0");