From: Ville Syrjälä Date: Tue, 27 May 2014 13:32:55 +0000 (+0300) Subject: drm/i915/chv: Force PHY clock buffers off after PLL disable X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=61407f6dd3c75ab900d52da4c29f9a52ed6b2acc;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915/chv: Force PHY clock buffers off after PLL disable Now that we forced the clock buffers on in .pre_pll_enable() we should probably undo the damage after we've turned the PLL off. We do the clock buffer force enable in the .pre_pll_enable() hook as we need to know which port is going to be used, but in the disable case we don't need the port since we just disable the clock buffers to both channels. So we can do this in chv_disable_pll() instead of having to add any kind of .post_pll_disable() hook. v2: Improve the commit message Signed-off-by: Ville Syrjälä Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0c693d8b3a2c..e7e95c3cf6ad 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1712,6 +1712,17 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) val &= ~DPIO_DCLKP_EN; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); + /* disable left/right clock distribution */ + if (pipe != PIPE_B) { + val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); + val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); + vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); + } else { + val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); + val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); + vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); + } + mutex_unlock(&dev_priv->dpio_lock); }