From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 12 Nov 2015 04:14:39 +0000 (-0500)
Subject: drm: add drm_pcie_get_max_link_width helper (v2)
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=60d8edd415e9da63599c7601707ca78ad74a927e;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm: add drm_pcie_get_max_link_width helper (v2)

Add a helper to get the max link width of the port.
Similar to the helper to get the max link speed.

v2: fix typo in commit message

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index fcd2a86acd2c..a1fff1179a97 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -410,6 +410,26 @@ int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask)
 }
 EXPORT_SYMBOL(drm_pcie_get_speed_cap_mask);
 
+int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw)
+{
+	struct pci_dev *root;
+	u32 lnkcap;
+
+	*mlw = 0;
+	if (!dev->pdev)
+		return -EINVAL;
+
+	root = dev->pdev->bus->self;
+
+	pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
+
+	*mlw = (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
+
+	DRM_INFO("probing mlw for device %x:%x = %x\n", root->vendor, root->device, lnkcap);
+	return 0;
+}
+EXPORT_SYMBOL(drm_pcie_get_max_link_width);
+
 #else
 
 int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver)
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 30d4a5a495e2..bd5d2c536ddc 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1098,6 +1098,7 @@ static inline int drm_pci_set_busid(struct drm_device *dev,
 #define DRM_PCIE_SPEED_80 4
 
 extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
+extern int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw);
 
 /* platform section */
 extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);