From: Christian König Date: Fri, 4 Apr 2014 11:45:42 +0000 (+0200) Subject: drm/radeon: apply more strict limits for PLL params v2 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5fb9cc4d8b1639b9a7487c1ee7b2b0c52877327d;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/radeon: apply more strict limits for PLL params v2 Letting post and refernce divider get to big is bad for signal stability. v2: increase the limit to 210 Signed-off-by: Christian König --- diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 386cfa4c194d..2f42912031ac 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, } post_div = post_div_best; + /* limit reference * post divider to a maximum */ + ref_div_max = min(210 / post_div, ref_div_max); + /* get matching reference and feedback divider */ ref_div = max(den / post_div, 1u); fb_div = nom;