From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat, 15 Mar 2014 23:07:07 +0000 (+0000)
Subject: ARM: l2c: add decode for L2C-220 cache ways
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5f47c38704e15f9db356dd799391bc9f9efc4e0c;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git

ARM: l2c: add decode for L2C-220 cache ways

Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b4dd2f4b491b..69a18316b239 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -701,6 +701,7 @@ static void __init __l2c_init(const struct l2c_init_data *data,
 		break;
 
 	case L2X0_CACHE_ID_PART_L210:
+	case L2X0_CACHE_ID_PART_L220:
 		ways = (aux >> 13) & 0xf;
 		break;