From: Bjorn Helgaas <bhelgaas@google.com>
Date: Sat, 4 Jan 2014 01:28:31 +0000 (-0700)
Subject: agp/intel: Use pci_bus_address() to get MMADR bus address
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5ef6d8f49533bb28a90ae9eec177ffd1ade54267;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

agp/intel: Use pci_bus_address() to get MMADR bus address

Per the Intel 915G/915GV/... Chipset spec (document number 301467-005),
MMADR is a standard PCI BAR.

The PCI core reads MMADR at enumeration-time.  Use pci_bus_address()
instead of reading it again in the driver.  This works correctly for both
32-bit and 64-bit BARs.  The spec above only mentions 32-bit MMADR, but we
should still use the standard interface.

Also, stop clearing the low 19 bits of the bus address because it's invalid
to use addresses outside the region defined by the BAR.  The spec claims
MMADR is 512KB; if that's the case, those bits will be zero anyway.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 0bf5590fd0f9..18bbaafb8509 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -56,7 +56,7 @@
 
 /* Intel i810 registers */
 #define I810_GMADR_BAR		0
-#define I810_MMADDR		0x14
+#define I810_MMADR_BAR		1
 #define I810_PTE_BASE		0x10000
 #define I810_PTE_MAIN_UNCACHED	0x00000000
 #define I810_PTE_LOCAL		0x00000002
@@ -114,7 +114,7 @@
 
 /* intel 915G registers */
 #define I915_GMADR_BAR	2
-#define I915_MMADDR	0x10
+#define I915_MMADR_BAR	0
 #define I915_PTEADDR	0x1C
 #define I915_GMCH_GMS_STOLEN_48M	(0x6 << 4)
 #define I915_GMCH_GMS_STOLEN_64M	(0x7 << 4)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 560f66bffebb..58916f32c0f3 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -181,8 +181,7 @@ static int i810_setup(void)
 		return -ENOMEM;
 	intel_private.i81x_gtt_table = gtt_table;
 
-	pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
-	reg_addr &= 0xfff80000;
+	reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
 
 	intel_private.registers = ioremap(reg_addr, KB(64));
 	if (!intel_private.registers)
@@ -785,8 +784,7 @@ static int i830_setup(void)
 {
 	u32 reg_addr;
 
-	pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
-	reg_addr &= 0xfff80000;
+	reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR);
 
 	intel_private.registers = ioremap(reg_addr, KB(64));
 	if (!intel_private.registers)
@@ -1107,9 +1105,7 @@ static int i9xx_setup(void)
 	u32 reg_addr, gtt_addr;
 	int size = KB(512);
 
-	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
-
-	reg_addr &= 0xfff80000;
+	reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR);
 
 	intel_private.registers = ioremap(reg_addr, size);
 	if (!intel_private.registers)