From: ChiHun Won <chihun.won@samsung.com>
Date: Sat, 19 May 2018 02:31:59 +0000 (+0900)
Subject: [9610] fbdev: dpu20: cal9610: changed dsim dphy reset
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5ece8f5a488a1952fa92f4666cf582d613e6e5dc;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[9610] fbdev: dpu20: cal9610: changed dsim dphy reset

Change-Id: Ib1059982c8ca70a6ff574fd79497b6cca77e2f99
Signed-off-by: ChiHun Won <chihun.won@samsung.com>
---

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
index 3dfa0b57d92c..51378312562a 100644
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
@@ -1711,20 +1711,23 @@ static int dsim_reg_set_ulps_by_ddi(u32 id, u32 ddi_type, u32 lanes, u32 en)
 
 void dpu_sysreg_select_dphy_rst_control(void __iomem *sysreg, u32 dsim_id, u32 sel)
 {
-#if 1
-	u32 phy_num = dsim_id ? 0 : 1;
+	u32 phy_num = dsim_id ? 1 : 0;
 	u32 old = readl(sysreg + DISP_DPU_MIPI_PHY_CON);
-	u32 val = sel ? ~0 : 0;
+	u32 val = sel ? 0 : ~0;
 	u32 mask = SEL_RESET_DPHY_MASK(phy_num);
 
 	val = (val & mask) | (old & ~mask);
 	writel(val, sysreg + DISP_DPU_MIPI_PHY_CON);
-#else
-	u32 val;
+}
+
+void dpu_sysreg_dphy_reset(void __iomem *sysreg, u32 dsim_id, u32 rst)
+{
+	u32 old = readl(sysreg + DISP_DPU_MIPI_PHY_CON);
+	u32 val = rst ? ~0 : 0;
+	u32 mask = dsim_id ? M_RESETN_M4S4_MODULE_MASK : M_RESETN_M4S4_TOP_MASK;
 
-	val = SEL_RESET_DPHY_MASK(dsim_id);
+	val = (val & mask) | (old & ~mask);
 	writel(val, sysreg + DISP_DPU_MIPI_PHY_CON);
-#endif
 }
 
 void dsim_reg_init(u32 id, struct decon_lcd *lcd_info, struct dsim_clks *clks,
@@ -1742,14 +1745,16 @@ void dsim_reg_init(u32 id, struct decon_lcd *lcd_info, struct dsim_clks *clks,
 	/* choose OSC_CLK */
 	dsim_reg_set_link_clock(id, 0);
 	/* Enable DPHY reset : DPHY reset start */
-	dsim_reg_dphy_resetn(dsim->id, 0);
+	dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 0);
 
 	dsim_reg_sw_reset(id);
 
 	dsim_reg_set_clocks(id, clks, &lcd_info->dphy_pms, 1);
 
 	dsim_reg_set_lanes(id, dsim->data_lane, 1);
-	dsim_reg_dphy_resetn(dsim->id, 1); /* Release DPHY reset */
+
+	dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 1); /* Release DPHY reset */
+
 	dsim_reg_set_link_clock(id, 1);	/* Selection to word clock */
 	dsim_reg_set_esc_clk_on_lane(id, 1, dsim->data_lane);
 	dsim_reg_enable_word_clock(id, 1);