From: Arend van Spriel Date: Fri, 21 Jan 2011 09:54:49 +0000 (+0100) Subject: staging: brcm80211: cleanup on the brcm80211 include directory X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5e72615c130d8fe9800711be2d713caeaa2d4a64;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git staging: brcm80211: cleanup on the brcm80211 include directory moved several files to specific source directory as these do not need to be shared between drivers. Also removed some unused include files from the include directory. Reviewed-by: Brett Rudley Reviewed-by: Henry Ptasinski Reviewed-by: Roland Vossen Signed-off-by: Arend van Spriel Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/brcm80211/brcmfmac/bcmcdc.h b/drivers/staging/brcm80211/brcmfmac/bcmcdc.h new file mode 100644 index 000000000000..ed4c4a517eca --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/bcmcdc.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include + +typedef struct cdc_ioctl { + u32 cmd; /* ioctl command value */ + u32 len; /* lower 16: output buflen; upper 16: + input buflen (excludes header) */ + u32 flags; /* flag defns given below */ + u32 status; /* status code returned from the device */ +} cdc_ioctl_t; + +/* Max valid buffer size that can be sent to the dongle */ +#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN) + +/* len field is divided into input and output buffer lengths */ +#define CDCL_IOC_OUTLEN_MASK 0x0000FFFF /* maximum or expected + response length, */ + /* excluding IOCTL header */ +#define CDCL_IOC_OUTLEN_SHIFT 0 +#define CDCL_IOC_INLEN_MASK 0xFFFF0000 /* input buffer length, + excluding IOCTL header */ +#define CDCL_IOC_INLEN_SHIFT 16 + +/* CDC flag definitions */ +#define CDCF_IOC_ERROR 0x01 /* 0=success, 1=ioctl cmd failed */ +#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */ +#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */ +#define CDCF_IOC_IF_SHIFT 12 +#define CDCF_IOC_ID_MASK 0xFFFF0000 /* used to uniquely id an ioctl + req/resp pairing */ +#define CDCF_IOC_ID_SHIFT 16 /* # of bits of shift for ID Mask */ + +#define CDC_IOC_IF_IDX(flags) \ + (((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT) +#define CDC_IOC_ID(flags) \ + (((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT) + +#define CDC_GET_IF_IDX(hdr) \ + ((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)) +#define CDC_SET_IF_IDX(hdr, idx) \ + ((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | \ + ((idx) << CDCF_IOC_IF_SHIFT))) + +/* + * BDC header + * + * The BDC header is used on data packets to convey priority across USB. + */ + +#define BDC_HEADER_LEN 4 + +#define BDC_PROTO_VER 1 /* Protocol version */ + +#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */ +#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */ + +#define BDC_FLAG__UNUSED 0x03 /* Unassigned */ +#define BDC_FLAG_SUM_GOOD 0x04 /* Dongle has verified good + RX checksums */ +#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */ + +#define BDC_PRIORITY_MASK 0x7 + +#define BDC_FLAG2_FC_FLAG 0x10 /* flag to indicate if pkt contains */ + /* FLOW CONTROL info only */ +#define BDC_PRIORITY_FC_SHIFT 4 /* flow control info shift */ + +#define BDC_FLAG2_IF_MASK 0x0f /* APSTA: interface on which the + packet was received */ +#define BDC_FLAG2_IF_SHIFT 0 + +#define BDC_GET_IF_IDX(hdr) \ + ((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT)) +#define BDC_SET_IF_IDX(hdr, idx) \ + ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \ + ((idx) << BDC_FLAG2_IF_SHIFT))) + +struct bdc_header { + u8 flags; /* Flags */ + u8 priority; /* 802.1d Priority 0:2 bits, 4:7 flow + control info for usb */ + u8 flags2; + u8 rssi; +}; diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdbus.h b/drivers/staging/brcm80211/brcmfmac/bcmsdbus.h new file mode 100644 index 000000000000..89059dd8088b --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/bcmsdbus.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _sdio_api_h_ +#define _sdio_api_h_ + +#define SDIOH_API_RC_SUCCESS (0x00) +#define SDIOH_API_RC_FAIL (0x01) +#define SDIOH_API_SUCCESS(status) (status == 0) + +#define SDIOH_READ 0 /* Read request */ +#define SDIOH_WRITE 1 /* Write request */ + +#define SDIOH_DATA_FIX 0 /* Fixed addressing */ +#define SDIOH_DATA_INC 1 /* Incremental addressing */ + +#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */ +#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */ +#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */ + +#define SDIOH_DATA_PIO 0 /* PIO mode */ +#define SDIOH_DATA_DMA 1 /* DMA mode */ + +typedef int SDIOH_API_RC; + +/* SDio Host structure */ +typedef struct sdioh_info sdioh_info_t; + +/* callback function, taking one arg */ +typedef void (*sdioh_cb_fn_t) (void *); + +/* attach, return handler on success, NULL if failed. + * The handler shall be provided by all subsequent calls. No local cache + * cfghdl points to the starting address of pci device mapped memory + */ +extern sdioh_info_t *sdioh_attach(struct osl_info *osh, void *cfghdl, uint irq); +extern SDIOH_API_RC sdioh_detach(struct osl_info *osh, sdioh_info_t *si); +extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, + sdioh_cb_fn_t fn, void *argh); +extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si); + +/* query whether SD interrupt is enabled or not */ +extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff); + +/* enable or disable SD interrupt */ +extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable); + +#if defined(BCMDBG) +extern bool sdioh_interrupt_pending(sdioh_info_t *si); +#endif + +extern int sdioh_claim_host_and_lock(sdioh_info_t *si); +extern int sdioh_release_host_and_unlock(sdioh_info_t *si); + +/* read or write one byte using cmd52 */ +extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, + uint addr, u8 *byte); + +/* read or write 2/4 bytes using cmd53 */ +extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, + uint rw, uint fnc, uint addr, + u32 *word, uint nbyte); + +/* read or write any buffer using cmd53 */ +extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, + uint fix_inc, uint rw, uint fnc_num, + u32 addr, uint regwidth, + u32 buflen, u8 *buffer, + struct sk_buff *pkt); + +/* get cis data */ +extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis, + u32 length); + +extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, u32 addr, + u8 *data); +extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, u32 addr, + u8 *data); + +/* query number of io functions */ +extern uint sdioh_query_iofnum(sdioh_info_t *si); + +/* handle iovars */ +extern int sdioh_iovar_op(sdioh_info_t *si, const char *name, + void *params, int plen, void *arg, int len, bool set); + +/* Issue abort to the specified function and clear controller as needed */ +extern int sdioh_abort(sdioh_info_t *si, uint fnc); + +/* Start and Stop SDIO without re-enumerating the SD card. */ +extern int sdioh_start(sdioh_info_t *si, int stage); +extern int sdioh_stop(sdioh_info_t *si); + +/* Reset and re-initialize the device */ +extern int sdioh_sdio_reset(sdioh_info_t *si); + +/* Helper function */ +void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh); + +#endif /* _sdio_api_h_ */ diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.h b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.h new file mode 100644 index 000000000000..4d671ddb3af1 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __BCMSDH_SDMMC_H__ +#define __BCMSDH_SDMMC_H__ + +#ifdef BCMDBG +#define sd_err(x) do { if ((sd_msglevel & SDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0) +#define sd_trace(x) do { if ((sd_msglevel & SDH_TRACE_VAL) && net_ratelimit()) printf x; } while (0) +#define sd_info(x) do { if ((sd_msglevel & SDH_INFO_VAL) && net_ratelimit()) printf x; } while (0) +#define sd_debug(x) do { if ((sd_msglevel & SDH_DEBUG_VAL) && net_ratelimit()) printf x; } while (0) +#define sd_data(x) do { if ((sd_msglevel & SDH_DATA_VAL) && net_ratelimit()) printf x; } while (0) +#define sd_ctrl(x) do { if ((sd_msglevel & SDH_CTRL_VAL) && net_ratelimit()) printf x; } while (0) +#else +#define sd_err(x) +#define sd_trace(x) +#define sd_info(x) +#define sd_debug(x) +#define sd_data(x) +#define sd_ctrl(x) +#endif + +/* Allocate/init/free per-OS private data */ +extern int sdioh_sdmmc_osinit(sdioh_info_t *sd); +extern void sdioh_sdmmc_osfree(sdioh_info_t *sd); + +#define BLOCK_SIZE_64 64 +#define BLOCK_SIZE_512 512 +#define BLOCK_SIZE_4318 64 +#define BLOCK_SIZE_4328 512 + +/* internal return code */ +#define SUCCESS 0 +#define ERROR 1 + +/* private bus modes */ +#define SDIOH_MODE_SD4 2 +#define CLIENT_INTR 0x100 /* Get rid of this! */ + +struct sdioh_info { + struct osl_info *osh; /* osh handler */ + bool client_intr_enabled; /* interrupt connnected flag */ + bool intr_handler_valid; /* client driver interrupt handler valid */ + sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ + void *intr_handler_arg; /* argument to call interrupt handler */ + u16 intmask; /* Current active interrupts */ + void *sdos_info; /* Pointer to per-OS private data */ + + uint irq; /* Client irq */ + int intrcount; /* Client interrupts */ + bool sd_use_dma; /* DMA on CMD53 */ + bool sd_blockmode; /* sd_blockmode == false => 64 Byte Cmd 53s. */ + /* Must be on for sd_multiblock to be effective */ + bool use_client_ints; /* If this is false, make sure to restore */ + int sd_mode; /* SD1/SD4/SPI */ + int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ + u8 num_funcs; /* Supported funcs on client */ + u32 com_cis_ptr; + u32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; + uint max_dma_len; + uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */ + /* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */ +}; + +/************************************************************ + * Internal interfaces: per-port references into bcmsdh_sdmmc.c + */ + +/* Global message bits */ +extern uint sd_msglevel; + +/* OS-independent interrupt handler */ +extern bool check_client_intr(sdioh_info_t *sd); + +/* Core interrupt enable/disable of device interrupts */ +extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd); +extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd); + +/************************************************************** + * Internal interfaces: bcmsdh_sdmmc.c references to per-port code + */ + +/* Register mapping routines */ +extern u32 *sdioh_sdmmc_reg_map(struct osl_info *osh, s32 addr, int size); +extern void sdioh_sdmmc_reg_unmap(struct osl_info *osh, s32 addr, int size); + +/* Interrupt (de)registration routines */ +extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq); +extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd); + +typedef struct _BCMSDH_SDMMC_INSTANCE { + sdioh_info_t *sd; + struct sdio_func *func[SDIOD_MAX_IOFUNCS]; + u32 host_claimed; +} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE; + +#endif /* __BCMSDH_SDMMC_H__ */ diff --git a/drivers/staging/brcm80211/brcmfmac/dhdioctl.h b/drivers/staging/brcm80211/brcmfmac/dhdioctl.h new file mode 100644 index 000000000000..f0ba53558ccd --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/dhdioctl.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _dhdioctl_h_ +#define _dhdioctl_h_ + +/* Linux network driver ioctl encoding */ +typedef struct dhd_ioctl { + uint cmd; /* common ioctl definition */ + void *buf; /* pointer to user buffer */ + uint len; /* length of user buffer */ + bool set; /* get or set request (optional) */ + uint used; /* bytes read or written (optional) */ + uint needed; /* bytes needed (optional) */ + uint driver; /* to identify target driver */ +} dhd_ioctl_t; + +/* per-driver magic numbers */ +#define DHD_IOCTL_MAGIC 0x00444944 + +/* bump this number if you change the ioctl interface */ +#define DHD_IOCTL_VERSION 1 + +#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */ +#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */ + +/* common ioctl definitions */ +#define DHD_GET_MAGIC 0 +#define DHD_GET_VERSION 1 +#define DHD_GET_VAR 2 +#define DHD_SET_VAR 3 + +/* message levels */ +#define DHD_ERROR_VAL 0x0001 +#define DHD_TRACE_VAL 0x0002 +#define DHD_INFO_VAL 0x0004 +#define DHD_DATA_VAL 0x0008 +#define DHD_CTL_VAL 0x0010 +#define DHD_TIMER_VAL 0x0020 +#define DHD_HDRS_VAL 0x0040 +#define DHD_BYTES_VAL 0x0080 +#define DHD_INTR_VAL 0x0100 +#define DHD_LOG_VAL 0x0200 +#define DHD_GLOM_VAL 0x0400 +#define DHD_EVENT_VAL 0x0800 +#define DHD_BTA_VAL 0x1000 +#define DHD_ISCAN_VAL 0x2000 + +#ifdef SDTEST +/* For pktgen iovar */ +typedef struct dhd_pktgen { + uint version; /* To allow structure change tracking */ + uint freq; /* Max ticks between tx/rx attempts */ + uint count; /* Test packets to send/rcv each attempt */ + uint print; /* Print counts every attempts */ + uint total; /* Total packets (or bursts) */ + uint minlen; /* Minimum length of packets to send */ + uint maxlen; /* Maximum length of packets to send */ + uint numsent; /* Count of test packets sent */ + uint numrcvd; /* Count of test packets received */ + uint numfail; /* Count of test send failures */ + uint mode; /* Test mode (type of test packets) */ + uint stop; /* Stop after this many tx failures */ +} dhd_pktgen_t; + +/* Version in case structure changes */ +#define DHD_PKTGEN_VERSION 2 + +/* Type of test packets to use */ +#define DHD_PKTGEN_ECHO 1 /* Send echo requests */ +#define DHD_PKTGEN_SEND 2 /* Send discard packets */ +#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */ +#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous + tx dongle */ +#endif /* SDTEST */ + +/* Enter idle immediately (no timeout) */ +#define DHD_IDLE_IMMEDIATE (-1) + +/* Values for idleclock iovar: other values are the sd_divisor to use + when idle */ +#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change + when idle */ +#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped + (and use SD1 mode) */ + +#endif /* _dhdioctl_h_ */ diff --git a/drivers/staging/brcm80211/brcmfmac/hndrte_armtrap.h b/drivers/staging/brcm80211/brcmfmac/hndrte_armtrap.h new file mode 100644 index 000000000000..28f092c9e027 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/hndrte_armtrap.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _hndrte_armtrap_h +#define _hndrte_armtrap_h + +/* ARM trap handling */ + +/* Trap types defined by ARM (see arminc.h) */ + +/* Trap locations in lo memory */ +#define TRAP_STRIDE 4 +#define FIRST_TRAP TR_RST +#define LAST_TRAP (TR_FIQ * TRAP_STRIDE) + +#if defined(__ARM_ARCH_4T__) +#define MAX_TRAP_TYPE (TR_FIQ + 1) +#elif defined(__ARM_ARCH_7M__) +#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS) +#endif /* __ARM_ARCH_7M__ */ + +/* The trap structure is defined here as offsets for assembly */ +#define TR_TYPE 0x00 +#define TR_EPC 0x04 +#define TR_CPSR 0x08 +#define TR_SPSR 0x0c +#define TR_REGS 0x10 +#define TR_REG(n) (TR_REGS + (n) * 4) +#define TR_SP TR_REG(13) +#define TR_LR TR_REG(14) +#define TR_PC TR_REG(15) + +#define TRAP_T_SIZE 80 + +#ifndef _LANGUAGE_ASSEMBLY + +typedef struct _trap_struct { + u32 type; + u32 epc; + u32 cpsr; + u32 spsr; + u32 r0; + u32 r1; + u32 r2; + u32 r3; + u32 r4; + u32 r5; + u32 r6; + u32 r7; + u32 r8; + u32 r9; + u32 r10; + u32 r11; + u32 r12; + u32 r13; + u32 r14; + u32 pc; +} trap_t; + +#endif /* !_LANGUAGE_ASSEMBLY */ + +#endif /* _hndrte_armtrap_h */ diff --git a/drivers/staging/brcm80211/brcmfmac/hndrte_cons.h b/drivers/staging/brcm80211/brcmfmac/hndrte_cons.h new file mode 100644 index 000000000000..5caa53fb6552 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/hndrte_cons.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define CBUF_LEN (128) + +#define LOG_BUF_LEN 1024 + +typedef struct { + u32 buf; /* Can't be pointer on (64-bit) hosts */ + uint buf_size; + uint idx; + char *_buf_compat; /* Redundant pointer for backward compat. */ +} hndrte_log_t; + +typedef struct { + /* Virtual UART + * When there is no UART (e.g. Quickturn), + * the host should write a complete + * input line directly into cbuf and then write + * the length into vcons_in. + * This may also be used when there is a real UART + * (at risk of conflicting with + * the real UART). vcons_out is currently unused. + */ + volatile uint vcons_in; + volatile uint vcons_out; + + /* Output (logging) buffer + * Console output is written to a ring buffer log_buf at index log_idx. + * The host may read the output when it sees log_idx advance. + * Output will be lost if the output wraps around faster than the host + * polls. + */ + hndrte_log_t log; + + /* Console input line buffer + * Characters are read one at a time into cbuf + * until is received, then + * the buffer is processed as a command line. + * Also used for virtual UART. + */ + uint cbuf_idx; + char cbuf[CBUF_LEN]; +} hndrte_cons_t; diff --git a/drivers/staging/brcm80211/brcmfmac/msgtrace.h b/drivers/staging/brcm80211/brcmfmac/msgtrace.h new file mode 100644 index 000000000000..d654671a5a30 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/msgtrace.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MSGTRACE_H +#define _MSGTRACE_H + +#define MSGTRACE_VERSION 1 + +/* Message trace header */ +typedef struct msgtrace_hdr { + u8 version; + u8 spare; + u16 len; /* Len of the trace */ + u32 seqnum; /* Sequence number of message. Useful + * if the messsage has been lost + * because of DMA error or a bus reset + * (ex: SDIO Func2) + */ + u32 discarded_bytes; /* Number of discarded bytes because of + trace overflow */ + u32 discarded_printf; /* Number of discarded printf + because of trace overflow */ +} __attribute__((packed)) msgtrace_hdr_t; + +#define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t) + +/* The hbus driver generates traces when sending a trace message. + * This causes endless traces. + * This flag must be set to true in any hbus traces. + * The flag is reset in the function msgtrace_put. + * This prevents endless traces but generates hasardous + * lost of traces only in bus device code. + * It is recommendat to set this flag in macro SD_TRACE + * but not in SD_ERROR for avoiding missing + * hbus error traces. hbus error trace should not generates endless traces. + */ +extern bool msgtrace_hbus_trace; + +typedef void (*msgtrace_func_send_t) (void *hdl1, void *hdl2, u8 *hdr, + u16 hdrlen, u8 *buf, + u16 buflen); + +extern void msgtrace_sent(void); +extern void msgtrace_put(char *buf, int count); +extern void msgtrace_init(void *hdl1, void *hdl2, + msgtrace_func_send_t func_send); + +#endif /* _MSGTRACE_H */ diff --git a/drivers/staging/brcm80211/brcmfmac/sdioh.h b/drivers/staging/brcm80211/brcmfmac/sdioh.h new file mode 100644 index 000000000000..f96aaf9cec74 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/sdioh.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SDIOH_H +#define _SDIOH_H + +#define SD_SysAddr 0x000 +#define SD_BlockSize 0x004 +#define SD_BlockCount 0x006 +#define SD_Arg0 0x008 +#define SD_Arg1 0x00A +#define SD_TransferMode 0x00C +#define SD_Command 0x00E +#define SD_Response0 0x010 +#define SD_Response1 0x012 +#define SD_Response2 0x014 +#define SD_Response3 0x016 +#define SD_Response4 0x018 +#define SD_Response5 0x01A +#define SD_Response6 0x01C +#define SD_Response7 0x01E +#define SD_BufferDataPort0 0x020 +#define SD_BufferDataPort1 0x022 +#define SD_PresentState 0x024 +#define SD_HostCntrl 0x028 +#define SD_PwrCntrl 0x029 +#define SD_BlockGapCntrl 0x02A +#define SD_WakeupCntrl 0x02B +#define SD_ClockCntrl 0x02C +#define SD_TimeoutCntrl 0x02E +#define SD_SoftwareReset 0x02F +#define SD_IntrStatus 0x030 +#define SD_ErrorIntrStatus 0x032 +#define SD_IntrStatusEnable 0x034 +#define SD_ErrorIntrStatusEnable 0x036 +#define SD_IntrSignalEnable 0x038 +#define SD_ErrorIntrSignalEnable 0x03A +#define SD_CMD12ErrorStatus 0x03C +#define SD_Capabilities 0x040 +#define SD_Capabilities_Reserved 0x044 +#define SD_MaxCurCap 0x048 +#define SD_MaxCurCap_Reserved 0x04C +#define SD_ADMA_SysAddr 0x58 +#define SD_SlotInterruptStatus 0x0FC +#define SD_HostControllerVersion 0x0FE + +/* SD specific registers in PCI config space */ +#define SD_SlotInfo 0x40 + +#endif /* _SDIOH_H */ diff --git a/drivers/staging/brcm80211/brcmfmac/sdiovar.h b/drivers/staging/brcm80211/brcmfmac/sdiovar.h new file mode 100644 index 000000000000..d1cfa5f0a982 --- /dev/null +++ b/drivers/staging/brcm80211/brcmfmac/sdiovar.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _sdiovar_h_ +#define _sdiovar_h_ + +typedef struct sdreg { + int func; + int offset; + int value; +} sdreg_t; + +/* Common msglevel constants */ +#define SDH_ERROR_VAL 0x0001 /* Error */ +#define SDH_TRACE_VAL 0x0002 /* Trace */ +#define SDH_INFO_VAL 0x0004 /* Info */ +#define SDH_DEBUG_VAL 0x0008 /* Debug */ +#define SDH_DATA_VAL 0x0010 /* Data */ +#define SDH_CTRL_VAL 0x0020 /* Control Regs */ +#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ +#define SDH_DMA_VAL 0x0080 /* DMA */ + +#define NUM_PREV_TRANSACTIONS 16 + +#endif /* _sdiovar_h_ */ diff --git a/drivers/staging/brcm80211/brcmsmac/Makefile b/drivers/staging/brcm80211/brcmsmac/Makefile index 910196a37353..e5dda8689890 100644 --- a/drivers/staging/brcm80211/brcmsmac/Makefile +++ b/drivers/staging/brcm80211/brcmsmac/Makefile @@ -25,6 +25,7 @@ ccflags-y := \ -DDBAND \ -DBCMDMA32 \ -DBCMNVRAMR \ + -Idrivers/staging/brcm80211/brcmsmac \ -Idrivers/staging/brcm80211/brcmsmac/sys \ -Idrivers/staging/brcm80211/brcmsmac/phy \ -Idrivers/staging/brcm80211/util \ diff --git a/drivers/staging/brcm80211/brcmsmac/d11.h b/drivers/staging/brcm80211/brcmsmac/d11.h new file mode 100644 index 000000000000..50883af62496 --- /dev/null +++ b/drivers/staging/brcm80211/brcmsmac/d11.h @@ -0,0 +1,1765 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _D11_H +#define _D11_H + +#ifndef WL_RSSI_ANT_MAX +#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */ +#elif WL_RSSI_ANT_MAX != 4 +#error "WL_RSSI_ANT_MAX does not match" +#endif + +/* cpp contortions to concatenate w/arg prescan */ +#ifndef PAD +#define _PADLINE(line) pad ## line +#define _XSTR(line) _PADLINE(line) +#define PAD _XSTR(__LINE__) +#endif + +#define BCN_TMPL_LEN 512 /* length of the BCN template area */ + +/* RX FIFO numbers */ +#define RX_FIFO 0 /* data and ctl frames */ +#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */ + +/* TX FIFO numbers using WME Access Classes */ +#define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */ +#define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */ +#define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */ +#define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */ +#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */ +#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */ + +/* Addr is byte address used by SW; offset is word offset used by uCode */ + +/* Per AC TX limit settings */ +#define M_AC_TXLMT_BASE_ADDR (0x180 * 2) +#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac))) + +/* Legacy TX FIFO numbers */ +#define TX_DATA_FIFO TX_AC_BE_FIFO +#define TX_CTL_FIFO TX_AC_VO_FIFO + +typedef volatile struct { + u32 intstatus; + u32 intmask; +} intctrlregs_t; + +/* read: 32-bit register that can be read as 32-bit or as 2 16-bit + * write: only low 16b-it half can be written + */ +typedef volatile union { + u32 pmqhostdata; /* read only! */ + struct { + u16 pmqctrlstatus; /* read/write */ + u16 PAD; + } w; +} pmqreg_t; + +/* pio register set 2/4 bytes union for d11 fifo */ +typedef volatile union { + pio2regp_t b2; /* < corerev 8 */ + pio4regp_t b4; /* >= corerev 8 */ +} u_pioreg_t; + +/* dma/pio corerev < 11 */ +typedef volatile struct { + dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */ + u_pioreg_t pioregs[8]; /* 0x300 */ +} fifo32_t; + +/* dma/pio corerev >= 11 */ +typedef volatile struct { + dma64regs_t dmaxmt; /* dma tx */ + pio4regs_t piotx; /* pio tx */ + dma64regs_t dmarcv; /* dma rx */ + pio4regs_t piorx; /* pio rx */ +} fifo64_t; + +/* + * Host Interface Registers + * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h + * - but definitely not complete + */ +typedef volatile struct _d11regs { + /* Device Control ("semi-standard host registers") */ + u32 PAD[3]; /* 0x0 - 0x8 */ + u32 biststatus; /* 0xC */ + u32 biststatus2; /* 0x10 */ + u32 PAD; /* 0x14 */ + u32 gptimer; /* 0x18 *//* for corerev >= 3 */ + u32 usectimer; /* 0x1c *//* for corerev >= 26 */ + + /* Interrupt Control *//* 0x20 */ + intctrlregs_t intctrlregs[8]; + + u32 PAD[40]; /* 0x60 - 0xFC */ + + /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */ + u32 intrcvlazy[4]; /* 0x100 - 0x10C */ + + u32 PAD[4]; /* 0x110 - 0x11c */ + + u32 maccontrol; /* 0x120 */ + u32 maccommand; /* 0x124 */ + u32 macintstatus; /* 0x128 */ + u32 macintmask; /* 0x12C */ + + /* Transmit Template Access */ + u32 tplatewrptr; /* 0x130 */ + u32 tplatewrdata; /* 0x134 */ + u32 PAD[2]; /* 0x138 - 0x13C */ + + /* PMQ registers */ + pmqreg_t pmqreg; /* 0x140 */ + u32 pmqpatl; /* 0x144 */ + u32 pmqpath; /* 0x148 */ + u32 PAD; /* 0x14C */ + + u32 chnstatus; /* 0x150 */ + u32 psmdebug; /* 0x154 *//* for corerev >= 3 */ + u32 phydebug; /* 0x158 *//* for corerev >= 3 */ + u32 machwcap; /* 0x15C *//* Corerev >= 13 */ + + /* Extended Internal Objects */ + u32 objaddr; /* 0x160 */ + u32 objdata; /* 0x164 */ + u32 PAD[2]; /* 0x168 - 0x16c */ + + /* New txstatus registers on corerev >= 5 */ + u32 frmtxstatus; /* 0x170 */ + u32 frmtxstatus2; /* 0x174 */ + u32 PAD[2]; /* 0x178 - 0x17c */ + + /* New TSF host access on corerev >= 3 */ + + u32 tsf_timerlow; /* 0x180 */ + u32 tsf_timerhigh; /* 0x184 */ + u32 tsf_cfprep; /* 0x188 */ + u32 tsf_cfpstart; /* 0x18c */ + u32 tsf_cfpmaxdur32; /* 0x190 */ + u32 PAD[3]; /* 0x194 - 0x19c */ + + u32 maccontrol1; /* 0x1a0 */ + u32 machwcap1; /* 0x1a4 */ + u32 PAD[14]; /* 0x1a8 - 0x1dc */ + + /* Clock control and hardware workarounds (corerev >= 13) */ + u32 clk_ctl_st; /* 0x1e0 */ + u32 hw_war; + u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are + * moved to clk_ctl_st for corerev >= 17 + */ + u32 PAD[5]; /* 0x1ec - 0x1fc */ + + /* 0x200-0x37F dma/pio registers */ + volatile union { + fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */ + fifo64_t f64regs[6]; /* on corerev >= 11 */ + } fifo; + + /* FIFO diagnostic port access */ + dma32diag_t dmafifo; /* 0x380 - 0x38C */ + + u32 aggfifocnt; /* 0x390 */ + u32 aggfifodata; /* 0x394 */ + u32 PAD[16]; /* 0x398 - 0x3d4 */ + u16 radioregaddr; /* 0x3d8 */ + u16 radioregdata; /* 0x3da */ + + /* time delay between the change on rf disable input and radio shutdown corerev 10 */ + u32 rfdisabledly; /* 0x3DC */ + + /* PHY register access */ + u16 phyversion; /* 0x3e0 - 0x0 */ + u16 phybbconfig; /* 0x3e2 - 0x1 */ + u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */ + u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */ + u16 phyrxstatus0; /* 0x3e8 - 0x4 */ + u16 phyrxstatus1; /* 0x3ea - 0x5 */ + u16 phycrsth; /* 0x3ec - 0x6 */ + u16 phytxerror; /* 0x3ee - 0x7 */ + u16 phychannel; /* 0x3f0 - 0x8 */ + u16 PAD[1]; /* 0x3f2 - 0x9 */ + u16 phytest; /* 0x3f4 - 0xa */ + u16 phy4waddr; /* 0x3f6 - 0xb */ + u16 phy4wdatahi; /* 0x3f8 - 0xc */ + u16 phy4wdatalo; /* 0x3fa - 0xd */ + u16 phyregaddr; /* 0x3fc - 0xe */ + u16 phyregdata; /* 0x3fe - 0xf */ + + /* IHR *//* 0x400 - 0x7FE */ + + /* RXE Block */ + u16 PAD[3]; /* 0x400 - 0x406 */ + u16 rcv_fifo_ctl; /* 0x406 */ + u16 PAD; /* 0x408 - 0x40a */ + u16 rcv_frm_cnt; /* 0x40a */ + u16 PAD[4]; /* 0x40a - 0x414 */ + u16 rssi; /* 0x414 */ + u16 PAD[5]; /* 0x414 - 0x420 */ + u16 rcm_ctl; /* 0x420 */ + u16 rcm_mat_data; /* 0x422 */ + u16 rcm_mat_mask; /* 0x424 */ + u16 rcm_mat_dly; /* 0x426 */ + u16 rcm_cond_mask_l; /* 0x428 */ + u16 rcm_cond_mask_h; /* 0x42A */ + u16 rcm_cond_dly; /* 0x42C */ + u16 PAD[1]; /* 0x42E */ + u16 ext_ihr_addr; /* 0x430 */ + u16 ext_ihr_data; /* 0x432 */ + u16 rxe_phyrs_2; /* 0x434 */ + u16 rxe_phyrs_3; /* 0x436 */ + u16 phy_mode; /* 0x438 */ + u16 rcmta_ctl; /* 0x43a */ + u16 rcmta_size; /* 0x43c */ + u16 rcmta_addr0; /* 0x43e */ + u16 rcmta_addr1; /* 0x440 */ + u16 rcmta_addr2; /* 0x442 */ + u16 PAD[30]; /* 0x444 - 0x480 */ + + /* PSM Block *//* 0x480 - 0x500 */ + + u16 PAD; /* 0x480 */ + u16 psm_maccontrol_h; /* 0x482 */ + u16 psm_macintstatus_l; /* 0x484 */ + u16 psm_macintstatus_h; /* 0x486 */ + u16 psm_macintmask_l; /* 0x488 */ + u16 psm_macintmask_h; /* 0x48A */ + u16 PAD; /* 0x48C */ + u16 psm_maccommand; /* 0x48E */ + u16 psm_brc; /* 0x490 */ + u16 psm_phy_hdr_param; /* 0x492 */ + u16 psm_postcard; /* 0x494 */ + u16 psm_pcard_loc_l; /* 0x496 */ + u16 psm_pcard_loc_h; /* 0x498 */ + u16 psm_gpio_in; /* 0x49A */ + u16 psm_gpio_out; /* 0x49C */ + u16 psm_gpio_oe; /* 0x49E */ + + u16 psm_bred_0; /* 0x4A0 */ + u16 psm_bred_1; /* 0x4A2 */ + u16 psm_bred_2; /* 0x4A4 */ + u16 psm_bred_3; /* 0x4A6 */ + u16 psm_brcl_0; /* 0x4A8 */ + u16 psm_brcl_1; /* 0x4AA */ + u16 psm_brcl_2; /* 0x4AC */ + u16 psm_brcl_3; /* 0x4AE */ + u16 psm_brpo_0; /* 0x4B0 */ + u16 psm_brpo_1; /* 0x4B2 */ + u16 psm_brpo_2; /* 0x4B4 */ + u16 psm_brpo_3; /* 0x4B6 */ + u16 psm_brwk_0; /* 0x4B8 */ + u16 psm_brwk_1; /* 0x4BA */ + u16 psm_brwk_2; /* 0x4BC */ + u16 psm_brwk_3; /* 0x4BE */ + + u16 psm_base_0; /* 0x4C0 */ + u16 psm_base_1; /* 0x4C2 */ + u16 psm_base_2; /* 0x4C4 */ + u16 psm_base_3; /* 0x4C6 */ + u16 psm_base_4; /* 0x4C8 */ + u16 psm_base_5; /* 0x4CA */ + u16 psm_base_6; /* 0x4CC */ + u16 psm_pc_reg_0; /* 0x4CE */ + u16 psm_pc_reg_1; /* 0x4D0 */ + u16 psm_pc_reg_2; /* 0x4D2 */ + u16 psm_pc_reg_3; /* 0x4D4 */ + u16 PAD[0xD]; /* 0x4D6 - 0x4DE */ + u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */ + u16 PAD[0x7]; /* 0x4f2 - 0x4fE */ + + /* TXE0 Block *//* 0x500 - 0x580 */ + u16 txe_ctl; /* 0x500 */ + u16 txe_aux; /* 0x502 */ + u16 txe_ts_loc; /* 0x504 */ + u16 txe_time_out; /* 0x506 */ + u16 txe_wm_0; /* 0x508 */ + u16 txe_wm_1; /* 0x50A */ + u16 txe_phyctl; /* 0x50C */ + u16 txe_status; /* 0x50E */ + u16 txe_mmplcp0; /* 0x510 */ + u16 txe_mmplcp1; /* 0x512 */ + u16 txe_phyctl1; /* 0x514 */ + + u16 PAD[0x05]; /* 0x510 - 0x51E */ + + /* Transmit control */ + u16 xmtfifodef; /* 0x520 */ + u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */ + u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */ + u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */ + u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */ + u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */ + u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */ + + u16 PAD[0x09]; /* 0x52E - 0x53E */ + + u16 xmtfifocmd; /* 0x540 */ + u16 xmtfifoflush; /* 0x542 */ + u16 xmtfifothresh; /* 0x544 */ + u16 xmtfifordy; /* 0x546 */ + u16 xmtfifoprirdy; /* 0x548 */ + u16 xmtfiforqpri; /* 0x54A */ + u16 xmttplatetxptr; /* 0x54C */ + u16 PAD; /* 0x54E */ + u16 xmttplateptr; /* 0x550 */ + u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */ + u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */ + u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */ + u16 PAD[0x04]; /* 0x558 - 0x55E */ + u16 xmttplatedatalo; /* 0x560 */ + u16 xmttplatedatahi; /* 0x562 */ + + u16 PAD[2]; /* 0x564 - 0x566 */ + + u16 xmtsel; /* 0x568 */ + u16 xmttxcnt; /* 0x56A */ + u16 xmttxshmaddr; /* 0x56C */ + + u16 PAD[0x09]; /* 0x56E - 0x57E */ + + /* TXE1 Block */ + u16 PAD[0x40]; /* 0x580 - 0x5FE */ + + /* TSF Block */ + u16 PAD[0X02]; /* 0x600 - 0x602 */ + u16 tsf_cfpstrt_l; /* 0x604 */ + u16 tsf_cfpstrt_h; /* 0x606 */ + u16 PAD[0X05]; /* 0x608 - 0x610 */ + u16 tsf_cfppretbtt; /* 0x612 */ + u16 PAD[0XD]; /* 0x614 - 0x62C */ + u16 tsf_clk_frac_l; /* 0x62E */ + u16 tsf_clk_frac_h; /* 0x630 */ + u16 PAD[0X14]; /* 0x632 - 0x658 */ + u16 tsf_random; /* 0x65A */ + u16 PAD[0x05]; /* 0x65C - 0x664 */ + /* GPTimer 2 registers are corerev >= 3 */ + u16 tsf_gpt2_stat; /* 0x666 */ + u16 tsf_gpt2_ctr_l; /* 0x668 */ + u16 tsf_gpt2_ctr_h; /* 0x66A */ + u16 tsf_gpt2_val_l; /* 0x66C */ + u16 tsf_gpt2_val_h; /* 0x66E */ + u16 tsf_gptall_stat; /* 0x670 */ + u16 PAD[0x07]; /* 0x672 - 0x67E */ + + /* IFS Block */ + u16 ifs_sifs_rx_tx_tx; /* 0x680 */ + u16 ifs_sifs_nav_tx; /* 0x682 */ + u16 ifs_slot; /* 0x684 */ + u16 PAD; /* 0x686 */ + u16 ifs_ctl; /* 0x688 */ + u16 PAD[0x3]; /* 0x68a - 0x68F */ + u16 ifsstat; /* 0x690 */ + u16 ifsmedbusyctl; /* 0x692 */ + u16 iftxdur; /* 0x694 */ + u16 PAD[0x3]; /* 0x696 - 0x69b */ + /* EDCF support in dot11macs with corerevs >= 16 */ + u16 ifs_aifsn; /* 0x69c */ + u16 ifs_ctl1; /* 0x69e */ + + /* New slow clock registers on corerev >= 5 */ + u16 scc_ctl; /* 0x6a0 */ + u16 scc_timer_l; /* 0x6a2 */ + u16 scc_timer_h; /* 0x6a4 */ + u16 scc_frac; /* 0x6a6 */ + u16 scc_fastpwrup_dly; /* 0x6a8 */ + u16 scc_per; /* 0x6aa */ + u16 scc_per_frac; /* 0x6ac */ + u16 scc_cal_timer_l; /* 0x6ae */ + u16 scc_cal_timer_h; /* 0x6b0 */ + u16 PAD; /* 0x6b2 */ + + u16 PAD[0x26]; + + /* NAV Block */ + u16 nav_ctl; /* 0x700 */ + u16 navstat; /* 0x702 */ + u16 PAD[0x3e]; /* 0x702 - 0x77E */ + + /* WEP/PMQ Block *//* 0x780 - 0x7FE */ + u16 PAD[0x20]; /* 0x780 - 0x7BE */ + + u16 wepctl; /* 0x7C0 */ + u16 wepivloc; /* 0x7C2 */ + u16 wepivkey; /* 0x7C4 */ + u16 wepwkey; /* 0x7C6 */ + + u16 PAD[4]; /* 0x7C8 - 0x7CE */ + u16 pcmctl; /* 0X7D0 */ + u16 pcmstat; /* 0X7D2 */ + u16 PAD[6]; /* 0x7D4 - 0x7DE */ + + u16 pmqctl; /* 0x7E0 */ + u16 pmqstatus; /* 0x7E2 */ + u16 pmqpat0; /* 0x7E4 */ + u16 pmqpat1; /* 0x7E6 */ + u16 pmqpat2; /* 0x7E8 */ + + u16 pmqdat; /* 0x7EA */ + u16 pmqdator; /* 0x7EC */ + u16 pmqhst; /* 0x7EE */ + u16 pmqpath0; /* 0x7F0 */ + u16 pmqpath1; /* 0x7F2 */ + u16 pmqpath2; /* 0x7F4 */ + u16 pmqdath; /* 0x7F6 */ + + u16 PAD[0x04]; /* 0x7F8 - 0x7FE */ + + /* SHM *//* 0x800 - 0xEFE */ + u16 PAD[0x380]; /* 0x800 - 0xEFE */ + + /* SB configuration registers: 0xF00 */ + sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */ +} d11regs_t; + +#define PIHR_BASE 0x0400 /* byte address of packed IHR region */ + +/* biststatus */ +#define BT_DONE (1U << 31) /* bist done */ +#define BT_B2S (1 << 30) /* bist2 ram summary bit */ + +/* intstatus and intmask */ +#define I_PC (1 << 10) /* pci descriptor error */ +#define I_PD (1 << 11) /* pci data error */ +#define I_DE (1 << 12) /* descriptor protocol error */ +#define I_RU (1 << 13) /* receive descriptor underflow */ +#define I_RO (1 << 14) /* receive fifo overflow */ +#define I_XU (1 << 15) /* transmit fifo underflow */ +#define I_RI (1 << 16) /* receive interrupt */ +#define I_XI (1 << 24) /* transmit interrupt */ + +/* interrupt receive lazy */ +#define IRL_TO_MASK 0x00ffffff /* timeout */ +#define IRL_FC_MASK 0xff000000 /* frame count */ +#define IRL_FC_SHIFT 24 /* frame count */ + +/* maccontrol register */ +#define MCTL_GMODE (1U << 31) +#define MCTL_DISCARD_PMQ (1 << 30) +#define MCTL_WAKE (1 << 26) +#define MCTL_HPS (1 << 25) +#define MCTL_PROMISC (1 << 24) +#define MCTL_KEEPBADFCS (1 << 23) +#define MCTL_KEEPCONTROL (1 << 22) +#define MCTL_PHYLOCK (1 << 21) +#define MCTL_BCNS_PROMISC (1 << 20) +#define MCTL_LOCK_RADIO (1 << 19) +#define MCTL_AP (1 << 18) +#define MCTL_INFRA (1 << 17) +#define MCTL_BIGEND (1 << 16) +#define MCTL_GPOUT_SEL_MASK (3 << 14) +#define MCTL_GPOUT_SEL_SHIFT 14 +#define MCTL_EN_PSMDBG (1 << 13) +#define MCTL_IHR_EN (1 << 10) +#define MCTL_SHM_UPPER (1 << 9) +#define MCTL_SHM_EN (1 << 8) +#define MCTL_PSM_JMP_0 (1 << 2) +#define MCTL_PSM_RUN (1 << 1) +#define MCTL_EN_MAC (1 << 0) + +/* maccommand register */ +#define MCMD_BCN0VLD (1 << 0) +#define MCMD_BCN1VLD (1 << 1) +#define MCMD_DIRFRMQVAL (1 << 2) +#define MCMD_CCA (1 << 3) +#define MCMD_BG_NOISE (1 << 4) +#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */ +#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */ + +/* macintstatus/macintmask */ +#define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */ +#define MI_BCNTPL (1 << 1) /* beacon template available */ +#define MI_TBTT (1 << 2) /* TBTT indication */ +#define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */ +#define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */ +#define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */ +#define MI_PMQ (1 << 6) /* PMQ entries available */ +#define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */ +#define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */ +#define MI_MACTXERR (1 << 9) /* MAC level Tx error */ +#define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */ +#define MI_PHYTXERR (1 << 11) /* PHY Tx error */ +#define MI_PME (1 << 12) /* Power Management Event */ +#define MI_GP0 (1 << 13) /* General-purpose timer0 */ +#define MI_GP1 (1 << 14) /* General-purpose timer1 */ +#define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */ +#define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */ +#define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */ +#define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */ +#define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */ +#define MI_PRQ (1 << 20) /* Probe response queue needs attention */ +#define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */ +#define MI_RESERVED3 (1 << 22) +#define MI_RESERVED2 (1 << 23) +#define MI_RESERVED1 (1 << 25) +#define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input + * (corerev >= 10) + */ +#define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */ +#define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */ +#define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */ + +/* Mac capabilities registers */ +/* machwcap */ +#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */ + +/* pmqhost data */ +#define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */ +#define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */ +#define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */ +#define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */ +#define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */ +#define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */ +#define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */ +#define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */ +#define PMQH_OFLO 0x00000004 /* pmq overflow indication */ +#define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */ + +/* phydebug (corerev >= 3) */ +#define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */ +#define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */ +#define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */ +#define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */ +#define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */ +#define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */ +#define PDBG_RXFRG (1 << 6) /* rx start not asserted */ +#define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */ +#define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */ + +/* objaddr register */ +#define OBJADDR_SEL_MASK 0x000F0000 +#define OBJADDR_UCM_SEL 0x00000000 +#define OBJADDR_SHM_SEL 0x00010000 +#define OBJADDR_SCR_SEL 0x00020000 +#define OBJADDR_IHR_SEL 0x00030000 +#define OBJADDR_RCMTA_SEL 0x00040000 +#define OBJADDR_SRCHM_SEL 0x00060000 +#define OBJADDR_WINC 0x01000000 +#define OBJADDR_RINC 0x02000000 +#define OBJADDR_AUTO_INC 0x03000000 + +#define WEP_PCMADDR 0x07d4 +#define WEP_PCMDATA 0x07d6 + +/* frmtxstatus */ +#define TXS_V (1 << 0) /* valid bit */ +#define TXS_STATUS_MASK 0xffff +/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */ +#define TXS_COMPAT_MASK 0x3 +#define TXS_COMPAT_SHIFT 1 +#define TXS_FID_MASK 0xffff0000 +#define TXS_FID_SHIFT 16 + +/* frmtxstatus2 */ +#define TXS_SEQ_MASK 0xffff +#define TXS_PTX_MASK 0xff0000 +#define TXS_PTX_SHIFT 16 +#define TXS_MU_MASK 0x01000000 +#define TXS_MU_SHIFT 24 + +/* clk_ctl_st, corerev >= 17 */ +#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */ +#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */ +#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */ +#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */ + +/* HT Cloclk Ctrl and Clock Avail for 4313 */ +#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */ +#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */ + +/* d11_pwrctl, corerev16 only */ +#define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */ +#define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */ + +/* tsf_cfprep register */ +#define CFPREP_CBI_MASK 0xffffffc0 +#define CFPREP_CBI_SHIFT 6 +#define CFPREP_CFPP 0x00000001 + +/* tx fifo sizes for corerev >= 9 */ +/* tx fifo sizes values are in terms of 256 byte blocks */ +#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */ +#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */ +#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */ + +#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */ +#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */ +#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */ +#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */ + +/* phy versions, PhyVersion:Revision field */ +#define PV_AV_MASK 0xf000 /* analog block version */ +#define PV_AV_SHIFT 12 /* analog block version bitfield offset */ +#define PV_PT_MASK 0x0f00 /* phy type */ +#define PV_PT_SHIFT 8 /* phy type bitfield offset */ +#define PV_PV_MASK 0x000f /* phy version */ +#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT) + +/* phy types, PhyVersion:PhyType field */ +#define PHY_TYPE_N 4 /* N-Phy value */ +#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */ +#define PHY_TYPE_LCN 8 /* LCN-Phy value */ +#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */ +#define PHY_TYPE_NULL 0xf /* Invalid Phy value */ + +/* analog types, PhyVersion:AnalogType field */ +#define ANA_11N_013 5 + +/* 802.11a PLCP header def */ +typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; +struct ofdm_phy_hdr { + u8 rlpt[3]; /* rate, length, parity, tail */ + u16 service; + u8 pad; +} __attribute__((packed)); + +#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) +#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) +#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff) +#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) +#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) + +/* rate encoded per 802.11a-1999 sec 17.3.4.1 */ +#define D11A_PHY_HDR_SRATE(phdr, rate) \ + ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf)) +/* set reserved field to zero */ +#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) +/* length is number of octets in PSDU */ +#define D11A_PHY_HDR_SLENGTH(phdr, length) \ + (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \ + (((length) & 0x0fff) << 5)) +/* set the tail to all zeros */ +#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) + +#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */ +#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */ + +#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */ + +#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */ +#define D11A_PHY_PRE_TIME (16) +#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME) + +/* 802.11b PLCP header def */ +typedef struct cck_phy_hdr cck_phy_hdr_t; +struct cck_phy_hdr { + u8 signal; + u8 service; + u16 length; + u16 crc; +} __attribute__((packed)); + +#define D11B_PHY_HDR_LEN 6 + +#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */ + +#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3) +#define D11B_PHY_LPRE_TIME (144) +#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME) + +#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1) +#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1) +#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME) + +#define D11B_PLCP_SIGNAL_LOCKED (1 << 2) +#define D11B_PLCP_SIGNAL_LE (1 << 7) + +#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */ +#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */ +#define MIMO_PLCP_AMPDU 0x08 /* ampdu */ + +#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8)) +#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8)) +#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \ + do { \ + plcp[1] = len & 0xff; \ + plcp[2] = ((len >> 8) & 0xff); \ + } while (0); + +#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU) +#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU) +#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU) + +/* The dot11a PLCP header is 5 bytes. To simplify the software (so that we + * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has + * padding added in the ucode. + */ +#define D11_PHY_HDR_LEN 6 + +/* TX DMA buffer header */ +typedef struct d11txh d11txh_t; +struct d11txh { + u16 MacTxControlLow; /* 0x0 */ + u16 MacTxControlHigh; /* 0x1 */ + u16 MacFrameControl; /* 0x2 */ + u16 TxFesTimeNormal; /* 0x3 */ + u16 PhyTxControlWord; /* 0x4 */ + u16 PhyTxControlWord_1; /* 0x5 */ + u16 PhyTxControlWord_1_Fbr; /* 0x6 */ + u16 PhyTxControlWord_1_Rts; /* 0x7 */ + u16 PhyTxControlWord_1_FbrRts; /* 0x8 */ + u16 MainRates; /* 0x9 */ + u16 XtraFrameTypes; /* 0xa */ + u8 IV[16]; /* 0x0b - 0x12 */ + u8 TxFrameRA[6]; /* 0x13 - 0x15 */ + u16 TxFesTimeFallback; /* 0x16 */ + u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ + u16 RTSDurFallback; /* 0x1a */ + u8 FragPLCPFallback[6]; /* 0x1b - 1d */ + u16 FragDurFallback; /* 0x1e */ + u16 MModeLen; /* 0x1f */ + u16 MModeFbrLen; /* 0x20 */ + u16 TstampLow; /* 0x21 */ + u16 TstampHigh; /* 0x22 */ + u16 ABI_MimoAntSel; /* 0x23 */ + u16 PreloadSize; /* 0x24 */ + u16 AmpduSeqCtl; /* 0x25 */ + u16 TxFrameID; /* 0x26 */ + u16 TxStatus; /* 0x27 */ + u16 MaxNMpdus; /* 0x28 corerev >=16 */ + u16 MaxABytes_MRT; /* 0x29 corerev >=16 */ + u16 MaxABytes_FBR; /* 0x2a corerev >=16 */ + u16 MinMBytes; /* 0x2b corerev >=16 */ + u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ + struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */ + u16 PAD; /* 0x37 */ +} __attribute__((packed)); + +#define D11_TXH_LEN 112 /* bytes */ + +/* Frame Types */ +#define FT_CCK 0 +#define FT_OFDM 1 +#define FT_HT 2 +#define FT_N 3 + +/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */ +#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */ +#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */ +#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */ +#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */ +#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */ + +/* MacTxControlLow */ +#define TXC_AMIC 0x8000 +#define TXC_SENDCTS 0x0800 +#define TXC_AMPDU_MASK 0x0600 +#define TXC_BW_40 0x0100 +#define TXC_FREQBAND_5G 0x0080 +#define TXC_DFCS 0x0040 +#define TXC_IGNOREPMQ 0x0020 +#define TXC_HWSEQ 0x0010 +#define TXC_STARTMSDU 0x0008 +#define TXC_SENDRTS 0x0004 +#define TXC_LONGFRAME 0x0002 +#define TXC_IMMEDACK 0x0001 + +/* MacTxControlHigh */ +#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */ +#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */ +#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type + * 1 = SHORT for OFDM/GF for MIMO + * 0 = LONG for CCK/MM for MIMO + */ +/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */ +#define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */ +#define TXC_SECKEY_MASK 0x0FF0 +#define TXC_SECKEY_SHIFT 4 +#define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ +#define TXC_SECTYPE_MASK 0x0007 +#define TXC_SECTYPE_SHIFT 0 + +/* Null delimiter for Fallback rate */ +#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */ + +/* PhyTxControl for Mimophy */ +#define PHY_TXC_PWR_MASK 0xFC00 +#define PHY_TXC_PWR_SHIFT 10 +#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */ +#define PHY_TXC_ANT_SHIFT 6 +#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */ +#define PHY_TXC_LCNPHY_ANT_LAST 0x0000 +#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */ +#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */ +#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */ +#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */ +#define PHY_TXC_SHORT_HDR 0x0010 + +#define PHY_TXC_OLD_ANT_0 0x0000 +#define PHY_TXC_OLD_ANT_1 0x0100 +#define PHY_TXC_OLD_ANT_LAST 0x0300 + +/* PhyTxControl_1 for Mimophy */ +#define PHY_TXC1_BW_MASK 0x0007 +#define PHY_TXC1_BW_10MHZ 0 +#define PHY_TXC1_BW_10MHZ_UP 1 +#define PHY_TXC1_BW_20MHZ 2 +#define PHY_TXC1_BW_20MHZ_UP 3 +#define PHY_TXC1_BW_40MHZ 4 +#define PHY_TXC1_BW_40MHZ_DUP 5 +#define PHY_TXC1_MODE_SHIFT 3 +#define PHY_TXC1_MODE_MASK 0x0038 +#define PHY_TXC1_MODE_SISO 0 +#define PHY_TXC1_MODE_CDD 1 +#define PHY_TXC1_MODE_STBC 2 +#define PHY_TXC1_MODE_SDM 3 + +/* PhyTxControl for HTphy that are different from Mimophy */ +#define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */ + +/* XtraFrameTypes */ +#define XFTS_RTS_FT_SHIFT 2 +#define XFTS_FBRRTS_FT_SHIFT 4 +#define XFTS_CHANNEL_SHIFT 8 + +/* Antenna diversity bit in ant_wr_settle */ +#define PHY_AWS_ANTDIV 0x2000 + +/* IFS ctl */ +#define IFS_USEEDCF (1 << 2) + +/* IFS ctl1 */ +#define IFS_CTL1_EDCRS (1 << 3) +#define IFS_CTL1_EDCRS_20L (1 << 4) +#define IFS_CTL1_EDCRS_40 (1 << 5) + +/* ABI_MimoAntSel */ +#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00 +#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8 +#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0 +#define ABI_MAS_FBR_ANT_PTN_SHIFT 4 +#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f + +/* tx status packet */ +typedef struct tx_status tx_status_t; +struct tx_status { + u16 framelen; + u16 PAD; + u16 frameid; + u16 status; + u16 lasttxtime; + u16 sequence; + u16 phyerr; + u16 ackphyrxsh; +} __attribute__((packed)); + +#define TXSTATUS_LEN 16 + +/* status field bit definitions */ +#define TX_STATUS_FRM_RTX_MASK 0xF000 +#define TX_STATUS_FRM_RTX_SHIFT 12 +#define TX_STATUS_RTS_RTX_MASK 0x0F00 +#define TX_STATUS_RTS_RTX_SHIFT 8 +#define TX_STATUS_MASK 0x00FE +#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */ +#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */ +#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */ +#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */ +#define TX_STATUS_SUPR_SHIFT 2 +#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */ +#define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */ +#define TX_STATUS_NO_ACK 0 + +/* suppress status reason codes */ +#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */ +#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */ +#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */ +#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */ +#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */ +#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */ +#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */ + +/* Unexpected tx status for rate update */ +#define TX_STATUS_UNEXP(status) \ + ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \ + TX_STATUS_UNEXP_AMPDU(status)) + +/* Unexpected tx status for A-MPDU rate update */ +#define TX_STATUS_UNEXP_AMPDU(status) \ + ((((status) & TX_STATUS_SUPR_MASK) != 0) && \ + (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME)) + +#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */ +#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */ +#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */ +#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */ + +/* RXE (Receive Engine) */ + +/* RCM_CTL */ +#define RCM_INC_MASK_H 0x0080 +#define RCM_INC_MASK_L 0x0040 +#define RCM_INC_DATA 0x0020 +#define RCM_INDEX_MASK 0x001F +#define RCM_SIZE 15 + +#define RCM_MAC_OFFSET 0 /* current MAC address */ +#define RCM_BSSID_OFFSET 3 /* current BSSID address */ +#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */ +#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */ +#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */ + +#define RCM_WEP_TA0_OFFSET 16 +#define RCM_WEP_TA1_OFFSET 19 +#define RCM_WEP_TA2_OFFSET 22 +#define RCM_WEP_TA3_OFFSET 25 + +/* PSM Block */ + +/* psm_phy_hdr_param bits */ +#define MAC_PHY_RESET 1 +#define MAC_PHY_CLOCK_EN 2 +#define MAC_PHY_FORCE_CLK 4 + +/* WEP Block */ + +/* WEP_WKEY */ +#define WKEY_START (1 << 8) +#define WKEY_SEL_MASK 0x1F + +/* WEP data formats */ + +/* the number of RCMTA entries */ +#define RCMTA_SIZE 50 + +#define M_ADDR_BMP_BLK (0x37e * 2) +#define M_ADDR_BMP_BLK_SZ 12 + +#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */ +#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */ +#define ADDR_BMP_BSSID (1 << 2) /* BSSID */ +#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */ +#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */ +#define ADDR_BMP_RESERVED1 (1 << 5) +#define ADDR_BMP_RESERVED2 (1 << 6) +#define ADDR_BMP_RESERVED3 (1 << 7) +#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */ +#define ADDR_BMP_BSS_IDX_SHIFT 8 + +#define WSEC_MAX_RCMTA_KEYS 54 + +/* max keys in M_TKMICKEYS_BLK */ +#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */ + +/* max RXE match registers */ +#define WSEC_MAX_RXE_KEYS 4 + +/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */ +/* SKL (Security Key Lookup) */ +#define SKL_ALGO_MASK 0x0007 +#define SKL_ALGO_SHIFT 0 +#define SKL_KEYID_MASK 0x0008 +#define SKL_KEYID_SHIFT 3 +#define SKL_INDEX_MASK 0x03F0 +#define SKL_INDEX_SHIFT 4 +#define SKL_GRP_ALGO_MASK 0x1c00 +#define SKL_GRP_ALGO_SHIFT 10 + +/* additional bits defined for IBSS group key support */ +#define SKL_IBSS_INDEX_MASK 0x01F0 +#define SKL_IBSS_INDEX_SHIFT 4 +#define SKL_IBSS_KEYID1_MASK 0x0600 +#define SKL_IBSS_KEYID1_SHIFT 9 +#define SKL_IBSS_KEYID2_MASK 0x1800 +#define SKL_IBSS_KEYID2_SHIFT 11 +#define SKL_IBSS_KEYALGO_MASK 0xE000 +#define SKL_IBSS_KEYALGO_SHIFT 13 + +#define WSEC_MODE_OFF 0 +#define WSEC_MODE_HW 1 +#define WSEC_MODE_SW 2 + +#define WSEC_ALGO_OFF 0 +#define WSEC_ALGO_WEP1 1 +#define WSEC_ALGO_TKIP 2 +#define WSEC_ALGO_AES 3 +#define WSEC_ALGO_WEP128 4 +#define WSEC_ALGO_AES_LEGACY 5 +#define WSEC_ALGO_NALG 6 + +#define AES_MODE_NONE 0 +#define AES_MODE_CCM 1 + +/* WEP_CTL (Rev 0) */ +#define WECR0_KEYREG_SHIFT 0 +#define WECR0_KEYREG_MASK 0x7 +#define WECR0_DECRYPT (1 << 3) +#define WECR0_IVINLINE (1 << 4) +#define WECR0_WEPALG_SHIFT 5 +#define WECR0_WEPALG_MASK (0x7 << 5) +#define WECR0_WKEYSEL_SHIFT 8 +#define WECR0_WKEYSEL_MASK (0x7 << 8) +#define WECR0_WKEYSTART (1 << 11) +#define WECR0_WEPINIT (1 << 14) +#define WECR0_ICVERR (1 << 15) + +/* Frame template map byte offsets */ +#define T_ACTS_TPL_BASE (0) +#define T_NULL_TPL_BASE (0xc * 2) +#define T_QNULL_TPL_BASE (0x1c * 2) +#define T_RR_TPL_BASE (0x2c * 2) +#define T_BCN0_TPL_BASE (0x34 * 2) +#define T_PRS_TPL_BASE (0x134 * 2) +#define T_BCN1_TPL_BASE (0x234 * 2) +#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT)) + +#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */ + +#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */ + +/* Shared Mem byte offsets */ + +/* Location where the ucode expects the corerev */ +#define M_MACHW_VER (0x00b * 2) + +/* Location where the ucode expects the MAC capabilities */ +#define M_MACHW_CAP_L (0x060 * 2) +#define M_MACHW_CAP_H (0x061 * 2) + +/* WME shared memory */ +#define M_EDCF_STATUS_OFF (0x007 * 2) +#define M_TXF_CUR_INDEX (0x018 * 2) +#define M_EDCF_QINFO (0x120 * 2) + +/* PS-mode related parameters */ +#define M_DOT11_SLOT (0x008 * 2) +#define M_DOT11_DTIMPERIOD (0x009 * 2) +#define M_NOSLPZNATDTIM (0x026 * 2) + +/* Beacon-related parameters */ +#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */ +#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */ +#define M_BCN_TXTSF_OFFSET (0x00e * 2) +#define M_TIMBPOS_INBEACON (0x00f * 2) +#define M_SFRMTXCNTFBRTHSD (0x022 * 2) +#define M_LFRMTXCNTFBRTHSD (0x023 * 2) +#define M_BCN_PCTLWD (0x02a * 2) +#define M_BCN_LI (0x05b * 2) /* beacon listen interval */ + +/* MAX Rx Frame len */ +#define M_MAXRXFRM_LEN (0x010 * 2) + +/* ACK/CTS related params */ +#define M_RSP_PCTLWD (0x011 * 2) + +/* Hardware Power Control */ +#define M_TXPWR_N (0x012 * 2) +#define M_TXPWR_TARGET (0x013 * 2) +#define M_TXPWR_MAX (0x014 * 2) +#define M_TXPWR_CUR (0x019 * 2) + +/* Rx-related parameters */ +#define M_RX_PAD_DATA_OFFSET (0x01a * 2) + +/* WEP Shared mem data */ +#define M_SEC_DEFIVLOC (0x01e * 2) +#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2) +#define M_PHYVER (0x028 * 2) +#define M_PHYTYPE (0x029 * 2) +#define M_SECRXKEYS_PTR (0x02b * 2) +#define M_TKMICKEYS_PTR (0x059 * 2) +#define M_SECKINDXALGO_BLK (0x2ea * 2) +#define M_SECKINDXALGO_BLK_SZ 54 +#define M_SECPSMRXTAMCH_BLK (0x2fa * 2) +#define M_TKIP_TSC_TTAK (0x18c * 2) +#define D11_MAX_KEY_SIZE 16 + +#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */ + +/* Probe response related parameters */ +#define M_SSIDLEN (0x024 * 2) +#define M_PRB_RESP_FRM_LEN (0x025 * 2) +#define M_PRS_MAXTIME (0x03a * 2) +#define M_SSID (0xb0 * 2) +#define M_CTXPRS_BLK (0xc0 * 2) +#define C_CTX_PCTLWD_POS (0x4 * 2) + +/* Delta between OFDM and CCK power in CCK power boost mode */ +#define M_OFDM_OFFSET (0x027 * 2) + +/* TSSI for last 4 11b/g CCK packets transmitted */ +#define M_B_TSSI_0 (0x02c * 2) +#define M_B_TSSI_1 (0x02d * 2) + +/* Host flags to turn on ucode options */ +#define M_HOST_FLAGS1 (0x02f * 2) +#define M_HOST_FLAGS2 (0x030 * 2) +#define M_HOST_FLAGS3 (0x031 * 2) +#define M_HOST_FLAGS4 (0x03c * 2) +#define M_HOST_FLAGS5 (0x06a * 2) +#define M_HOST_FLAGS_SZ 16 + +#define M_RADAR_REG (0x033 * 2) + +/* TSSI for last 4 11a OFDM packets transmitted */ +#define M_A_TSSI_0 (0x034 * 2) +#define M_A_TSSI_1 (0x035 * 2) + +/* noise interference measurement */ +#define M_NOISE_IF_COUNT (0x034 * 2) +#define M_NOISE_IF_TIMEOUT (0x035 * 2) + +#define M_RF_RX_SP_REG1 (0x036 * 2) + +/* TSSI for last 4 11g OFDM packets transmitted */ +#define M_G_TSSI_0 (0x038 * 2) +#define M_G_TSSI_1 (0x039 * 2) + +/* Background noise measure */ +#define M_JSSI_0 (0x44 * 2) +#define M_JSSI_1 (0x45 * 2) +#define M_JSSI_AUX (0x46 * 2) + +#define M_CUR_2050_RADIOCODE (0x47 * 2) + +/* TX fifo sizes */ +#define M_FIFOSIZE0 (0x4c * 2) +#define M_FIFOSIZE1 (0x4d * 2) +#define M_FIFOSIZE2 (0x4e * 2) +#define M_FIFOSIZE3 (0x4f * 2) +#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */ + +/* Current channel number plus upper bits */ +#define M_CURCHANNEL (0x50 * 2) +#define D11_CURCHANNEL_5G 0x0100; +#define D11_CURCHANNEL_40 0x0200; +#define D11_CURCHANNEL_MAX 0x00FF; + +/* last posted frameid on the bcmc fifo */ +#define M_BCMC_FID (0x54 * 2) +#define INVALIDFID 0xffff + +/* extended beacon phyctl bytes for 11N */ +#define M_BCN_PCTL1WD (0x058 * 2) + +/* idle busy ratio to duty_cycle requirement */ +#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2) +#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2) + +/* CW RSSI for LCNPHY */ +#define M_LCN_RSSI_0 0x1332 +#define M_LCN_RSSI_1 0x1338 +#define M_LCN_RSSI_2 0x133e +#define M_LCN_RSSI_3 0x1344 + +/* SNR for LCNPHY */ +#define M_LCN_SNR_A_0 0x1334 +#define M_LCN_SNR_B_0 0x1336 + +#define M_LCN_SNR_A_1 0x133a +#define M_LCN_SNR_B_1 0x133c + +#define M_LCN_SNR_A_2 0x1340 +#define M_LCN_SNR_B_2 0x1342 + +#define M_LCN_SNR_A_3 0x1346 +#define M_LCN_SNR_B_3 0x1348 + +#define M_LCN_LAST_RESET (81*2) +#define M_LCN_LAST_LOC (63*2) +#define M_LCNPHY_RESET_STATUS (4902) +#define M_LCNPHY_DSC_TIME (0x98d*2) +#define M_LCNPHY_RESET_CNT_DSC (0x98b*2) +#define M_LCNPHY_RESET_CNT (0x98c*2) + +/* Rate table offsets */ +#define M_RT_DIRMAP_A (0xe0 * 2) +#define M_RT_BBRSMAP_A (0xf0 * 2) +#define M_RT_DIRMAP_B (0x100 * 2) +#define M_RT_BBRSMAP_B (0x110 * 2) + +/* Rate table entry offsets */ +#define M_RT_PRS_PLCP_POS 10 +#define M_RT_PRS_DUR_POS 16 +#define M_RT_OFDM_PCTL1_POS 18 + +#define M_20IN40_IQ (0x380 * 2) + +/* SHM locations where ucode stores the current power index */ +#define M_CURR_IDX1 (0x384 * 2) +#define M_CURR_IDX2 (0x387 * 2) + +#define M_BSCALE_ANT0 (0x5e * 2) +#define M_BSCALE_ANT1 (0x5f * 2) + +/* Antenna Diversity Testing */ +#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2) +#define M_ANTSEL_CLKDIV (0x61 * 2) +#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2) + +#define M_MIMO_MAXSYM (0x5d * 2) +#define MIMO_MAXSYM_DEF 0x8000 /* 32k */ +#define MIMO_MAXSYM_MAX 0xffff /* 64k */ + +#define M_WATCHDOG_8TU (0x1e * 2) +#define WATCHDOG_8TU_DEF 5 +#define WATCHDOG_8TU_MAX 10 + +/* Manufacturing Test Variables */ +#define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */ +#define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */ +#define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */ +#define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */ + +/* Index variation in vbat ripple */ +#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */ +#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */ + +/* M_PKTENG_CTRL bit definitions */ +#define M_PKTENG_MODE_TX 0x0001 +#define M_PKTENG_MODE_TX_RIFS 0x0004 +#define M_PKTENG_MODE_TX_CTS 0x0008 +#define M_PKTENG_MODE_RX 0x0002 +#define M_PKTENG_MODE_RX_WITH_ACK 0x0402 +#define M_PKTENG_MODE_MASK 0x0003 +#define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */ + +/* Sample Collect parameters (bitmap and type) */ +#define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */ +#define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */ + +#define ANTSEL_CLKDIV_4MHZ 6 +#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */ +#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */ +#define MIMO_ANTSEL_WAIT 50 /* 50us wait */ +#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */ + +typedef struct shm_acparams shm_acparams_t; +struct shm_acparams { + u16 txop; + u16 cwmin; + u16 cwmax; + u16 cwcur; + u16 aifs; + u16 bslots; + u16 reggap; + u16 status; + u16 rsvd[8]; +} __attribute__((packed)); +#define M_EDCF_QLEN (16 * 2) + +#define WME_STATUS_NEWAC (1 << 8) + +/* M_HOST_FLAGS */ +#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */ +#define MHF1 0 /* Hostflag 1 index */ +#define MHF2 1 /* Hostflag 2 index */ +#define MHF3 2 /* Hostflag 3 index */ +#define MHF4 3 /* Hostflag 4 index */ +#define MHF5 4 /* Hostflag 5 index */ + +/* Flags in M_HOST_FLAGS */ +#define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */ +#define MHF1_EDCF 0x0100 /* Enable EDCF access control */ +#define MHF1_IQSWAP_WAR 0x0200 +#define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */ + +/* Flags in M_HOST_FLAGS2 */ +#define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */ +#define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */ +#define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */ +#define MHF2_NPHY40MHZ_WAR 0x0800 + +/* Flags in M_HOST_FLAGS3 */ +#define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */ +#define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */ +#define MHF3_RESERVED1 0x0004 +#define MHF3_RESERVED2 0x0008 +#define MHF3_NPHY_MLADV_WAR 0x0010 + +/* Flags in M_HOST_FLAGS4 */ +#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */ +#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */ + +/* Flags in M_HOST_FLAGS5 */ +#define MHF5_4313_GPIOCTRL 0x0001 +#define MHF5_RESERVED1 0x0002 +#define MHF5_RESERVED2 0x0004 +/* Radio power setting for ucode */ +#define M_RADIO_PWR (0x32 * 2) + +/* phy noise recorded by ucode right after tx */ +#define M_PHY_NOISE (0x037 * 2) +#define PHY_NOISE_MASK 0x00ff + +/* Receive Frame Data Header for 802.11b DCF-only frames */ +typedef struct d11rxhdr d11rxhdr_t; +struct d11rxhdr { + u16 RxFrameSize; /* Actual byte length of the frame data received */ + u16 PAD; + u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */ + u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */ + u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */ + u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */ + u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */ + u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */ + u16 RxStatus1; /* MAC Rx Status */ + u16 RxStatus2; /* extended MAC Rx status */ + u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ + u16 RxChan; /* gain code, channel radio code, and phy type */ +} __attribute__((packed)); + +#define RXHDR_LEN 24 /* sizeof d11rxhdr_t */ +#define FRAMELEN(h) ((h)->RxFrameSize) + +typedef struct wlc_d11rxhdr wlc_d11rxhdr_t; +struct wlc_d11rxhdr { + d11rxhdr_t rxhdr; + u32 tsf_l; /* TSF_L reading */ + s8 rssi; /* computed instanteneous rssi in BMAC */ + s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ + s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ + s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */ + s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */ +} __attribute__((packed)); + +/* PhyRxStatus_0: */ +#define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */ +#define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */ +#define PRXS0_CLIP_SHIFT 2 +#define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */ +#define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */ +#define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */ +#define PRXS0_SHORTH 0x0080 /* Short Preamble */ +#define PRXS0_PLCPFV 0x0100 /* PLCP violation */ +#define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */ +#define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */ +#define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */ +#define PRXS0_ANTSEL_SHIFT 0x12 + +/* subfield PRXS0_FT_MASK */ +#define PRXS0_CCK 0x0000 +#define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */ +#define PRXS0_PREN 0x0002 +#define PRXS0_STDN 0x0003 + +/* subfield PRXS0_ANTSEL_MASK */ +#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */ +#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */ +#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */ +#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */ + +/* PhyRxStatus_1: */ +#define PRXS1_JSSI_MASK 0x00FF +#define PRXS1_JSSI_SHIFT 0 +#define PRXS1_SQ_MASK 0xFF00 +#define PRXS1_SQ_SHIFT 8 + +/* nphy PhyRxStatus_1: */ +#define PRXS1_nphy_PWR0_MASK 0x00FF +#define PRXS1_nphy_PWR1_MASK 0xFF00 + +/* HTPHY Rx Status defines */ +/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */ +#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */ +#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */ +#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */ + +/* htphy PhyRxStatus_1: */ +#define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */ +#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */ +#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */ + +/* htphy PhyRxStatus_2: */ +#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */ +#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */ +#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */ + +/* htphy PhyRxStatus_3: */ +#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */ +#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */ + +/* htphy PhyRxStatus_4: */ +#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */ +#define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */ + +/* htphy PhyRxStatus_5: */ +#define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */ +#define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */ + +#define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \ + (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8)) +/* Get Rx power on core 0 */ +#define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8) +/* Get Rx power on core 1 */ +#define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1) +/* Get Rx power on core 2 */ +#define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8) + +/* ucode RxStatus1: */ +#define RXS_BCNSENT 0x8000 +#define RXS_SECKINDX_MASK 0x07e0 +#define RXS_SECKINDX_SHIFT 5 +#define RXS_DECERR (1 << 4) +#define RXS_DECATMPT (1 << 3) +#define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */ +#define RXS_RESPFRAMETX (1 << 1) +#define RXS_FCSERR (1 << 0) + +/* ucode RxStatus2: */ +#define RXS_AMSDU_MASK 1 +#define RXS_AGGTYPE_MASK 0x6 +#define RXS_AGGTYPE_SHIFT 1 +#define RXS_PHYRXST_VALID (1 << 8) +#define RXS_RXANT_MASK 0x3 +#define RXS_RXANT_SHIFT 12 + +/* RxChan */ +#define RXS_CHAN_40 0x1000 +#define RXS_CHAN_5G 0x0800 +#define RXS_CHAN_ID_MASK 0x07f8 +#define RXS_CHAN_ID_SHIFT 3 +#define RXS_CHAN_PHYTYPE_MASK 0x0007 +#define RXS_CHAN_PHYTYPE_SHIFT 0 + +/* Index of attenuations used during ucode power control. */ +#define M_PWRIND_BLKS (0x184 * 2) +#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0) +#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2) +#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4) +#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6) +/* M_PWRIND_MAP(core) macro */ +#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1)) + +/* PSM SHM variable offsets */ +#define M_PSM_SOFT_REGS 0x0 +#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0) +#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2) +#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */ +#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */ + +#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */ +#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */ +#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */ +#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */ +#define M_PRETBTT (0x4b * 2) + +#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */ +#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2)) +#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2)) +#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2)) + +/* PKTENG Rx Stats Block */ +#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2)) + +/* ucode debug status codes */ +#define DBGST_INACTIVE 0 /* not valid really */ +#define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */ +#define DBGST_ACTIVE 2 /* "normal" state */ +#define DBGST_SUSPENDED 3 /* suspended */ +#define DBGST_ASLEEP 4 /* asleep (PS mode) */ + +/* Scratch Reg defs */ +typedef enum { + S_RSV0 = 0, + S_RSV1, + S_RSV2, + + /* scratch registers for Dot11-contants */ + S_DOT11_CWMIN, /* CW-minimum 0x03 */ + S_DOT11_CWMAX, /* CW-maximum 0x04 */ + S_DOT11_CWCUR, /* CW-current 0x05 */ + S_DOT11_SRC_LMT, /* short retry count limit 0x06 */ + S_DOT11_LRC_LMT, /* long retry count limit 0x07 */ + S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */ + + /* Tx-side scratch registers */ + S_SEQ_NUM, /* hardware sequence number reg 0x09 */ + S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */ + S_FRMRETX_CNT, /* frame retx count 0x0B */ + S_SSRC, /* Station short retry count 0x0C */ + S_SLRC, /* Station long retry count 0x0D */ + S_EXP_RSP, /* Expected response frame 0x0E */ + S_OLD_BREM, /* Remaining backoff ctr 0x0F */ + S_OLD_CWWIN, /* saved-off CW-cur 0x10 */ + S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */ + S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */ + + /* Rx-side scratch registers */ + S_RXTST, /* Type and subtype in Rxframe 0x13 */ + + /* Global state register */ + S_STREG, /* state storage actual bit maps below 0x14 */ + + S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */ + S_TXPWR_ITER, /* Tx power control: iteration 0x16 */ + S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */ + S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */ + + S_KEYINDX, /* 0x19 */ + S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */ + + /* Receive TSF time stored in SCR */ + S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */ + S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */ + S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */ + S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */ + S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */ + S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */ + + /* Scratch pad regs used in microcode as temp storage */ + S_TMP0, /* stmp0 0x21 */ + S_TMP1, /* stmp1 0x22 */ + S_TMP2, /* stmp2 0x23 */ + S_TMP3, /* stmp3 0x24 */ + S_TMP4, /* stmp4 0x25 */ + S_TMP5, /* stmp5 0x26 */ + S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */ + S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */ + S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */ + S_RXTP, /* rx frame type 0x2A */ + S_STREG2, /* extra state storage 0x2B */ + S_STREG3, /* even more extra state storage 0x2C */ + S_STREG4, /* ... 0x2D */ + S_STREG5, /* remember to initialize it to zero 0x2E */ + + S_ADJPWR_IDX, + S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */ + S_REVID4, /* 0x33 */ + S_INDX, /* 0x34 */ + S_ADDR0, /* 0x35 */ + S_ADDR1, /* 0x36 */ + S_ADDR2, /* 0x37 */ + S_ADDR3, /* 0x38 */ + S_ADDR4, /* 0x39 */ + S_ADDR5, /* 0x3A */ + S_TMP6, /* 0x3B */ + S_KEYINDX_BU, /* Backup for Key index 0x3C */ + S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */ + S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */ + S_STREG6, /* 0x3F */ +} ePsmScratchPadRegDefinitions; + +#define S_BEACON_INDX S_OLD_BREM +#define S_PRS_INDX S_OLD_CWWIN +#define S_PHYTYPE S_SSRC +#define S_PHYVER S_SLRC + +/* IHR SLOW_CTRL values */ +#define SLOW_CTRL_PDE (1 << 0) +#define SLOW_CTRL_FD (1 << 8) + +/* ucode mac statistic counters in shared memory */ +typedef struct macstat { + u16 txallfrm; /* 0x80 */ + u16 txrtsfrm; /* 0x82 */ + u16 txctsfrm; /* 0x84 */ + u16 txackfrm; /* 0x86 */ + u16 txdnlfrm; /* 0x88 */ + u16 txbcnfrm; /* 0x8a */ + u16 txfunfl[8]; /* 0x8c - 0x9b */ + u16 txtplunfl; /* 0x9c */ + u16 txphyerr; /* 0x9e */ + u16 pktengrxducast; /* 0xa0 */ + u16 pktengrxdmcast; /* 0xa2 */ + u16 rxfrmtoolong; /* 0xa4 */ + u16 rxfrmtooshrt; /* 0xa6 */ + u16 rxinvmachdr; /* 0xa8 */ + u16 rxbadfcs; /* 0xaa */ + u16 rxbadplcp; /* 0xac */ + u16 rxcrsglitch; /* 0xae */ + u16 rxstrt; /* 0xb0 */ + u16 rxdfrmucastmbss; /* 0xb2 */ + u16 rxmfrmucastmbss; /* 0xb4 */ + u16 rxcfrmucast; /* 0xb6 */ + u16 rxrtsucast; /* 0xb8 */ + u16 rxctsucast; /* 0xba */ + u16 rxackucast; /* 0xbc */ + u16 rxdfrmocast; /* 0xbe */ + u16 rxmfrmocast; /* 0xc0 */ + u16 rxcfrmocast; /* 0xc2 */ + u16 rxrtsocast; /* 0xc4 */ + u16 rxctsocast; /* 0xc6 */ + u16 rxdfrmmcast; /* 0xc8 */ + u16 rxmfrmmcast; /* 0xca */ + u16 rxcfrmmcast; /* 0xcc */ + u16 rxbeaconmbss; /* 0xce */ + u16 rxdfrmucastobss; /* 0xd0 */ + u16 rxbeaconobss; /* 0xd2 */ + u16 rxrsptmout; /* 0xd4 */ + u16 bcntxcancl; /* 0xd6 */ + u16 PAD; + u16 rxf0ovfl; /* 0xda */ + u16 rxf1ovfl; /* 0xdc */ + u16 rxf2ovfl; /* 0xde */ + u16 txsfovfl; /* 0xe0 */ + u16 pmqovfl; /* 0xe2 */ + u16 rxcgprqfrm; /* 0xe4 */ + u16 rxcgprsqovfl; /* 0xe6 */ + u16 txcgprsfail; /* 0xe8 */ + u16 txcgprssuc; /* 0xea */ + u16 prs_timeout; /* 0xec */ + u16 rxnack; + u16 frmscons; + u16 txnack; + u16 txglitch_nack; + u16 txburst; /* 0xf6 # tx bursts */ + u16 bphy_rxcrsglitch; /* bphy rx crs glitch */ + u16 phywatchdog; /* 0xfa # of phy watchdog events */ + u16 PAD; + u16 bphy_badplcp; /* bphy bad plcp */ +} macstat_t; + +/* dot11 core-specific control flags */ +#define SICF_PCLKE 0x0004 /* PHY clock enable */ +#define SICF_PRST 0x0008 /* PHY reset */ +#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */ +#define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */ +/* NOTE: the following bw bits only apply when the core is attached + * to a NPHY (and corerev >= 11 which it will always be for NPHYs). + */ +#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */ +#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */ +#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */ +#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */ +#define SICF_GMODE 0x2000 /* gmode enable */ + +/* dot11 core-specific status flags */ +#define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */ +#define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */ +#define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */ +#define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */ + +/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */ + +#define BPHY_REG_OFT_BASE 0x0 +/* offsets for indirect access to bphy registers */ +#define BPHY_BB_CONFIG 0x01 +#define BPHY_ADCBIAS 0x02 +#define BPHY_ANACORE 0x03 +#define BPHY_PHYCRSTH 0x06 +#define BPHY_TEST 0x0a +#define BPHY_PA_TX_TO 0x10 +#define BPHY_SYNTH_DC_TO 0x11 +#define BPHY_PA_TX_TIME_UP 0x12 +#define BPHY_RX_FLTR_TIME_UP 0x13 +#define BPHY_TX_POWER_OVERRIDE 0x14 +#define BPHY_RF_OVERRIDE 0x15 +#define BPHY_RF_TR_LOOKUP1 0x16 +#define BPHY_RF_TR_LOOKUP2 0x17 +#define BPHY_COEFFS 0x18 +#define BPHY_PLL_OUT 0x19 +#define BPHY_REFRESH_MAIN 0x1a +#define BPHY_REFRESH_TO0 0x1b +#define BPHY_REFRESH_TO1 0x1c +#define BPHY_RSSI_TRESH 0x20 +#define BPHY_IQ_TRESH_HH 0x21 +#define BPHY_IQ_TRESH_H 0x22 +#define BPHY_IQ_TRESH_L 0x23 +#define BPHY_IQ_TRESH_LL 0x24 +#define BPHY_GAIN 0x25 +#define BPHY_LNA_GAIN_RANGE 0x26 +#define BPHY_JSSI 0x27 +#define BPHY_TSSI_CTL 0x28 +#define BPHY_TSSI 0x29 +#define BPHY_TR_LOSS_CTL 0x2a +#define BPHY_LO_LEAKAGE 0x2b +#define BPHY_LO_RSSI_ACC 0x2c +#define BPHY_LO_IQMAG_ACC 0x2d +#define BPHY_TX_DC_OFF1 0x2e +#define BPHY_TX_DC_OFF2 0x2f +#define BPHY_PEAK_CNT_THRESH 0x30 +#define BPHY_FREQ_OFFSET 0x31 +#define BPHY_DIVERSITY_CTL 0x32 +#define BPHY_PEAK_ENERGY_LO 0x33 +#define BPHY_PEAK_ENERGY_HI 0x34 +#define BPHY_SYNC_CTL 0x35 +#define BPHY_TX_PWR_CTRL 0x36 +#define BPHY_TX_EST_PWR 0x37 +#define BPHY_STEP 0x38 +#define BPHY_WARMUP 0x39 +#define BPHY_LMS_CFF_READ 0x3a +#define BPHY_LMS_COEFF_I 0x3b +#define BPHY_LMS_COEFF_Q 0x3c +#define BPHY_SIG_POW 0x3d +#define BPHY_RFDC_CANCEL_CTL 0x3e +#define BPHY_HDR_TYPE 0x40 +#define BPHY_SFD_TO 0x41 +#define BPHY_SFD_CTL 0x42 +#define BPHY_DEBUG 0x43 +#define BPHY_RX_DELAY_COMP 0x44 +#define BPHY_CRS_DROP_TO 0x45 +#define BPHY_SHORT_SFD_NZEROS 0x46 +#define BPHY_DSSS_COEFF1 0x48 +#define BPHY_DSSS_COEFF2 0x49 +#define BPHY_CCK_COEFF1 0x4a +#define BPHY_CCK_COEFF2 0x4b +#define BPHY_TR_CORR 0x4c +#define BPHY_ANGLE_SCALE 0x4d +#define BPHY_TX_PWR_BASE_IDX 0x4e +#define BPHY_OPTIONAL_MODES2 0x4f +#define BPHY_CCK_LMS_STEP 0x50 +#define BPHY_BYPASS 0x51 +#define BPHY_CCK_DELAY_LONG 0x52 +#define BPHY_CCK_DELAY_SHORT 0x53 +#define BPHY_PPROC_CHAN_DELAY 0x54 +#define BPHY_DDFS_ENABLE 0x58 +#define BPHY_PHASE_SCALE 0x59 +#define BPHY_FREQ_CONTROL 0x5a +#define BPHY_LNA_GAIN_RANGE_10 0x5b +#define BPHY_LNA_GAIN_RANGE_32 0x5c +#define BPHY_OPTIONAL_MODES 0x5d +#define BPHY_RX_STATUS2 0x5e +#define BPHY_RX_STATUS3 0x5f +#define BPHY_DAC_CONTROL 0x60 +#define BPHY_ANA11G_FILT_CTRL 0x62 +#define BPHY_REFRESH_CTRL 0x64 +#define BPHY_RF_OVERRIDE2 0x65 +#define BPHY_SPUR_CANCEL_CTRL 0x66 +#define BPHY_FINE_DIGIGAIN_CTRL 0x67 +#define BPHY_RSSI_LUT 0x88 +#define BPHY_RSSI_LUT_END 0xa7 +#define BPHY_TSSI_LUT 0xa8 +#define BPHY_TSSI_LUT_END 0xc7 +#define BPHY_TSSI2PWR_LUT 0x380 +#define BPHY_TSSI2PWR_LUT_END 0x39f +#define BPHY_LOCOMP_LUT 0x3a0 +#define BPHY_LOCOMP_LUT_END 0x3bf +#define BPHY_TXGAIN_LUT 0x3c0 +#define BPHY_TXGAIN_LUT_END 0x3ff + +/* Bits in BB_CONFIG: */ +#define PHY_BBC_ANT_MASK 0x0180 +#define PHY_BBC_ANT_SHIFT 7 +#define BB_DARWIN 0x1000 +#define BBCFG_RESETCCA 0x4000 +#define BBCFG_RESETRX 0x8000 + +/* Bits in phytest(0x0a): */ +#define TST_DDFS 0x2000 +#define TST_TXFILT1 0x0800 +#define TST_UNSCRAM 0x0400 +#define TST_CARR_SUPP 0x0200 +#define TST_DC_COMP_LOOP 0x0100 +#define TST_LOOPBACK 0x0080 +#define TST_TXFILT0 0x0040 +#define TST_TXTEST_ENABLE 0x0020 +#define TST_TXTEST_RATE 0x0018 +#define TST_TXTEST_PHASE 0x0007 + +/* phytest txTestRate values */ +#define TST_TXTEST_RATE_1MBPS 0 +#define TST_TXTEST_RATE_2MBPS 1 +#define TST_TXTEST_RATE_5_5MBPS 2 +#define TST_TXTEST_RATE_11MBPS 3 +#define TST_TXTEST_RATE_SHIFT 3 + +#define SHM_BYT_CNT 0x2 /* IHR location */ +#define MAX_BYT_CNT 0x600 /* Maximum frame len */ + +#endif /* _D11_H */ diff --git a/drivers/staging/brcm80211/brcmsmac/sbhndpio.h b/drivers/staging/brcm80211/brcmsmac/sbhndpio.h new file mode 100644 index 000000000000..9eabdb56da73 --- /dev/null +++ b/drivers/staging/brcm80211/brcmsmac/sbhndpio.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _sbhndpio_h_ +#define _sbhndpio_h_ + +/* PIO structure, + * support two PIO format: 2 bytes access and 4 bytes access + * basic FIFO register set is per channel(transmit or receive) + * a pair of channels is defined for convenience + */ + +/* 2byte-wide pio register set per channel(xmt or rcv) */ +typedef volatile struct { + u16 fifocontrol; + u16 fifodata; + u16 fifofree; /* only valid in xmt channel, not in rcv channel */ + u16 PAD; +} pio2regs_t; + +/* a pair of pio channels(tx and rx) */ +typedef volatile struct { + pio2regs_t tx; + pio2regs_t rx; +} pio2regp_t; + +/* 4byte-wide pio register set per channel(xmt or rcv) */ +typedef volatile struct { + u32 fifocontrol; + u32 fifodata; +} pio4regs_t; + +/* a pair of pio channels(tx and rx) */ +typedef volatile struct { + pio4regs_t tx; + pio4regs_t rx; +} pio4regp_t; + +#endif /* _sbhndpio_h_ */ diff --git a/drivers/staging/brcm80211/brcmsmac/sys/wlc_event.c b/drivers/staging/brcm80211/brcmsmac/sys/wlc_event.c index dabd7094cd73..12b156a82ff2 100644 --- a/drivers/staging/brcm80211/brcmsmac/sys/wlc_event.c +++ b/drivers/staging/brcm80211/brcmsmac/sys/wlc_event.c @@ -33,9 +33,6 @@ #include #include #include -#ifdef MSGTRACE -#include -#endif #include /* Local prototypes */ diff --git a/drivers/staging/brcm80211/include/bcmcdc.h b/drivers/staging/brcm80211/include/bcmcdc.h deleted file mode 100644 index ed4c4a517eca..000000000000 --- a/drivers/staging/brcm80211/include/bcmcdc.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include - -typedef struct cdc_ioctl { - u32 cmd; /* ioctl command value */ - u32 len; /* lower 16: output buflen; upper 16: - input buflen (excludes header) */ - u32 flags; /* flag defns given below */ - u32 status; /* status code returned from the device */ -} cdc_ioctl_t; - -/* Max valid buffer size that can be sent to the dongle */ -#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN) - -/* len field is divided into input and output buffer lengths */ -#define CDCL_IOC_OUTLEN_MASK 0x0000FFFF /* maximum or expected - response length, */ - /* excluding IOCTL header */ -#define CDCL_IOC_OUTLEN_SHIFT 0 -#define CDCL_IOC_INLEN_MASK 0xFFFF0000 /* input buffer length, - excluding IOCTL header */ -#define CDCL_IOC_INLEN_SHIFT 16 - -/* CDC flag definitions */ -#define CDCF_IOC_ERROR 0x01 /* 0=success, 1=ioctl cmd failed */ -#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */ -#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */ -#define CDCF_IOC_IF_SHIFT 12 -#define CDCF_IOC_ID_MASK 0xFFFF0000 /* used to uniquely id an ioctl - req/resp pairing */ -#define CDCF_IOC_ID_SHIFT 16 /* # of bits of shift for ID Mask */ - -#define CDC_IOC_IF_IDX(flags) \ - (((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT) -#define CDC_IOC_ID(flags) \ - (((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT) - -#define CDC_GET_IF_IDX(hdr) \ - ((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)) -#define CDC_SET_IF_IDX(hdr, idx) \ - ((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | \ - ((idx) << CDCF_IOC_IF_SHIFT))) - -/* - * BDC header - * - * The BDC header is used on data packets to convey priority across USB. - */ - -#define BDC_HEADER_LEN 4 - -#define BDC_PROTO_VER 1 /* Protocol version */ - -#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */ -#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */ - -#define BDC_FLAG__UNUSED 0x03 /* Unassigned */ -#define BDC_FLAG_SUM_GOOD 0x04 /* Dongle has verified good - RX checksums */ -#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */ - -#define BDC_PRIORITY_MASK 0x7 - -#define BDC_FLAG2_FC_FLAG 0x10 /* flag to indicate if pkt contains */ - /* FLOW CONTROL info only */ -#define BDC_PRIORITY_FC_SHIFT 4 /* flow control info shift */ - -#define BDC_FLAG2_IF_MASK 0x0f /* APSTA: interface on which the - packet was received */ -#define BDC_FLAG2_IF_SHIFT 0 - -#define BDC_GET_IF_IDX(hdr) \ - ((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT)) -#define BDC_SET_IF_IDX(hdr, idx) \ - ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \ - ((idx) << BDC_FLAG2_IF_SHIFT))) - -struct bdc_header { - u8 flags; /* Flags */ - u8 priority; /* 802.1d Priority 0:2 bits, 4:7 flow - control info for usb */ - u8 flags2; - u8 rssi; -}; diff --git a/drivers/staging/brcm80211/include/bcmsdbus.h b/drivers/staging/brcm80211/include/bcmsdbus.h deleted file mode 100644 index 89059dd8088b..000000000000 --- a/drivers/staging/brcm80211/include/bcmsdbus.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _sdio_api_h_ -#define _sdio_api_h_ - -#define SDIOH_API_RC_SUCCESS (0x00) -#define SDIOH_API_RC_FAIL (0x01) -#define SDIOH_API_SUCCESS(status) (status == 0) - -#define SDIOH_READ 0 /* Read request */ -#define SDIOH_WRITE 1 /* Write request */ - -#define SDIOH_DATA_FIX 0 /* Fixed addressing */ -#define SDIOH_DATA_INC 1 /* Incremental addressing */ - -#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */ -#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */ -#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */ - -#define SDIOH_DATA_PIO 0 /* PIO mode */ -#define SDIOH_DATA_DMA 1 /* DMA mode */ - -typedef int SDIOH_API_RC; - -/* SDio Host structure */ -typedef struct sdioh_info sdioh_info_t; - -/* callback function, taking one arg */ -typedef void (*sdioh_cb_fn_t) (void *); - -/* attach, return handler on success, NULL if failed. - * The handler shall be provided by all subsequent calls. No local cache - * cfghdl points to the starting address of pci device mapped memory - */ -extern sdioh_info_t *sdioh_attach(struct osl_info *osh, void *cfghdl, uint irq); -extern SDIOH_API_RC sdioh_detach(struct osl_info *osh, sdioh_info_t *si); -extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, - sdioh_cb_fn_t fn, void *argh); -extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si); - -/* query whether SD interrupt is enabled or not */ -extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff); - -/* enable or disable SD interrupt */ -extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable); - -#if defined(BCMDBG) -extern bool sdioh_interrupt_pending(sdioh_info_t *si); -#endif - -extern int sdioh_claim_host_and_lock(sdioh_info_t *si); -extern int sdioh_release_host_and_unlock(sdioh_info_t *si); - -/* read or write one byte using cmd52 */ -extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, - uint addr, u8 *byte); - -/* read or write 2/4 bytes using cmd53 */ -extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, - uint rw, uint fnc, uint addr, - u32 *word, uint nbyte); - -/* read or write any buffer using cmd53 */ -extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, - uint fix_inc, uint rw, uint fnc_num, - u32 addr, uint regwidth, - u32 buflen, u8 *buffer, - struct sk_buff *pkt); - -/* get cis data */ -extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis, - u32 length); - -extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, u32 addr, - u8 *data); -extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, u32 addr, - u8 *data); - -/* query number of io functions */ -extern uint sdioh_query_iofnum(sdioh_info_t *si); - -/* handle iovars */ -extern int sdioh_iovar_op(sdioh_info_t *si, const char *name, - void *params, int plen, void *arg, int len, bool set); - -/* Issue abort to the specified function and clear controller as needed */ -extern int sdioh_abort(sdioh_info_t *si, uint fnc); - -/* Start and Stop SDIO without re-enumerating the SD card. */ -extern int sdioh_start(sdioh_info_t *si, int stage); -extern int sdioh_stop(sdioh_info_t *si); - -/* Reset and re-initialize the device */ -extern int sdioh_sdio_reset(sdioh_info_t *si); - -/* Helper function */ -void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh); - -#endif /* _sdio_api_h_ */ diff --git a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h b/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h deleted file mode 100644 index 4d671ddb3af1..000000000000 --- a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef __BCMSDH_SDMMC_H__ -#define __BCMSDH_SDMMC_H__ - -#ifdef BCMDBG -#define sd_err(x) do { if ((sd_msglevel & SDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0) -#define sd_trace(x) do { if ((sd_msglevel & SDH_TRACE_VAL) && net_ratelimit()) printf x; } while (0) -#define sd_info(x) do { if ((sd_msglevel & SDH_INFO_VAL) && net_ratelimit()) printf x; } while (0) -#define sd_debug(x) do { if ((sd_msglevel & SDH_DEBUG_VAL) && net_ratelimit()) printf x; } while (0) -#define sd_data(x) do { if ((sd_msglevel & SDH_DATA_VAL) && net_ratelimit()) printf x; } while (0) -#define sd_ctrl(x) do { if ((sd_msglevel & SDH_CTRL_VAL) && net_ratelimit()) printf x; } while (0) -#else -#define sd_err(x) -#define sd_trace(x) -#define sd_info(x) -#define sd_debug(x) -#define sd_data(x) -#define sd_ctrl(x) -#endif - -/* Allocate/init/free per-OS private data */ -extern int sdioh_sdmmc_osinit(sdioh_info_t *sd); -extern void sdioh_sdmmc_osfree(sdioh_info_t *sd); - -#define BLOCK_SIZE_64 64 -#define BLOCK_SIZE_512 512 -#define BLOCK_SIZE_4318 64 -#define BLOCK_SIZE_4328 512 - -/* internal return code */ -#define SUCCESS 0 -#define ERROR 1 - -/* private bus modes */ -#define SDIOH_MODE_SD4 2 -#define CLIENT_INTR 0x100 /* Get rid of this! */ - -struct sdioh_info { - struct osl_info *osh; /* osh handler */ - bool client_intr_enabled; /* interrupt connnected flag */ - bool intr_handler_valid; /* client driver interrupt handler valid */ - sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ - void *intr_handler_arg; /* argument to call interrupt handler */ - u16 intmask; /* Current active interrupts */ - void *sdos_info; /* Pointer to per-OS private data */ - - uint irq; /* Client irq */ - int intrcount; /* Client interrupts */ - bool sd_use_dma; /* DMA on CMD53 */ - bool sd_blockmode; /* sd_blockmode == false => 64 Byte Cmd 53s. */ - /* Must be on for sd_multiblock to be effective */ - bool use_client_ints; /* If this is false, make sure to restore */ - int sd_mode; /* SD1/SD4/SPI */ - int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ - u8 num_funcs; /* Supported funcs on client */ - u32 com_cis_ptr; - u32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; - uint max_dma_len; - uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */ - /* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */ -}; - -/************************************************************ - * Internal interfaces: per-port references into bcmsdh_sdmmc.c - */ - -/* Global message bits */ -extern uint sd_msglevel; - -/* OS-independent interrupt handler */ -extern bool check_client_intr(sdioh_info_t *sd); - -/* Core interrupt enable/disable of device interrupts */ -extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd); -extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd); - -/************************************************************** - * Internal interfaces: bcmsdh_sdmmc.c references to per-port code - */ - -/* Register mapping routines */ -extern u32 *sdioh_sdmmc_reg_map(struct osl_info *osh, s32 addr, int size); -extern void sdioh_sdmmc_reg_unmap(struct osl_info *osh, s32 addr, int size); - -/* Interrupt (de)registration routines */ -extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq); -extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd); - -typedef struct _BCMSDH_SDMMC_INSTANCE { - sdioh_info_t *sd; - struct sdio_func *func[SDIOD_MAX_IOFUNCS]; - u32 host_claimed; -} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE; - -#endif /* __BCMSDH_SDMMC_H__ */ diff --git a/drivers/staging/brcm80211/include/bcmsrom_tbl.h b/drivers/staging/brcm80211/include/bcmsrom_tbl.h deleted file mode 100644 index 22ae7c1c18fb..000000000000 --- a/drivers/staging/brcm80211/include/bcmsrom_tbl.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _bcmsrom_tbl_h_ -#define _bcmsrom_tbl_h_ - -#include "sbpcmcia.h" -#include "wlioctl.h" - -typedef struct { - const char *name; - u32 revmask; - u32 flags; - u16 off; - u16 mask; -} sromvar_t; - -#define SRFL_MORE 1 /* value continues as described by the next entry */ -#define SRFL_NOFFS 2 /* value bits can't be all one's */ -#define SRFL_PRHEX 4 /* value is in hexdecimal format */ -#define SRFL_PRSIGN 8 /* value is in signed decimal format */ -#define SRFL_CCODE 0x10 /* value is in country code format */ -#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ -#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ -#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ - -/* Assumptions: - * - Ethernet address spans across 3 consective words - * - * Table rules: - * - Add multiple entries next to each other if a value spans across multiple words - * (even multiple fields in the same word) with each entry except the last having - * it's SRFL_MORE bit set. - * - Ethernet address entry does not follow above rule and must not have SRFL_MORE - * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. - * - The last entry's name field must be NULL to indicate the end of the table. Other - * entries must have non-NULL name. - */ - -static const sromvar_t pci_sromvars[] = { - {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff}, - {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, - {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, - {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, - {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, - {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, - {"", 0, 0, SROM_BFL2, 0xffff}, - {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, - {"", 0, 0, SROM3_BFL2, 0xffff}, - {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff}, - {"", 0, 0, SROM4_BFL1, 0xffff}, - {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff}, - {"", 0, 0, SROM5_BFL1, 0xffff}, - {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff}, - {"", 0, 0, SROM8_BFL1, 0xffff}, - {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff}, - {"", 0, 0, SROM4_BFL3, 0xffff}, - {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff}, - {"", 0, 0, SROM5_BFL3, 0xffff}, - {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff}, - {"", 0, 0, SROM8_BFL3, 0xffff}, - {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, - {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, - {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, - {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, - {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, - {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff}, - {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, - {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, - {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff}, - {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff}, - {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff}, - {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff}, - {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, - {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff}, - {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, - {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff}, - {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, - {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff}, - {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, - {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff}, - {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, - {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff}, - {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, - {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, - {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, - {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, - {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, - {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, - {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, - {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, - {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, - {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, - {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, - {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, - {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, - {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, - {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff}, - {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, - {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff}, - {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, - {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, - {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff}, - {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, - {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, - {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00}, - {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, - {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, - {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, - {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, - {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, - {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, - {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff}, - {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00}, - {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff}, - {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00}, - {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, - {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, - {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, - {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, - {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, - {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, - {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, - {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, - {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, - {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, - {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, - {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, - {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, - {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, - {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, - {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, - {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, - {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, - {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, - {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, - {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, - {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, - {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00}, - {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff}, - {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, - {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, - {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, - {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, - {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, - {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, - {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, - {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, - {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, - {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, - {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, - {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, - {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, - {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, - {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, - {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, - {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, - {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, - {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, - {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, - {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, - {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, - {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff}, - {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00}, - {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff}, - {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, - {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, - {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, - {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, - {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, - {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, - {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, - {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, - {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, - {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, - {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, - {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, - {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, - {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, - {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, - {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, - {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, - {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, - {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, - {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, - {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, - {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00}, - {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff}, - {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, - {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, - {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, - {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, - {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, - {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, - {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, - {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, - {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, - {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, - {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, - {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, - {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, - {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, - {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, - {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, - - {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, - {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, - {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, - {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, - {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, - {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, - {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, - {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, - {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, - {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, - {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff}, - {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff}, - {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff}, - {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff}, - {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, - {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, - {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, - 0x00ff}, - {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, - {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, - 0x0300}, - {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, - 0x000f}, - {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, - {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, - {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, - - {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, - {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, - {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, - {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, - {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, - {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, - {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, - {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, - {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, - {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, - {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, - {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, - {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, - {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, - {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, - {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, - {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, - {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, - {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, - {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, - {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, - {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, - {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, - {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, - {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, - {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, - {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, - {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, - {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, - {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, - {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, - {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, - {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, - {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, - {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, - {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, - {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, - {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, - {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, - {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, - {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, - {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, - {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, - {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, - {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, - {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, - {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, - {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, - {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, - {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, - {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, - {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, - {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, - {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, - {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, - {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, - {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, - {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, - {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, - {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, - {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, - {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, - {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, - {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, - {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, - {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, - {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, - {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, - {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, - {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, - {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, - {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, - {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, - {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, - {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, - {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, - {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, - {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, - {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, - {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, - {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, - {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, - {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, - {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, - - /* power per rate from sromrev 9 */ - {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff}, - {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, - {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20, - 0xffff}, - {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, - {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, - 0xffff}, - {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, - {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, - 0xffff}, - {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, - {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, - {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, - 0xffff}, - {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, - {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, - {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, - 0xffff}, - {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, - {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, - {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, - {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, - {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, - {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, - {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, - {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, - {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, - {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, - {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, - {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, - {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, - {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, - {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, - {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, - {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, - {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, - {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, - {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, - {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, - 0xffff}, - {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, - {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, - {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, - {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff}, - {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff}, - - {NULL, 0, 0, 0, 0} -}; - -static const sromvar_t perpath_pci_sromvars[] = { - {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, - {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, - {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, - {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, - {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, - {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, - {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, - {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, - {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, - {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, - {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, - {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, - {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, - {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, - {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, - {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, - {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, - {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, - {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, - {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, - {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, - {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, - {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff}, - {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, - {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, - {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, - {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, - {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, - {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff}, - {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff}, - {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00}, - {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, - {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, - {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, - {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, - {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, - {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, - {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, - {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, - {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, - {NULL, 0, 0, 0, 0} -}; - -#if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) -#define PHY_TYPE_N 4 /* N-Phy value */ -#define PHY_TYPE_LP 5 /* LP-Phy value */ -#endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */ -#if !defined(PHY_TYPE_NULL) -#define PHY_TYPE_NULL 0xf /* Invalid Phy value */ -#endif /* !defined(PHY_TYPE_NULL) */ - -typedef struct { - u16 phy_type; - u16 bandrange; - u16 chain; - const char *vars; -} pavars_t; - -static const pavars_t pavars[] = { - /* NPHY */ - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0, - "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1, - "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0, - "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1, - "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, - /* LPPHY */ - {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"}, - {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"}, - {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"}, - {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"}, - {PHY_TYPE_NULL, 0, 0, ""} -}; - -typedef struct { - u16 phy_type; - u16 bandrange; - const char *vars; -} povars_t; - -static const povars_t povars[] = { - /* NPHY */ - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, - "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 " - "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, - "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 " - "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, - "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 " - "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"}, - {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, - "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 " - "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"}, - {PHY_TYPE_NULL, 0, ""} -}; - -typedef struct { - u8 tag; /* Broadcom subtag name */ - u8 len; /* Length field of the tuple, note that it includes the - * subtag name (1 byte): 1 + tuple content length - */ - const char *params; -} cis_tuple_t; - -#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ -#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ -#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ -#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ - -static const cis_tuple_t cis_hnbuvars[] = { - {OTP_RAW1, 0, ""}, /* special case */ - {OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */ - {OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */ - {HNBU_SROMREV, 2, "1sromrev"}, - /* NOTE: subdevid is also written to boardtype. - * Need to write HNBU_BOARDTYPE to change it if it is different. - */ - {HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, - {HNBU_BOARDREV, 3, "2boardrev"}, - {HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, - {HNBU_AA, 3, "1aa2g 1aa5g"}, - {HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */ - {HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"}, - {HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"}, - {HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"}, - {HNBU_CCODE, 4, "2ccode 1cctl"}, - {HNBU_CCKPO, 3, "2cckpo"}, - {HNBU_OFDMPO, 5, "4ofdmpo"}, - {HNBU_RDLID, 3, "2rdlid"}, - {HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */ - {HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */ - {HNBU_XTALFREQ, 5, "4xtalfreq"}, - {HNBU_TRI2G, 2, "1tri2g"}, - {HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"}, - {HNBU_RXPO2G, 2, "1rxpo2g"}, - {HNBU_RXPO5G, 2, "1rxpo5g"}, - {HNBU_BOARDNUM, 3, "2boardnum"}, - {HNBU_MACADDR, 7, "6macaddr"}, /* special case */ - {HNBU_RDLSN, 3, "2rdlsn"}, - {HNBU_BOARDTYPE, 3, "2boardtype"}, - {HNBU_LEDDC, 3, "2leddc"}, - {HNBU_RDLRNDIS, 2, "1rdlndis"}, - {HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"}, - {HNBU_REGREV, 2, "1regrev"}, - {HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g" "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"}, /* special case */ - {HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " - "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 " - "2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 " - "2pa5ghw1a0 2pa5ghw2a0"}, - {HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " - "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 " - "2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 " - "2pa5ghw1a1 2pa5ghw2a1"}, - {HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " - "4ofdm5ghpo"}, - {HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " - "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, - {HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " - "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, - {HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " - "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " - "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " - "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, - {HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"}, - {HNBU_PO_CDD, 3, "2cddpo"}, - {HNBU_PO_STBC, 3, "2stbcpo"}, - {HNBU_PO_40M, 3, "2bw40po"}, - {HNBU_PO_40MDUP, 3, "2bwduppo"}, - {HNBU_RDLRWU, 2, "1rdlrwu"}, - {HNBU_WPS, 3, "1wpsgpio 1wpsled"}, - {HNBU_USBFS, 2, "1usbfs"}, - {HNBU_CUSTOM1, 5, "4customvar1"}, - {OTP_RAW, 0, ""}, /* special case */ - {HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, - {HNBU_USBEPNUM, 3, "2usbepnum"}, - {0xFF, 0, ""} -}; - -#endif /* _bcmsrom_tbl_h_ */ diff --git a/drivers/staging/brcm80211/include/d11.h b/drivers/staging/brcm80211/include/d11.h deleted file mode 100644 index 50883af62496..000000000000 --- a/drivers/staging/brcm80211/include/d11.h +++ /dev/null @@ -1,1765 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _D11_H -#define _D11_H - -#ifndef WL_RSSI_ANT_MAX -#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */ -#elif WL_RSSI_ANT_MAX != 4 -#error "WL_RSSI_ANT_MAX does not match" -#endif - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -#define BCN_TMPL_LEN 512 /* length of the BCN template area */ - -/* RX FIFO numbers */ -#define RX_FIFO 0 /* data and ctl frames */ -#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */ - -/* TX FIFO numbers using WME Access Classes */ -#define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */ -#define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */ -#define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */ -#define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */ -#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */ -#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */ - -/* Addr is byte address used by SW; offset is word offset used by uCode */ - -/* Per AC TX limit settings */ -#define M_AC_TXLMT_BASE_ADDR (0x180 * 2) -#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac))) - -/* Legacy TX FIFO numbers */ -#define TX_DATA_FIFO TX_AC_BE_FIFO -#define TX_CTL_FIFO TX_AC_VO_FIFO - -typedef volatile struct { - u32 intstatus; - u32 intmask; -} intctrlregs_t; - -/* read: 32-bit register that can be read as 32-bit or as 2 16-bit - * write: only low 16b-it half can be written - */ -typedef volatile union { - u32 pmqhostdata; /* read only! */ - struct { - u16 pmqctrlstatus; /* read/write */ - u16 PAD; - } w; -} pmqreg_t; - -/* pio register set 2/4 bytes union for d11 fifo */ -typedef volatile union { - pio2regp_t b2; /* < corerev 8 */ - pio4regp_t b4; /* >= corerev 8 */ -} u_pioreg_t; - -/* dma/pio corerev < 11 */ -typedef volatile struct { - dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */ - u_pioreg_t pioregs[8]; /* 0x300 */ -} fifo32_t; - -/* dma/pio corerev >= 11 */ -typedef volatile struct { - dma64regs_t dmaxmt; /* dma tx */ - pio4regs_t piotx; /* pio tx */ - dma64regs_t dmarcv; /* dma rx */ - pio4regs_t piorx; /* pio rx */ -} fifo64_t; - -/* - * Host Interface Registers - * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h - * - but definitely not complete - */ -typedef volatile struct _d11regs { - /* Device Control ("semi-standard host registers") */ - u32 PAD[3]; /* 0x0 - 0x8 */ - u32 biststatus; /* 0xC */ - u32 biststatus2; /* 0x10 */ - u32 PAD; /* 0x14 */ - u32 gptimer; /* 0x18 *//* for corerev >= 3 */ - u32 usectimer; /* 0x1c *//* for corerev >= 26 */ - - /* Interrupt Control *//* 0x20 */ - intctrlregs_t intctrlregs[8]; - - u32 PAD[40]; /* 0x60 - 0xFC */ - - /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */ - u32 intrcvlazy[4]; /* 0x100 - 0x10C */ - - u32 PAD[4]; /* 0x110 - 0x11c */ - - u32 maccontrol; /* 0x120 */ - u32 maccommand; /* 0x124 */ - u32 macintstatus; /* 0x128 */ - u32 macintmask; /* 0x12C */ - - /* Transmit Template Access */ - u32 tplatewrptr; /* 0x130 */ - u32 tplatewrdata; /* 0x134 */ - u32 PAD[2]; /* 0x138 - 0x13C */ - - /* PMQ registers */ - pmqreg_t pmqreg; /* 0x140 */ - u32 pmqpatl; /* 0x144 */ - u32 pmqpath; /* 0x148 */ - u32 PAD; /* 0x14C */ - - u32 chnstatus; /* 0x150 */ - u32 psmdebug; /* 0x154 *//* for corerev >= 3 */ - u32 phydebug; /* 0x158 *//* for corerev >= 3 */ - u32 machwcap; /* 0x15C *//* Corerev >= 13 */ - - /* Extended Internal Objects */ - u32 objaddr; /* 0x160 */ - u32 objdata; /* 0x164 */ - u32 PAD[2]; /* 0x168 - 0x16c */ - - /* New txstatus registers on corerev >= 5 */ - u32 frmtxstatus; /* 0x170 */ - u32 frmtxstatus2; /* 0x174 */ - u32 PAD[2]; /* 0x178 - 0x17c */ - - /* New TSF host access on corerev >= 3 */ - - u32 tsf_timerlow; /* 0x180 */ - u32 tsf_timerhigh; /* 0x184 */ - u32 tsf_cfprep; /* 0x188 */ - u32 tsf_cfpstart; /* 0x18c */ - u32 tsf_cfpmaxdur32; /* 0x190 */ - u32 PAD[3]; /* 0x194 - 0x19c */ - - u32 maccontrol1; /* 0x1a0 */ - u32 machwcap1; /* 0x1a4 */ - u32 PAD[14]; /* 0x1a8 - 0x1dc */ - - /* Clock control and hardware workarounds (corerev >= 13) */ - u32 clk_ctl_st; /* 0x1e0 */ - u32 hw_war; - u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are - * moved to clk_ctl_st for corerev >= 17 - */ - u32 PAD[5]; /* 0x1ec - 0x1fc */ - - /* 0x200-0x37F dma/pio registers */ - volatile union { - fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */ - fifo64_t f64regs[6]; /* on corerev >= 11 */ - } fifo; - - /* FIFO diagnostic port access */ - dma32diag_t dmafifo; /* 0x380 - 0x38C */ - - u32 aggfifocnt; /* 0x390 */ - u32 aggfifodata; /* 0x394 */ - u32 PAD[16]; /* 0x398 - 0x3d4 */ - u16 radioregaddr; /* 0x3d8 */ - u16 radioregdata; /* 0x3da */ - - /* time delay between the change on rf disable input and radio shutdown corerev 10 */ - u32 rfdisabledly; /* 0x3DC */ - - /* PHY register access */ - u16 phyversion; /* 0x3e0 - 0x0 */ - u16 phybbconfig; /* 0x3e2 - 0x1 */ - u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */ - u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */ - u16 phyrxstatus0; /* 0x3e8 - 0x4 */ - u16 phyrxstatus1; /* 0x3ea - 0x5 */ - u16 phycrsth; /* 0x3ec - 0x6 */ - u16 phytxerror; /* 0x3ee - 0x7 */ - u16 phychannel; /* 0x3f0 - 0x8 */ - u16 PAD[1]; /* 0x3f2 - 0x9 */ - u16 phytest; /* 0x3f4 - 0xa */ - u16 phy4waddr; /* 0x3f6 - 0xb */ - u16 phy4wdatahi; /* 0x3f8 - 0xc */ - u16 phy4wdatalo; /* 0x3fa - 0xd */ - u16 phyregaddr; /* 0x3fc - 0xe */ - u16 phyregdata; /* 0x3fe - 0xf */ - - /* IHR *//* 0x400 - 0x7FE */ - - /* RXE Block */ - u16 PAD[3]; /* 0x400 - 0x406 */ - u16 rcv_fifo_ctl; /* 0x406 */ - u16 PAD; /* 0x408 - 0x40a */ - u16 rcv_frm_cnt; /* 0x40a */ - u16 PAD[4]; /* 0x40a - 0x414 */ - u16 rssi; /* 0x414 */ - u16 PAD[5]; /* 0x414 - 0x420 */ - u16 rcm_ctl; /* 0x420 */ - u16 rcm_mat_data; /* 0x422 */ - u16 rcm_mat_mask; /* 0x424 */ - u16 rcm_mat_dly; /* 0x426 */ - u16 rcm_cond_mask_l; /* 0x428 */ - u16 rcm_cond_mask_h; /* 0x42A */ - u16 rcm_cond_dly; /* 0x42C */ - u16 PAD[1]; /* 0x42E */ - u16 ext_ihr_addr; /* 0x430 */ - u16 ext_ihr_data; /* 0x432 */ - u16 rxe_phyrs_2; /* 0x434 */ - u16 rxe_phyrs_3; /* 0x436 */ - u16 phy_mode; /* 0x438 */ - u16 rcmta_ctl; /* 0x43a */ - u16 rcmta_size; /* 0x43c */ - u16 rcmta_addr0; /* 0x43e */ - u16 rcmta_addr1; /* 0x440 */ - u16 rcmta_addr2; /* 0x442 */ - u16 PAD[30]; /* 0x444 - 0x480 */ - - /* PSM Block *//* 0x480 - 0x500 */ - - u16 PAD; /* 0x480 */ - u16 psm_maccontrol_h; /* 0x482 */ - u16 psm_macintstatus_l; /* 0x484 */ - u16 psm_macintstatus_h; /* 0x486 */ - u16 psm_macintmask_l; /* 0x488 */ - u16 psm_macintmask_h; /* 0x48A */ - u16 PAD; /* 0x48C */ - u16 psm_maccommand; /* 0x48E */ - u16 psm_brc; /* 0x490 */ - u16 psm_phy_hdr_param; /* 0x492 */ - u16 psm_postcard; /* 0x494 */ - u16 psm_pcard_loc_l; /* 0x496 */ - u16 psm_pcard_loc_h; /* 0x498 */ - u16 psm_gpio_in; /* 0x49A */ - u16 psm_gpio_out; /* 0x49C */ - u16 psm_gpio_oe; /* 0x49E */ - - u16 psm_bred_0; /* 0x4A0 */ - u16 psm_bred_1; /* 0x4A2 */ - u16 psm_bred_2; /* 0x4A4 */ - u16 psm_bred_3; /* 0x4A6 */ - u16 psm_brcl_0; /* 0x4A8 */ - u16 psm_brcl_1; /* 0x4AA */ - u16 psm_brcl_2; /* 0x4AC */ - u16 psm_brcl_3; /* 0x4AE */ - u16 psm_brpo_0; /* 0x4B0 */ - u16 psm_brpo_1; /* 0x4B2 */ - u16 psm_brpo_2; /* 0x4B4 */ - u16 psm_brpo_3; /* 0x4B6 */ - u16 psm_brwk_0; /* 0x4B8 */ - u16 psm_brwk_1; /* 0x4BA */ - u16 psm_brwk_2; /* 0x4BC */ - u16 psm_brwk_3; /* 0x4BE */ - - u16 psm_base_0; /* 0x4C0 */ - u16 psm_base_1; /* 0x4C2 */ - u16 psm_base_2; /* 0x4C4 */ - u16 psm_base_3; /* 0x4C6 */ - u16 psm_base_4; /* 0x4C8 */ - u16 psm_base_5; /* 0x4CA */ - u16 psm_base_6; /* 0x4CC */ - u16 psm_pc_reg_0; /* 0x4CE */ - u16 psm_pc_reg_1; /* 0x4D0 */ - u16 psm_pc_reg_2; /* 0x4D2 */ - u16 psm_pc_reg_3; /* 0x4D4 */ - u16 PAD[0xD]; /* 0x4D6 - 0x4DE */ - u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */ - u16 PAD[0x7]; /* 0x4f2 - 0x4fE */ - - /* TXE0 Block *//* 0x500 - 0x580 */ - u16 txe_ctl; /* 0x500 */ - u16 txe_aux; /* 0x502 */ - u16 txe_ts_loc; /* 0x504 */ - u16 txe_time_out; /* 0x506 */ - u16 txe_wm_0; /* 0x508 */ - u16 txe_wm_1; /* 0x50A */ - u16 txe_phyctl; /* 0x50C */ - u16 txe_status; /* 0x50E */ - u16 txe_mmplcp0; /* 0x510 */ - u16 txe_mmplcp1; /* 0x512 */ - u16 txe_phyctl1; /* 0x514 */ - - u16 PAD[0x05]; /* 0x510 - 0x51E */ - - /* Transmit control */ - u16 xmtfifodef; /* 0x520 */ - u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */ - u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */ - u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */ - u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */ - u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */ - u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */ - - u16 PAD[0x09]; /* 0x52E - 0x53E */ - - u16 xmtfifocmd; /* 0x540 */ - u16 xmtfifoflush; /* 0x542 */ - u16 xmtfifothresh; /* 0x544 */ - u16 xmtfifordy; /* 0x546 */ - u16 xmtfifoprirdy; /* 0x548 */ - u16 xmtfiforqpri; /* 0x54A */ - u16 xmttplatetxptr; /* 0x54C */ - u16 PAD; /* 0x54E */ - u16 xmttplateptr; /* 0x550 */ - u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */ - u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */ - u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */ - u16 PAD[0x04]; /* 0x558 - 0x55E */ - u16 xmttplatedatalo; /* 0x560 */ - u16 xmttplatedatahi; /* 0x562 */ - - u16 PAD[2]; /* 0x564 - 0x566 */ - - u16 xmtsel; /* 0x568 */ - u16 xmttxcnt; /* 0x56A */ - u16 xmttxshmaddr; /* 0x56C */ - - u16 PAD[0x09]; /* 0x56E - 0x57E */ - - /* TXE1 Block */ - u16 PAD[0x40]; /* 0x580 - 0x5FE */ - - /* TSF Block */ - u16 PAD[0X02]; /* 0x600 - 0x602 */ - u16 tsf_cfpstrt_l; /* 0x604 */ - u16 tsf_cfpstrt_h; /* 0x606 */ - u16 PAD[0X05]; /* 0x608 - 0x610 */ - u16 tsf_cfppretbtt; /* 0x612 */ - u16 PAD[0XD]; /* 0x614 - 0x62C */ - u16 tsf_clk_frac_l; /* 0x62E */ - u16 tsf_clk_frac_h; /* 0x630 */ - u16 PAD[0X14]; /* 0x632 - 0x658 */ - u16 tsf_random; /* 0x65A */ - u16 PAD[0x05]; /* 0x65C - 0x664 */ - /* GPTimer 2 registers are corerev >= 3 */ - u16 tsf_gpt2_stat; /* 0x666 */ - u16 tsf_gpt2_ctr_l; /* 0x668 */ - u16 tsf_gpt2_ctr_h; /* 0x66A */ - u16 tsf_gpt2_val_l; /* 0x66C */ - u16 tsf_gpt2_val_h; /* 0x66E */ - u16 tsf_gptall_stat; /* 0x670 */ - u16 PAD[0x07]; /* 0x672 - 0x67E */ - - /* IFS Block */ - u16 ifs_sifs_rx_tx_tx; /* 0x680 */ - u16 ifs_sifs_nav_tx; /* 0x682 */ - u16 ifs_slot; /* 0x684 */ - u16 PAD; /* 0x686 */ - u16 ifs_ctl; /* 0x688 */ - u16 PAD[0x3]; /* 0x68a - 0x68F */ - u16 ifsstat; /* 0x690 */ - u16 ifsmedbusyctl; /* 0x692 */ - u16 iftxdur; /* 0x694 */ - u16 PAD[0x3]; /* 0x696 - 0x69b */ - /* EDCF support in dot11macs with corerevs >= 16 */ - u16 ifs_aifsn; /* 0x69c */ - u16 ifs_ctl1; /* 0x69e */ - - /* New slow clock registers on corerev >= 5 */ - u16 scc_ctl; /* 0x6a0 */ - u16 scc_timer_l; /* 0x6a2 */ - u16 scc_timer_h; /* 0x6a4 */ - u16 scc_frac; /* 0x6a6 */ - u16 scc_fastpwrup_dly; /* 0x6a8 */ - u16 scc_per; /* 0x6aa */ - u16 scc_per_frac; /* 0x6ac */ - u16 scc_cal_timer_l; /* 0x6ae */ - u16 scc_cal_timer_h; /* 0x6b0 */ - u16 PAD; /* 0x6b2 */ - - u16 PAD[0x26]; - - /* NAV Block */ - u16 nav_ctl; /* 0x700 */ - u16 navstat; /* 0x702 */ - u16 PAD[0x3e]; /* 0x702 - 0x77E */ - - /* WEP/PMQ Block *//* 0x780 - 0x7FE */ - u16 PAD[0x20]; /* 0x780 - 0x7BE */ - - u16 wepctl; /* 0x7C0 */ - u16 wepivloc; /* 0x7C2 */ - u16 wepivkey; /* 0x7C4 */ - u16 wepwkey; /* 0x7C6 */ - - u16 PAD[4]; /* 0x7C8 - 0x7CE */ - u16 pcmctl; /* 0X7D0 */ - u16 pcmstat; /* 0X7D2 */ - u16 PAD[6]; /* 0x7D4 - 0x7DE */ - - u16 pmqctl; /* 0x7E0 */ - u16 pmqstatus; /* 0x7E2 */ - u16 pmqpat0; /* 0x7E4 */ - u16 pmqpat1; /* 0x7E6 */ - u16 pmqpat2; /* 0x7E8 */ - - u16 pmqdat; /* 0x7EA */ - u16 pmqdator; /* 0x7EC */ - u16 pmqhst; /* 0x7EE */ - u16 pmqpath0; /* 0x7F0 */ - u16 pmqpath1; /* 0x7F2 */ - u16 pmqpath2; /* 0x7F4 */ - u16 pmqdath; /* 0x7F6 */ - - u16 PAD[0x04]; /* 0x7F8 - 0x7FE */ - - /* SHM *//* 0x800 - 0xEFE */ - u16 PAD[0x380]; /* 0x800 - 0xEFE */ - - /* SB configuration registers: 0xF00 */ - sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */ -} d11regs_t; - -#define PIHR_BASE 0x0400 /* byte address of packed IHR region */ - -/* biststatus */ -#define BT_DONE (1U << 31) /* bist done */ -#define BT_B2S (1 << 30) /* bist2 ram summary bit */ - -/* intstatus and intmask */ -#define I_PC (1 << 10) /* pci descriptor error */ -#define I_PD (1 << 11) /* pci data error */ -#define I_DE (1 << 12) /* descriptor protocol error */ -#define I_RU (1 << 13) /* receive descriptor underflow */ -#define I_RO (1 << 14) /* receive fifo overflow */ -#define I_XU (1 << 15) /* transmit fifo underflow */ -#define I_RI (1 << 16) /* receive interrupt */ -#define I_XI (1 << 24) /* transmit interrupt */ - -/* interrupt receive lazy */ -#define IRL_TO_MASK 0x00ffffff /* timeout */ -#define IRL_FC_MASK 0xff000000 /* frame count */ -#define IRL_FC_SHIFT 24 /* frame count */ - -/* maccontrol register */ -#define MCTL_GMODE (1U << 31) -#define MCTL_DISCARD_PMQ (1 << 30) -#define MCTL_WAKE (1 << 26) -#define MCTL_HPS (1 << 25) -#define MCTL_PROMISC (1 << 24) -#define MCTL_KEEPBADFCS (1 << 23) -#define MCTL_KEEPCONTROL (1 << 22) -#define MCTL_PHYLOCK (1 << 21) -#define MCTL_BCNS_PROMISC (1 << 20) -#define MCTL_LOCK_RADIO (1 << 19) -#define MCTL_AP (1 << 18) -#define MCTL_INFRA (1 << 17) -#define MCTL_BIGEND (1 << 16) -#define MCTL_GPOUT_SEL_MASK (3 << 14) -#define MCTL_GPOUT_SEL_SHIFT 14 -#define MCTL_EN_PSMDBG (1 << 13) -#define MCTL_IHR_EN (1 << 10) -#define MCTL_SHM_UPPER (1 << 9) -#define MCTL_SHM_EN (1 << 8) -#define MCTL_PSM_JMP_0 (1 << 2) -#define MCTL_PSM_RUN (1 << 1) -#define MCTL_EN_MAC (1 << 0) - -/* maccommand register */ -#define MCMD_BCN0VLD (1 << 0) -#define MCMD_BCN1VLD (1 << 1) -#define MCMD_DIRFRMQVAL (1 << 2) -#define MCMD_CCA (1 << 3) -#define MCMD_BG_NOISE (1 << 4) -#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */ -#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */ - -/* macintstatus/macintmask */ -#define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */ -#define MI_BCNTPL (1 << 1) /* beacon template available */ -#define MI_TBTT (1 << 2) /* TBTT indication */ -#define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */ -#define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */ -#define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */ -#define MI_PMQ (1 << 6) /* PMQ entries available */ -#define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */ -#define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */ -#define MI_MACTXERR (1 << 9) /* MAC level Tx error */ -#define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */ -#define MI_PHYTXERR (1 << 11) /* PHY Tx error */ -#define MI_PME (1 << 12) /* Power Management Event */ -#define MI_GP0 (1 << 13) /* General-purpose timer0 */ -#define MI_GP1 (1 << 14) /* General-purpose timer1 */ -#define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */ -#define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */ -#define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */ -#define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */ -#define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */ -#define MI_PRQ (1 << 20) /* Probe response queue needs attention */ -#define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */ -#define MI_RESERVED3 (1 << 22) -#define MI_RESERVED2 (1 << 23) -#define MI_RESERVED1 (1 << 25) -#define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input - * (corerev >= 10) - */ -#define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */ -#define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */ -#define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */ - -/* Mac capabilities registers */ -/* machwcap */ -#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */ - -/* pmqhost data */ -#define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */ -#define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */ -#define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */ -#define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */ -#define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */ -#define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */ -#define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */ -#define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */ -#define PMQH_OFLO 0x00000004 /* pmq overflow indication */ -#define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */ - -/* phydebug (corerev >= 3) */ -#define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */ -#define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */ -#define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */ -#define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */ -#define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */ -#define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */ -#define PDBG_RXFRG (1 << 6) /* rx start not asserted */ -#define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */ -#define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */ - -/* objaddr register */ -#define OBJADDR_SEL_MASK 0x000F0000 -#define OBJADDR_UCM_SEL 0x00000000 -#define OBJADDR_SHM_SEL 0x00010000 -#define OBJADDR_SCR_SEL 0x00020000 -#define OBJADDR_IHR_SEL 0x00030000 -#define OBJADDR_RCMTA_SEL 0x00040000 -#define OBJADDR_SRCHM_SEL 0x00060000 -#define OBJADDR_WINC 0x01000000 -#define OBJADDR_RINC 0x02000000 -#define OBJADDR_AUTO_INC 0x03000000 - -#define WEP_PCMADDR 0x07d4 -#define WEP_PCMDATA 0x07d6 - -/* frmtxstatus */ -#define TXS_V (1 << 0) /* valid bit */ -#define TXS_STATUS_MASK 0xffff -/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */ -#define TXS_COMPAT_MASK 0x3 -#define TXS_COMPAT_SHIFT 1 -#define TXS_FID_MASK 0xffff0000 -#define TXS_FID_SHIFT 16 - -/* frmtxstatus2 */ -#define TXS_SEQ_MASK 0xffff -#define TXS_PTX_MASK 0xff0000 -#define TXS_PTX_SHIFT 16 -#define TXS_MU_MASK 0x01000000 -#define TXS_MU_SHIFT 24 - -/* clk_ctl_st, corerev >= 17 */ -#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */ -#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */ -#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */ -#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */ - -/* HT Cloclk Ctrl and Clock Avail for 4313 */ -#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */ -#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */ - -/* d11_pwrctl, corerev16 only */ -#define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */ -#define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */ - -/* tsf_cfprep register */ -#define CFPREP_CBI_MASK 0xffffffc0 -#define CFPREP_CBI_SHIFT 6 -#define CFPREP_CFPP 0x00000001 - -/* tx fifo sizes for corerev >= 9 */ -/* tx fifo sizes values are in terms of 256 byte blocks */ -#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */ -#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */ -#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */ - -#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */ -#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */ -#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */ -#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */ - -/* phy versions, PhyVersion:Revision field */ -#define PV_AV_MASK 0xf000 /* analog block version */ -#define PV_AV_SHIFT 12 /* analog block version bitfield offset */ -#define PV_PT_MASK 0x0f00 /* phy type */ -#define PV_PT_SHIFT 8 /* phy type bitfield offset */ -#define PV_PV_MASK 0x000f /* phy version */ -#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT) - -/* phy types, PhyVersion:PhyType field */ -#define PHY_TYPE_N 4 /* N-Phy value */ -#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */ -#define PHY_TYPE_LCN 8 /* LCN-Phy value */ -#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */ -#define PHY_TYPE_NULL 0xf /* Invalid Phy value */ - -/* analog types, PhyVersion:AnalogType field */ -#define ANA_11N_013 5 - -/* 802.11a PLCP header def */ -typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; -struct ofdm_phy_hdr { - u8 rlpt[3]; /* rate, length, parity, tail */ - u16 service; - u8 pad; -} __attribute__((packed)); - -#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) -#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) -#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff) -#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) -#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) - -/* rate encoded per 802.11a-1999 sec 17.3.4.1 */ -#define D11A_PHY_HDR_SRATE(phdr, rate) \ - ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf)) -/* set reserved field to zero */ -#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) -/* length is number of octets in PSDU */ -#define D11A_PHY_HDR_SLENGTH(phdr, length) \ - (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \ - (((length) & 0x0fff) << 5)) -/* set the tail to all zeros */ -#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) - -#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */ -#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */ - -#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */ - -#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */ -#define D11A_PHY_PRE_TIME (16) -#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME) - -/* 802.11b PLCP header def */ -typedef struct cck_phy_hdr cck_phy_hdr_t; -struct cck_phy_hdr { - u8 signal; - u8 service; - u16 length; - u16 crc; -} __attribute__((packed)); - -#define D11B_PHY_HDR_LEN 6 - -#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */ - -#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3) -#define D11B_PHY_LPRE_TIME (144) -#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME) - -#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1) -#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1) -#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME) - -#define D11B_PLCP_SIGNAL_LOCKED (1 << 2) -#define D11B_PLCP_SIGNAL_LE (1 << 7) - -#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */ -#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */ -#define MIMO_PLCP_AMPDU 0x08 /* ampdu */ - -#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8)) -#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8)) -#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \ - do { \ - plcp[1] = len & 0xff; \ - plcp[2] = ((len >> 8) & 0xff); \ - } while (0); - -#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU) -#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU) -#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU) - -/* The dot11a PLCP header is 5 bytes. To simplify the software (so that we - * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has - * padding added in the ucode. - */ -#define D11_PHY_HDR_LEN 6 - -/* TX DMA buffer header */ -typedef struct d11txh d11txh_t; -struct d11txh { - u16 MacTxControlLow; /* 0x0 */ - u16 MacTxControlHigh; /* 0x1 */ - u16 MacFrameControl; /* 0x2 */ - u16 TxFesTimeNormal; /* 0x3 */ - u16 PhyTxControlWord; /* 0x4 */ - u16 PhyTxControlWord_1; /* 0x5 */ - u16 PhyTxControlWord_1_Fbr; /* 0x6 */ - u16 PhyTxControlWord_1_Rts; /* 0x7 */ - u16 PhyTxControlWord_1_FbrRts; /* 0x8 */ - u16 MainRates; /* 0x9 */ - u16 XtraFrameTypes; /* 0xa */ - u8 IV[16]; /* 0x0b - 0x12 */ - u8 TxFrameRA[6]; /* 0x13 - 0x15 */ - u16 TxFesTimeFallback; /* 0x16 */ - u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ - u16 RTSDurFallback; /* 0x1a */ - u8 FragPLCPFallback[6]; /* 0x1b - 1d */ - u16 FragDurFallback; /* 0x1e */ - u16 MModeLen; /* 0x1f */ - u16 MModeFbrLen; /* 0x20 */ - u16 TstampLow; /* 0x21 */ - u16 TstampHigh; /* 0x22 */ - u16 ABI_MimoAntSel; /* 0x23 */ - u16 PreloadSize; /* 0x24 */ - u16 AmpduSeqCtl; /* 0x25 */ - u16 TxFrameID; /* 0x26 */ - u16 TxStatus; /* 0x27 */ - u16 MaxNMpdus; /* 0x28 corerev >=16 */ - u16 MaxABytes_MRT; /* 0x29 corerev >=16 */ - u16 MaxABytes_FBR; /* 0x2a corerev >=16 */ - u16 MinMBytes; /* 0x2b corerev >=16 */ - u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ - struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */ - u16 PAD; /* 0x37 */ -} __attribute__((packed)); - -#define D11_TXH_LEN 112 /* bytes */ - -/* Frame Types */ -#define FT_CCK 0 -#define FT_OFDM 1 -#define FT_HT 2 -#define FT_N 3 - -/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */ -#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */ -#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */ -#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */ -#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */ -#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */ - -/* MacTxControlLow */ -#define TXC_AMIC 0x8000 -#define TXC_SENDCTS 0x0800 -#define TXC_AMPDU_MASK 0x0600 -#define TXC_BW_40 0x0100 -#define TXC_FREQBAND_5G 0x0080 -#define TXC_DFCS 0x0040 -#define TXC_IGNOREPMQ 0x0020 -#define TXC_HWSEQ 0x0010 -#define TXC_STARTMSDU 0x0008 -#define TXC_SENDRTS 0x0004 -#define TXC_LONGFRAME 0x0002 -#define TXC_IMMEDACK 0x0001 - -/* MacTxControlHigh */ -#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */ -#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */ -#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type - * 1 = SHORT for OFDM/GF for MIMO - * 0 = LONG for CCK/MM for MIMO - */ -/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */ -#define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */ -#define TXC_SECKEY_MASK 0x0FF0 -#define TXC_SECKEY_SHIFT 4 -#define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ -#define TXC_SECTYPE_MASK 0x0007 -#define TXC_SECTYPE_SHIFT 0 - -/* Null delimiter for Fallback rate */ -#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */ - -/* PhyTxControl for Mimophy */ -#define PHY_TXC_PWR_MASK 0xFC00 -#define PHY_TXC_PWR_SHIFT 10 -#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */ -#define PHY_TXC_ANT_SHIFT 6 -#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */ -#define PHY_TXC_LCNPHY_ANT_LAST 0x0000 -#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */ -#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */ -#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */ -#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */ -#define PHY_TXC_SHORT_HDR 0x0010 - -#define PHY_TXC_OLD_ANT_0 0x0000 -#define PHY_TXC_OLD_ANT_1 0x0100 -#define PHY_TXC_OLD_ANT_LAST 0x0300 - -/* PhyTxControl_1 for Mimophy */ -#define PHY_TXC1_BW_MASK 0x0007 -#define PHY_TXC1_BW_10MHZ 0 -#define PHY_TXC1_BW_10MHZ_UP 1 -#define PHY_TXC1_BW_20MHZ 2 -#define PHY_TXC1_BW_20MHZ_UP 3 -#define PHY_TXC1_BW_40MHZ 4 -#define PHY_TXC1_BW_40MHZ_DUP 5 -#define PHY_TXC1_MODE_SHIFT 3 -#define PHY_TXC1_MODE_MASK 0x0038 -#define PHY_TXC1_MODE_SISO 0 -#define PHY_TXC1_MODE_CDD 1 -#define PHY_TXC1_MODE_STBC 2 -#define PHY_TXC1_MODE_SDM 3 - -/* PhyTxControl for HTphy that are different from Mimophy */ -#define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */ - -/* XtraFrameTypes */ -#define XFTS_RTS_FT_SHIFT 2 -#define XFTS_FBRRTS_FT_SHIFT 4 -#define XFTS_CHANNEL_SHIFT 8 - -/* Antenna diversity bit in ant_wr_settle */ -#define PHY_AWS_ANTDIV 0x2000 - -/* IFS ctl */ -#define IFS_USEEDCF (1 << 2) - -/* IFS ctl1 */ -#define IFS_CTL1_EDCRS (1 << 3) -#define IFS_CTL1_EDCRS_20L (1 << 4) -#define IFS_CTL1_EDCRS_40 (1 << 5) - -/* ABI_MimoAntSel */ -#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00 -#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8 -#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0 -#define ABI_MAS_FBR_ANT_PTN_SHIFT 4 -#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f - -/* tx status packet */ -typedef struct tx_status tx_status_t; -struct tx_status { - u16 framelen; - u16 PAD; - u16 frameid; - u16 status; - u16 lasttxtime; - u16 sequence; - u16 phyerr; - u16 ackphyrxsh; -} __attribute__((packed)); - -#define TXSTATUS_LEN 16 - -/* status field bit definitions */ -#define TX_STATUS_FRM_RTX_MASK 0xF000 -#define TX_STATUS_FRM_RTX_SHIFT 12 -#define TX_STATUS_RTS_RTX_MASK 0x0F00 -#define TX_STATUS_RTS_RTX_SHIFT 8 -#define TX_STATUS_MASK 0x00FE -#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */ -#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */ -#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */ -#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */ -#define TX_STATUS_SUPR_SHIFT 2 -#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */ -#define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */ -#define TX_STATUS_NO_ACK 0 - -/* suppress status reason codes */ -#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */ -#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */ -#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */ -#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */ -#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */ -#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */ -#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */ - -/* Unexpected tx status for rate update */ -#define TX_STATUS_UNEXP(status) \ - ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \ - TX_STATUS_UNEXP_AMPDU(status)) - -/* Unexpected tx status for A-MPDU rate update */ -#define TX_STATUS_UNEXP_AMPDU(status) \ - ((((status) & TX_STATUS_SUPR_MASK) != 0) && \ - (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME)) - -#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */ -#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */ -#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */ -#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */ - -/* RXE (Receive Engine) */ - -/* RCM_CTL */ -#define RCM_INC_MASK_H 0x0080 -#define RCM_INC_MASK_L 0x0040 -#define RCM_INC_DATA 0x0020 -#define RCM_INDEX_MASK 0x001F -#define RCM_SIZE 15 - -#define RCM_MAC_OFFSET 0 /* current MAC address */ -#define RCM_BSSID_OFFSET 3 /* current BSSID address */ -#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */ -#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */ -#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */ - -#define RCM_WEP_TA0_OFFSET 16 -#define RCM_WEP_TA1_OFFSET 19 -#define RCM_WEP_TA2_OFFSET 22 -#define RCM_WEP_TA3_OFFSET 25 - -/* PSM Block */ - -/* psm_phy_hdr_param bits */ -#define MAC_PHY_RESET 1 -#define MAC_PHY_CLOCK_EN 2 -#define MAC_PHY_FORCE_CLK 4 - -/* WEP Block */ - -/* WEP_WKEY */ -#define WKEY_START (1 << 8) -#define WKEY_SEL_MASK 0x1F - -/* WEP data formats */ - -/* the number of RCMTA entries */ -#define RCMTA_SIZE 50 - -#define M_ADDR_BMP_BLK (0x37e * 2) -#define M_ADDR_BMP_BLK_SZ 12 - -#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */ -#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */ -#define ADDR_BMP_BSSID (1 << 2) /* BSSID */ -#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */ -#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */ -#define ADDR_BMP_RESERVED1 (1 << 5) -#define ADDR_BMP_RESERVED2 (1 << 6) -#define ADDR_BMP_RESERVED3 (1 << 7) -#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */ -#define ADDR_BMP_BSS_IDX_SHIFT 8 - -#define WSEC_MAX_RCMTA_KEYS 54 - -/* max keys in M_TKMICKEYS_BLK */ -#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */ - -/* max RXE match registers */ -#define WSEC_MAX_RXE_KEYS 4 - -/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */ -/* SKL (Security Key Lookup) */ -#define SKL_ALGO_MASK 0x0007 -#define SKL_ALGO_SHIFT 0 -#define SKL_KEYID_MASK 0x0008 -#define SKL_KEYID_SHIFT 3 -#define SKL_INDEX_MASK 0x03F0 -#define SKL_INDEX_SHIFT 4 -#define SKL_GRP_ALGO_MASK 0x1c00 -#define SKL_GRP_ALGO_SHIFT 10 - -/* additional bits defined for IBSS group key support */ -#define SKL_IBSS_INDEX_MASK 0x01F0 -#define SKL_IBSS_INDEX_SHIFT 4 -#define SKL_IBSS_KEYID1_MASK 0x0600 -#define SKL_IBSS_KEYID1_SHIFT 9 -#define SKL_IBSS_KEYID2_MASK 0x1800 -#define SKL_IBSS_KEYID2_SHIFT 11 -#define SKL_IBSS_KEYALGO_MASK 0xE000 -#define SKL_IBSS_KEYALGO_SHIFT 13 - -#define WSEC_MODE_OFF 0 -#define WSEC_MODE_HW 1 -#define WSEC_MODE_SW 2 - -#define WSEC_ALGO_OFF 0 -#define WSEC_ALGO_WEP1 1 -#define WSEC_ALGO_TKIP 2 -#define WSEC_ALGO_AES 3 -#define WSEC_ALGO_WEP128 4 -#define WSEC_ALGO_AES_LEGACY 5 -#define WSEC_ALGO_NALG 6 - -#define AES_MODE_NONE 0 -#define AES_MODE_CCM 1 - -/* WEP_CTL (Rev 0) */ -#define WECR0_KEYREG_SHIFT 0 -#define WECR0_KEYREG_MASK 0x7 -#define WECR0_DECRYPT (1 << 3) -#define WECR0_IVINLINE (1 << 4) -#define WECR0_WEPALG_SHIFT 5 -#define WECR0_WEPALG_MASK (0x7 << 5) -#define WECR0_WKEYSEL_SHIFT 8 -#define WECR0_WKEYSEL_MASK (0x7 << 8) -#define WECR0_WKEYSTART (1 << 11) -#define WECR0_WEPINIT (1 << 14) -#define WECR0_ICVERR (1 << 15) - -/* Frame template map byte offsets */ -#define T_ACTS_TPL_BASE (0) -#define T_NULL_TPL_BASE (0xc * 2) -#define T_QNULL_TPL_BASE (0x1c * 2) -#define T_RR_TPL_BASE (0x2c * 2) -#define T_BCN0_TPL_BASE (0x34 * 2) -#define T_PRS_TPL_BASE (0x134 * 2) -#define T_BCN1_TPL_BASE (0x234 * 2) -#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT)) - -#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */ - -#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */ - -/* Shared Mem byte offsets */ - -/* Location where the ucode expects the corerev */ -#define M_MACHW_VER (0x00b * 2) - -/* Location where the ucode expects the MAC capabilities */ -#define M_MACHW_CAP_L (0x060 * 2) -#define M_MACHW_CAP_H (0x061 * 2) - -/* WME shared memory */ -#define M_EDCF_STATUS_OFF (0x007 * 2) -#define M_TXF_CUR_INDEX (0x018 * 2) -#define M_EDCF_QINFO (0x120 * 2) - -/* PS-mode related parameters */ -#define M_DOT11_SLOT (0x008 * 2) -#define M_DOT11_DTIMPERIOD (0x009 * 2) -#define M_NOSLPZNATDTIM (0x026 * 2) - -/* Beacon-related parameters */ -#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */ -#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */ -#define M_BCN_TXTSF_OFFSET (0x00e * 2) -#define M_TIMBPOS_INBEACON (0x00f * 2) -#define M_SFRMTXCNTFBRTHSD (0x022 * 2) -#define M_LFRMTXCNTFBRTHSD (0x023 * 2) -#define M_BCN_PCTLWD (0x02a * 2) -#define M_BCN_LI (0x05b * 2) /* beacon listen interval */ - -/* MAX Rx Frame len */ -#define M_MAXRXFRM_LEN (0x010 * 2) - -/* ACK/CTS related params */ -#define M_RSP_PCTLWD (0x011 * 2) - -/* Hardware Power Control */ -#define M_TXPWR_N (0x012 * 2) -#define M_TXPWR_TARGET (0x013 * 2) -#define M_TXPWR_MAX (0x014 * 2) -#define M_TXPWR_CUR (0x019 * 2) - -/* Rx-related parameters */ -#define M_RX_PAD_DATA_OFFSET (0x01a * 2) - -/* WEP Shared mem data */ -#define M_SEC_DEFIVLOC (0x01e * 2) -#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2) -#define M_PHYVER (0x028 * 2) -#define M_PHYTYPE (0x029 * 2) -#define M_SECRXKEYS_PTR (0x02b * 2) -#define M_TKMICKEYS_PTR (0x059 * 2) -#define M_SECKINDXALGO_BLK (0x2ea * 2) -#define M_SECKINDXALGO_BLK_SZ 54 -#define M_SECPSMRXTAMCH_BLK (0x2fa * 2) -#define M_TKIP_TSC_TTAK (0x18c * 2) -#define D11_MAX_KEY_SIZE 16 - -#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */ - -/* Probe response related parameters */ -#define M_SSIDLEN (0x024 * 2) -#define M_PRB_RESP_FRM_LEN (0x025 * 2) -#define M_PRS_MAXTIME (0x03a * 2) -#define M_SSID (0xb0 * 2) -#define M_CTXPRS_BLK (0xc0 * 2) -#define C_CTX_PCTLWD_POS (0x4 * 2) - -/* Delta between OFDM and CCK power in CCK power boost mode */ -#define M_OFDM_OFFSET (0x027 * 2) - -/* TSSI for last 4 11b/g CCK packets transmitted */ -#define M_B_TSSI_0 (0x02c * 2) -#define M_B_TSSI_1 (0x02d * 2) - -/* Host flags to turn on ucode options */ -#define M_HOST_FLAGS1 (0x02f * 2) -#define M_HOST_FLAGS2 (0x030 * 2) -#define M_HOST_FLAGS3 (0x031 * 2) -#define M_HOST_FLAGS4 (0x03c * 2) -#define M_HOST_FLAGS5 (0x06a * 2) -#define M_HOST_FLAGS_SZ 16 - -#define M_RADAR_REG (0x033 * 2) - -/* TSSI for last 4 11a OFDM packets transmitted */ -#define M_A_TSSI_0 (0x034 * 2) -#define M_A_TSSI_1 (0x035 * 2) - -/* noise interference measurement */ -#define M_NOISE_IF_COUNT (0x034 * 2) -#define M_NOISE_IF_TIMEOUT (0x035 * 2) - -#define M_RF_RX_SP_REG1 (0x036 * 2) - -/* TSSI for last 4 11g OFDM packets transmitted */ -#define M_G_TSSI_0 (0x038 * 2) -#define M_G_TSSI_1 (0x039 * 2) - -/* Background noise measure */ -#define M_JSSI_0 (0x44 * 2) -#define M_JSSI_1 (0x45 * 2) -#define M_JSSI_AUX (0x46 * 2) - -#define M_CUR_2050_RADIOCODE (0x47 * 2) - -/* TX fifo sizes */ -#define M_FIFOSIZE0 (0x4c * 2) -#define M_FIFOSIZE1 (0x4d * 2) -#define M_FIFOSIZE2 (0x4e * 2) -#define M_FIFOSIZE3 (0x4f * 2) -#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */ - -/* Current channel number plus upper bits */ -#define M_CURCHANNEL (0x50 * 2) -#define D11_CURCHANNEL_5G 0x0100; -#define D11_CURCHANNEL_40 0x0200; -#define D11_CURCHANNEL_MAX 0x00FF; - -/* last posted frameid on the bcmc fifo */ -#define M_BCMC_FID (0x54 * 2) -#define INVALIDFID 0xffff - -/* extended beacon phyctl bytes for 11N */ -#define M_BCN_PCTL1WD (0x058 * 2) - -/* idle busy ratio to duty_cycle requirement */ -#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2) -#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2) - -/* CW RSSI for LCNPHY */ -#define M_LCN_RSSI_0 0x1332 -#define M_LCN_RSSI_1 0x1338 -#define M_LCN_RSSI_2 0x133e -#define M_LCN_RSSI_3 0x1344 - -/* SNR for LCNPHY */ -#define M_LCN_SNR_A_0 0x1334 -#define M_LCN_SNR_B_0 0x1336 - -#define M_LCN_SNR_A_1 0x133a -#define M_LCN_SNR_B_1 0x133c - -#define M_LCN_SNR_A_2 0x1340 -#define M_LCN_SNR_B_2 0x1342 - -#define M_LCN_SNR_A_3 0x1346 -#define M_LCN_SNR_B_3 0x1348 - -#define M_LCN_LAST_RESET (81*2) -#define M_LCN_LAST_LOC (63*2) -#define M_LCNPHY_RESET_STATUS (4902) -#define M_LCNPHY_DSC_TIME (0x98d*2) -#define M_LCNPHY_RESET_CNT_DSC (0x98b*2) -#define M_LCNPHY_RESET_CNT (0x98c*2) - -/* Rate table offsets */ -#define M_RT_DIRMAP_A (0xe0 * 2) -#define M_RT_BBRSMAP_A (0xf0 * 2) -#define M_RT_DIRMAP_B (0x100 * 2) -#define M_RT_BBRSMAP_B (0x110 * 2) - -/* Rate table entry offsets */ -#define M_RT_PRS_PLCP_POS 10 -#define M_RT_PRS_DUR_POS 16 -#define M_RT_OFDM_PCTL1_POS 18 - -#define M_20IN40_IQ (0x380 * 2) - -/* SHM locations where ucode stores the current power index */ -#define M_CURR_IDX1 (0x384 * 2) -#define M_CURR_IDX2 (0x387 * 2) - -#define M_BSCALE_ANT0 (0x5e * 2) -#define M_BSCALE_ANT1 (0x5f * 2) - -/* Antenna Diversity Testing */ -#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2) -#define M_ANTSEL_CLKDIV (0x61 * 2) -#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2) - -#define M_MIMO_MAXSYM (0x5d * 2) -#define MIMO_MAXSYM_DEF 0x8000 /* 32k */ -#define MIMO_MAXSYM_MAX 0xffff /* 64k */ - -#define M_WATCHDOG_8TU (0x1e * 2) -#define WATCHDOG_8TU_DEF 5 -#define WATCHDOG_8TU_MAX 10 - -/* Manufacturing Test Variables */ -#define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */ -#define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */ -#define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */ -#define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */ - -/* Index variation in vbat ripple */ -#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */ -#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */ - -/* M_PKTENG_CTRL bit definitions */ -#define M_PKTENG_MODE_TX 0x0001 -#define M_PKTENG_MODE_TX_RIFS 0x0004 -#define M_PKTENG_MODE_TX_CTS 0x0008 -#define M_PKTENG_MODE_RX 0x0002 -#define M_PKTENG_MODE_RX_WITH_ACK 0x0402 -#define M_PKTENG_MODE_MASK 0x0003 -#define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */ - -/* Sample Collect parameters (bitmap and type) */ -#define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */ -#define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */ - -#define ANTSEL_CLKDIV_4MHZ 6 -#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */ -#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */ -#define MIMO_ANTSEL_WAIT 50 /* 50us wait */ -#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */ - -typedef struct shm_acparams shm_acparams_t; -struct shm_acparams { - u16 txop; - u16 cwmin; - u16 cwmax; - u16 cwcur; - u16 aifs; - u16 bslots; - u16 reggap; - u16 status; - u16 rsvd[8]; -} __attribute__((packed)); -#define M_EDCF_QLEN (16 * 2) - -#define WME_STATUS_NEWAC (1 << 8) - -/* M_HOST_FLAGS */ -#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */ -#define MHF1 0 /* Hostflag 1 index */ -#define MHF2 1 /* Hostflag 2 index */ -#define MHF3 2 /* Hostflag 3 index */ -#define MHF4 3 /* Hostflag 4 index */ -#define MHF5 4 /* Hostflag 5 index */ - -/* Flags in M_HOST_FLAGS */ -#define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */ -#define MHF1_EDCF 0x0100 /* Enable EDCF access control */ -#define MHF1_IQSWAP_WAR 0x0200 -#define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */ - -/* Flags in M_HOST_FLAGS2 */ -#define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */ -#define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */ -#define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */ -#define MHF2_NPHY40MHZ_WAR 0x0800 - -/* Flags in M_HOST_FLAGS3 */ -#define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */ -#define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */ -#define MHF3_RESERVED1 0x0004 -#define MHF3_RESERVED2 0x0008 -#define MHF3_NPHY_MLADV_WAR 0x0010 - -/* Flags in M_HOST_FLAGS4 */ -#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */ -#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */ - -/* Flags in M_HOST_FLAGS5 */ -#define MHF5_4313_GPIOCTRL 0x0001 -#define MHF5_RESERVED1 0x0002 -#define MHF5_RESERVED2 0x0004 -/* Radio power setting for ucode */ -#define M_RADIO_PWR (0x32 * 2) - -/* phy noise recorded by ucode right after tx */ -#define M_PHY_NOISE (0x037 * 2) -#define PHY_NOISE_MASK 0x00ff - -/* Receive Frame Data Header for 802.11b DCF-only frames */ -typedef struct d11rxhdr d11rxhdr_t; -struct d11rxhdr { - u16 RxFrameSize; /* Actual byte length of the frame data received */ - u16 PAD; - u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */ - u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */ - u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */ - u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */ - u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */ - u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */ - u16 RxStatus1; /* MAC Rx Status */ - u16 RxStatus2; /* extended MAC Rx status */ - u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ - u16 RxChan; /* gain code, channel radio code, and phy type */ -} __attribute__((packed)); - -#define RXHDR_LEN 24 /* sizeof d11rxhdr_t */ -#define FRAMELEN(h) ((h)->RxFrameSize) - -typedef struct wlc_d11rxhdr wlc_d11rxhdr_t; -struct wlc_d11rxhdr { - d11rxhdr_t rxhdr; - u32 tsf_l; /* TSF_L reading */ - s8 rssi; /* computed instanteneous rssi in BMAC */ - s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ - s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ - s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */ - s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */ -} __attribute__((packed)); - -/* PhyRxStatus_0: */ -#define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */ -#define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */ -#define PRXS0_CLIP_SHIFT 2 -#define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */ -#define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */ -#define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */ -#define PRXS0_SHORTH 0x0080 /* Short Preamble */ -#define PRXS0_PLCPFV 0x0100 /* PLCP violation */ -#define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */ -#define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */ -#define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */ -#define PRXS0_ANTSEL_SHIFT 0x12 - -/* subfield PRXS0_FT_MASK */ -#define PRXS0_CCK 0x0000 -#define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */ -#define PRXS0_PREN 0x0002 -#define PRXS0_STDN 0x0003 - -/* subfield PRXS0_ANTSEL_MASK */ -#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */ -#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */ -#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */ -#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */ - -/* PhyRxStatus_1: */ -#define PRXS1_JSSI_MASK 0x00FF -#define PRXS1_JSSI_SHIFT 0 -#define PRXS1_SQ_MASK 0xFF00 -#define PRXS1_SQ_SHIFT 8 - -/* nphy PhyRxStatus_1: */ -#define PRXS1_nphy_PWR0_MASK 0x00FF -#define PRXS1_nphy_PWR1_MASK 0xFF00 - -/* HTPHY Rx Status defines */ -/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */ -#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */ -#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */ -#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */ - -/* htphy PhyRxStatus_1: */ -#define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */ -#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */ -#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */ - -/* htphy PhyRxStatus_2: */ -#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */ -#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */ -#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */ - -/* htphy PhyRxStatus_3: */ -#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */ -#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */ - -/* htphy PhyRxStatus_4: */ -#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */ -#define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */ - -/* htphy PhyRxStatus_5: */ -#define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */ -#define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */ - -#define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \ - (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8)) -/* Get Rx power on core 0 */ -#define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8) -/* Get Rx power on core 1 */ -#define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1) -/* Get Rx power on core 2 */ -#define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8) - -/* ucode RxStatus1: */ -#define RXS_BCNSENT 0x8000 -#define RXS_SECKINDX_MASK 0x07e0 -#define RXS_SECKINDX_SHIFT 5 -#define RXS_DECERR (1 << 4) -#define RXS_DECATMPT (1 << 3) -#define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */ -#define RXS_RESPFRAMETX (1 << 1) -#define RXS_FCSERR (1 << 0) - -/* ucode RxStatus2: */ -#define RXS_AMSDU_MASK 1 -#define RXS_AGGTYPE_MASK 0x6 -#define RXS_AGGTYPE_SHIFT 1 -#define RXS_PHYRXST_VALID (1 << 8) -#define RXS_RXANT_MASK 0x3 -#define RXS_RXANT_SHIFT 12 - -/* RxChan */ -#define RXS_CHAN_40 0x1000 -#define RXS_CHAN_5G 0x0800 -#define RXS_CHAN_ID_MASK 0x07f8 -#define RXS_CHAN_ID_SHIFT 3 -#define RXS_CHAN_PHYTYPE_MASK 0x0007 -#define RXS_CHAN_PHYTYPE_SHIFT 0 - -/* Index of attenuations used during ucode power control. */ -#define M_PWRIND_BLKS (0x184 * 2) -#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0) -#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2) -#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4) -#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6) -/* M_PWRIND_MAP(core) macro */ -#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1)) - -/* PSM SHM variable offsets */ -#define M_PSM_SOFT_REGS 0x0 -#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0) -#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2) -#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */ -#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */ - -#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */ -#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */ -#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */ -#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */ -#define M_PRETBTT (0x4b * 2) - -#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */ -#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2)) -#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2)) -#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2)) - -/* PKTENG Rx Stats Block */ -#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2)) - -/* ucode debug status codes */ -#define DBGST_INACTIVE 0 /* not valid really */ -#define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */ -#define DBGST_ACTIVE 2 /* "normal" state */ -#define DBGST_SUSPENDED 3 /* suspended */ -#define DBGST_ASLEEP 4 /* asleep (PS mode) */ - -/* Scratch Reg defs */ -typedef enum { - S_RSV0 = 0, - S_RSV1, - S_RSV2, - - /* scratch registers for Dot11-contants */ - S_DOT11_CWMIN, /* CW-minimum 0x03 */ - S_DOT11_CWMAX, /* CW-maximum 0x04 */ - S_DOT11_CWCUR, /* CW-current 0x05 */ - S_DOT11_SRC_LMT, /* short retry count limit 0x06 */ - S_DOT11_LRC_LMT, /* long retry count limit 0x07 */ - S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */ - - /* Tx-side scratch registers */ - S_SEQ_NUM, /* hardware sequence number reg 0x09 */ - S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */ - S_FRMRETX_CNT, /* frame retx count 0x0B */ - S_SSRC, /* Station short retry count 0x0C */ - S_SLRC, /* Station long retry count 0x0D */ - S_EXP_RSP, /* Expected response frame 0x0E */ - S_OLD_BREM, /* Remaining backoff ctr 0x0F */ - S_OLD_CWWIN, /* saved-off CW-cur 0x10 */ - S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */ - S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */ - - /* Rx-side scratch registers */ - S_RXTST, /* Type and subtype in Rxframe 0x13 */ - - /* Global state register */ - S_STREG, /* state storage actual bit maps below 0x14 */ - - S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */ - S_TXPWR_ITER, /* Tx power control: iteration 0x16 */ - S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */ - S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */ - - S_KEYINDX, /* 0x19 */ - S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */ - - /* Receive TSF time stored in SCR */ - S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */ - S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */ - S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */ - S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */ - S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */ - S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */ - - /* Scratch pad regs used in microcode as temp storage */ - S_TMP0, /* stmp0 0x21 */ - S_TMP1, /* stmp1 0x22 */ - S_TMP2, /* stmp2 0x23 */ - S_TMP3, /* stmp3 0x24 */ - S_TMP4, /* stmp4 0x25 */ - S_TMP5, /* stmp5 0x26 */ - S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */ - S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */ - S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */ - S_RXTP, /* rx frame type 0x2A */ - S_STREG2, /* extra state storage 0x2B */ - S_STREG3, /* even more extra state storage 0x2C */ - S_STREG4, /* ... 0x2D */ - S_STREG5, /* remember to initialize it to zero 0x2E */ - - S_ADJPWR_IDX, - S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */ - S_REVID4, /* 0x33 */ - S_INDX, /* 0x34 */ - S_ADDR0, /* 0x35 */ - S_ADDR1, /* 0x36 */ - S_ADDR2, /* 0x37 */ - S_ADDR3, /* 0x38 */ - S_ADDR4, /* 0x39 */ - S_ADDR5, /* 0x3A */ - S_TMP6, /* 0x3B */ - S_KEYINDX_BU, /* Backup for Key index 0x3C */ - S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */ - S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */ - S_STREG6, /* 0x3F */ -} ePsmScratchPadRegDefinitions; - -#define S_BEACON_INDX S_OLD_BREM -#define S_PRS_INDX S_OLD_CWWIN -#define S_PHYTYPE S_SSRC -#define S_PHYVER S_SLRC - -/* IHR SLOW_CTRL values */ -#define SLOW_CTRL_PDE (1 << 0) -#define SLOW_CTRL_FD (1 << 8) - -/* ucode mac statistic counters in shared memory */ -typedef struct macstat { - u16 txallfrm; /* 0x80 */ - u16 txrtsfrm; /* 0x82 */ - u16 txctsfrm; /* 0x84 */ - u16 txackfrm; /* 0x86 */ - u16 txdnlfrm; /* 0x88 */ - u16 txbcnfrm; /* 0x8a */ - u16 txfunfl[8]; /* 0x8c - 0x9b */ - u16 txtplunfl; /* 0x9c */ - u16 txphyerr; /* 0x9e */ - u16 pktengrxducast; /* 0xa0 */ - u16 pktengrxdmcast; /* 0xa2 */ - u16 rxfrmtoolong; /* 0xa4 */ - u16 rxfrmtooshrt; /* 0xa6 */ - u16 rxinvmachdr; /* 0xa8 */ - u16 rxbadfcs; /* 0xaa */ - u16 rxbadplcp; /* 0xac */ - u16 rxcrsglitch; /* 0xae */ - u16 rxstrt; /* 0xb0 */ - u16 rxdfrmucastmbss; /* 0xb2 */ - u16 rxmfrmucastmbss; /* 0xb4 */ - u16 rxcfrmucast; /* 0xb6 */ - u16 rxrtsucast; /* 0xb8 */ - u16 rxctsucast; /* 0xba */ - u16 rxackucast; /* 0xbc */ - u16 rxdfrmocast; /* 0xbe */ - u16 rxmfrmocast; /* 0xc0 */ - u16 rxcfrmocast; /* 0xc2 */ - u16 rxrtsocast; /* 0xc4 */ - u16 rxctsocast; /* 0xc6 */ - u16 rxdfrmmcast; /* 0xc8 */ - u16 rxmfrmmcast; /* 0xca */ - u16 rxcfrmmcast; /* 0xcc */ - u16 rxbeaconmbss; /* 0xce */ - u16 rxdfrmucastobss; /* 0xd0 */ - u16 rxbeaconobss; /* 0xd2 */ - u16 rxrsptmout; /* 0xd4 */ - u16 bcntxcancl; /* 0xd6 */ - u16 PAD; - u16 rxf0ovfl; /* 0xda */ - u16 rxf1ovfl; /* 0xdc */ - u16 rxf2ovfl; /* 0xde */ - u16 txsfovfl; /* 0xe0 */ - u16 pmqovfl; /* 0xe2 */ - u16 rxcgprqfrm; /* 0xe4 */ - u16 rxcgprsqovfl; /* 0xe6 */ - u16 txcgprsfail; /* 0xe8 */ - u16 txcgprssuc; /* 0xea */ - u16 prs_timeout; /* 0xec */ - u16 rxnack; - u16 frmscons; - u16 txnack; - u16 txglitch_nack; - u16 txburst; /* 0xf6 # tx bursts */ - u16 bphy_rxcrsglitch; /* bphy rx crs glitch */ - u16 phywatchdog; /* 0xfa # of phy watchdog events */ - u16 PAD; - u16 bphy_badplcp; /* bphy bad plcp */ -} macstat_t; - -/* dot11 core-specific control flags */ -#define SICF_PCLKE 0x0004 /* PHY clock enable */ -#define SICF_PRST 0x0008 /* PHY reset */ -#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */ -#define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */ -/* NOTE: the following bw bits only apply when the core is attached - * to a NPHY (and corerev >= 11 which it will always be for NPHYs). - */ -#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */ -#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */ -#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */ -#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */ -#define SICF_GMODE 0x2000 /* gmode enable */ - -/* dot11 core-specific status flags */ -#define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */ -#define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */ -#define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */ -#define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */ - -/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */ - -#define BPHY_REG_OFT_BASE 0x0 -/* offsets for indirect access to bphy registers */ -#define BPHY_BB_CONFIG 0x01 -#define BPHY_ADCBIAS 0x02 -#define BPHY_ANACORE 0x03 -#define BPHY_PHYCRSTH 0x06 -#define BPHY_TEST 0x0a -#define BPHY_PA_TX_TO 0x10 -#define BPHY_SYNTH_DC_TO 0x11 -#define BPHY_PA_TX_TIME_UP 0x12 -#define BPHY_RX_FLTR_TIME_UP 0x13 -#define BPHY_TX_POWER_OVERRIDE 0x14 -#define BPHY_RF_OVERRIDE 0x15 -#define BPHY_RF_TR_LOOKUP1 0x16 -#define BPHY_RF_TR_LOOKUP2 0x17 -#define BPHY_COEFFS 0x18 -#define BPHY_PLL_OUT 0x19 -#define BPHY_REFRESH_MAIN 0x1a -#define BPHY_REFRESH_TO0 0x1b -#define BPHY_REFRESH_TO1 0x1c -#define BPHY_RSSI_TRESH 0x20 -#define BPHY_IQ_TRESH_HH 0x21 -#define BPHY_IQ_TRESH_H 0x22 -#define BPHY_IQ_TRESH_L 0x23 -#define BPHY_IQ_TRESH_LL 0x24 -#define BPHY_GAIN 0x25 -#define BPHY_LNA_GAIN_RANGE 0x26 -#define BPHY_JSSI 0x27 -#define BPHY_TSSI_CTL 0x28 -#define BPHY_TSSI 0x29 -#define BPHY_TR_LOSS_CTL 0x2a -#define BPHY_LO_LEAKAGE 0x2b -#define BPHY_LO_RSSI_ACC 0x2c -#define BPHY_LO_IQMAG_ACC 0x2d -#define BPHY_TX_DC_OFF1 0x2e -#define BPHY_TX_DC_OFF2 0x2f -#define BPHY_PEAK_CNT_THRESH 0x30 -#define BPHY_FREQ_OFFSET 0x31 -#define BPHY_DIVERSITY_CTL 0x32 -#define BPHY_PEAK_ENERGY_LO 0x33 -#define BPHY_PEAK_ENERGY_HI 0x34 -#define BPHY_SYNC_CTL 0x35 -#define BPHY_TX_PWR_CTRL 0x36 -#define BPHY_TX_EST_PWR 0x37 -#define BPHY_STEP 0x38 -#define BPHY_WARMUP 0x39 -#define BPHY_LMS_CFF_READ 0x3a -#define BPHY_LMS_COEFF_I 0x3b -#define BPHY_LMS_COEFF_Q 0x3c -#define BPHY_SIG_POW 0x3d -#define BPHY_RFDC_CANCEL_CTL 0x3e -#define BPHY_HDR_TYPE 0x40 -#define BPHY_SFD_TO 0x41 -#define BPHY_SFD_CTL 0x42 -#define BPHY_DEBUG 0x43 -#define BPHY_RX_DELAY_COMP 0x44 -#define BPHY_CRS_DROP_TO 0x45 -#define BPHY_SHORT_SFD_NZEROS 0x46 -#define BPHY_DSSS_COEFF1 0x48 -#define BPHY_DSSS_COEFF2 0x49 -#define BPHY_CCK_COEFF1 0x4a -#define BPHY_CCK_COEFF2 0x4b -#define BPHY_TR_CORR 0x4c -#define BPHY_ANGLE_SCALE 0x4d -#define BPHY_TX_PWR_BASE_IDX 0x4e -#define BPHY_OPTIONAL_MODES2 0x4f -#define BPHY_CCK_LMS_STEP 0x50 -#define BPHY_BYPASS 0x51 -#define BPHY_CCK_DELAY_LONG 0x52 -#define BPHY_CCK_DELAY_SHORT 0x53 -#define BPHY_PPROC_CHAN_DELAY 0x54 -#define BPHY_DDFS_ENABLE 0x58 -#define BPHY_PHASE_SCALE 0x59 -#define BPHY_FREQ_CONTROL 0x5a -#define BPHY_LNA_GAIN_RANGE_10 0x5b -#define BPHY_LNA_GAIN_RANGE_32 0x5c -#define BPHY_OPTIONAL_MODES 0x5d -#define BPHY_RX_STATUS2 0x5e -#define BPHY_RX_STATUS3 0x5f -#define BPHY_DAC_CONTROL 0x60 -#define BPHY_ANA11G_FILT_CTRL 0x62 -#define BPHY_REFRESH_CTRL 0x64 -#define BPHY_RF_OVERRIDE2 0x65 -#define BPHY_SPUR_CANCEL_CTRL 0x66 -#define BPHY_FINE_DIGIGAIN_CTRL 0x67 -#define BPHY_RSSI_LUT 0x88 -#define BPHY_RSSI_LUT_END 0xa7 -#define BPHY_TSSI_LUT 0xa8 -#define BPHY_TSSI_LUT_END 0xc7 -#define BPHY_TSSI2PWR_LUT 0x380 -#define BPHY_TSSI2PWR_LUT_END 0x39f -#define BPHY_LOCOMP_LUT 0x3a0 -#define BPHY_LOCOMP_LUT_END 0x3bf -#define BPHY_TXGAIN_LUT 0x3c0 -#define BPHY_TXGAIN_LUT_END 0x3ff - -/* Bits in BB_CONFIG: */ -#define PHY_BBC_ANT_MASK 0x0180 -#define PHY_BBC_ANT_SHIFT 7 -#define BB_DARWIN 0x1000 -#define BBCFG_RESETCCA 0x4000 -#define BBCFG_RESETRX 0x8000 - -/* Bits in phytest(0x0a): */ -#define TST_DDFS 0x2000 -#define TST_TXFILT1 0x0800 -#define TST_UNSCRAM 0x0400 -#define TST_CARR_SUPP 0x0200 -#define TST_DC_COMP_LOOP 0x0100 -#define TST_LOOPBACK 0x0080 -#define TST_TXFILT0 0x0040 -#define TST_TXTEST_ENABLE 0x0020 -#define TST_TXTEST_RATE 0x0018 -#define TST_TXTEST_PHASE 0x0007 - -/* phytest txTestRate values */ -#define TST_TXTEST_RATE_1MBPS 0 -#define TST_TXTEST_RATE_2MBPS 1 -#define TST_TXTEST_RATE_5_5MBPS 2 -#define TST_TXTEST_RATE_11MBPS 3 -#define TST_TXTEST_RATE_SHIFT 3 - -#define SHM_BYT_CNT 0x2 /* IHR location */ -#define MAX_BYT_CNT 0x600 /* Maximum frame len */ - -#endif /* _D11_H */ diff --git a/drivers/staging/brcm80211/include/dhdioctl.h b/drivers/staging/brcm80211/include/dhdioctl.h deleted file mode 100644 index f0ba53558ccd..000000000000 --- a/drivers/staging/brcm80211/include/dhdioctl.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _dhdioctl_h_ -#define _dhdioctl_h_ - -/* Linux network driver ioctl encoding */ -typedef struct dhd_ioctl { - uint cmd; /* common ioctl definition */ - void *buf; /* pointer to user buffer */ - uint len; /* length of user buffer */ - bool set; /* get or set request (optional) */ - uint used; /* bytes read or written (optional) */ - uint needed; /* bytes needed (optional) */ - uint driver; /* to identify target driver */ -} dhd_ioctl_t; - -/* per-driver magic numbers */ -#define DHD_IOCTL_MAGIC 0x00444944 - -/* bump this number if you change the ioctl interface */ -#define DHD_IOCTL_VERSION 1 - -#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */ -#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */ - -/* common ioctl definitions */ -#define DHD_GET_MAGIC 0 -#define DHD_GET_VERSION 1 -#define DHD_GET_VAR 2 -#define DHD_SET_VAR 3 - -/* message levels */ -#define DHD_ERROR_VAL 0x0001 -#define DHD_TRACE_VAL 0x0002 -#define DHD_INFO_VAL 0x0004 -#define DHD_DATA_VAL 0x0008 -#define DHD_CTL_VAL 0x0010 -#define DHD_TIMER_VAL 0x0020 -#define DHD_HDRS_VAL 0x0040 -#define DHD_BYTES_VAL 0x0080 -#define DHD_INTR_VAL 0x0100 -#define DHD_LOG_VAL 0x0200 -#define DHD_GLOM_VAL 0x0400 -#define DHD_EVENT_VAL 0x0800 -#define DHD_BTA_VAL 0x1000 -#define DHD_ISCAN_VAL 0x2000 - -#ifdef SDTEST -/* For pktgen iovar */ -typedef struct dhd_pktgen { - uint version; /* To allow structure change tracking */ - uint freq; /* Max ticks between tx/rx attempts */ - uint count; /* Test packets to send/rcv each attempt */ - uint print; /* Print counts every attempts */ - uint total; /* Total packets (or bursts) */ - uint minlen; /* Minimum length of packets to send */ - uint maxlen; /* Maximum length of packets to send */ - uint numsent; /* Count of test packets sent */ - uint numrcvd; /* Count of test packets received */ - uint numfail; /* Count of test send failures */ - uint mode; /* Test mode (type of test packets) */ - uint stop; /* Stop after this many tx failures */ -} dhd_pktgen_t; - -/* Version in case structure changes */ -#define DHD_PKTGEN_VERSION 2 - -/* Type of test packets to use */ -#define DHD_PKTGEN_ECHO 1 /* Send echo requests */ -#define DHD_PKTGEN_SEND 2 /* Send discard packets */ -#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */ -#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous - tx dongle */ -#endif /* SDTEST */ - -/* Enter idle immediately (no timeout) */ -#define DHD_IDLE_IMMEDIATE (-1) - -/* Values for idleclock iovar: other values are the sd_divisor to use - when idle */ -#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change - when idle */ -#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped - (and use SD1 mode) */ - -#endif /* _dhdioctl_h_ */ diff --git a/drivers/staging/brcm80211/include/hndrte_armtrap.h b/drivers/staging/brcm80211/include/hndrte_armtrap.h deleted file mode 100644 index 28f092c9e027..000000000000 --- a/drivers/staging/brcm80211/include/hndrte_armtrap.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _hndrte_armtrap_h -#define _hndrte_armtrap_h - -/* ARM trap handling */ - -/* Trap types defined by ARM (see arminc.h) */ - -/* Trap locations in lo memory */ -#define TRAP_STRIDE 4 -#define FIRST_TRAP TR_RST -#define LAST_TRAP (TR_FIQ * TRAP_STRIDE) - -#if defined(__ARM_ARCH_4T__) -#define MAX_TRAP_TYPE (TR_FIQ + 1) -#elif defined(__ARM_ARCH_7M__) -#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS) -#endif /* __ARM_ARCH_7M__ */ - -/* The trap structure is defined here as offsets for assembly */ -#define TR_TYPE 0x00 -#define TR_EPC 0x04 -#define TR_CPSR 0x08 -#define TR_SPSR 0x0c -#define TR_REGS 0x10 -#define TR_REG(n) (TR_REGS + (n) * 4) -#define TR_SP TR_REG(13) -#define TR_LR TR_REG(14) -#define TR_PC TR_REG(15) - -#define TRAP_T_SIZE 80 - -#ifndef _LANGUAGE_ASSEMBLY - -typedef struct _trap_struct { - u32 type; - u32 epc; - u32 cpsr; - u32 spsr; - u32 r0; - u32 r1; - u32 r2; - u32 r3; - u32 r4; - u32 r5; - u32 r6; - u32 r7; - u32 r8; - u32 r9; - u32 r10; - u32 r11; - u32 r12; - u32 r13; - u32 r14; - u32 pc; -} trap_t; - -#endif /* !_LANGUAGE_ASSEMBLY */ - -#endif /* _hndrte_armtrap_h */ diff --git a/drivers/staging/brcm80211/include/hndrte_cons.h b/drivers/staging/brcm80211/include/hndrte_cons.h deleted file mode 100644 index 5caa53fb6552..000000000000 --- a/drivers/staging/brcm80211/include/hndrte_cons.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#define CBUF_LEN (128) - -#define LOG_BUF_LEN 1024 - -typedef struct { - u32 buf; /* Can't be pointer on (64-bit) hosts */ - uint buf_size; - uint idx; - char *_buf_compat; /* Redundant pointer for backward compat. */ -} hndrte_log_t; - -typedef struct { - /* Virtual UART - * When there is no UART (e.g. Quickturn), - * the host should write a complete - * input line directly into cbuf and then write - * the length into vcons_in. - * This may also be used when there is a real UART - * (at risk of conflicting with - * the real UART). vcons_out is currently unused. - */ - volatile uint vcons_in; - volatile uint vcons_out; - - /* Output (logging) buffer - * Console output is written to a ring buffer log_buf at index log_idx. - * The host may read the output when it sees log_idx advance. - * Output will be lost if the output wraps around faster than the host - * polls. - */ - hndrte_log_t log; - - /* Console input line buffer - * Characters are read one at a time into cbuf - * until is received, then - * the buffer is processed as a command line. - * Also used for virtual UART. - */ - uint cbuf_idx; - char cbuf[CBUF_LEN]; -} hndrte_cons_t; diff --git a/drivers/staging/brcm80211/include/msgtrace.h b/drivers/staging/brcm80211/include/msgtrace.h deleted file mode 100644 index d654671a5a30..000000000000 --- a/drivers/staging/brcm80211/include/msgtrace.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _MSGTRACE_H -#define _MSGTRACE_H - -#define MSGTRACE_VERSION 1 - -/* Message trace header */ -typedef struct msgtrace_hdr { - u8 version; - u8 spare; - u16 len; /* Len of the trace */ - u32 seqnum; /* Sequence number of message. Useful - * if the messsage has been lost - * because of DMA error or a bus reset - * (ex: SDIO Func2) - */ - u32 discarded_bytes; /* Number of discarded bytes because of - trace overflow */ - u32 discarded_printf; /* Number of discarded printf - because of trace overflow */ -} __attribute__((packed)) msgtrace_hdr_t; - -#define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t) - -/* The hbus driver generates traces when sending a trace message. - * This causes endless traces. - * This flag must be set to true in any hbus traces. - * The flag is reset in the function msgtrace_put. - * This prevents endless traces but generates hasardous - * lost of traces only in bus device code. - * It is recommendat to set this flag in macro SD_TRACE - * but not in SD_ERROR for avoiding missing - * hbus error traces. hbus error trace should not generates endless traces. - */ -extern bool msgtrace_hbus_trace; - -typedef void (*msgtrace_func_send_t) (void *hdl1, void *hdl2, u8 *hdr, - u16 hdrlen, u8 *buf, - u16 buflen); - -extern void msgtrace_sent(void); -extern void msgtrace_put(char *buf, int count); -extern void msgtrace_init(void *hdl1, void *hdl2, - msgtrace_func_send_t func_send); - -#endif /* _MSGTRACE_H */ diff --git a/drivers/staging/brcm80211/include/pci_core.h b/drivers/staging/brcm80211/include/pci_core.h deleted file mode 100644 index 9153dcb8160e..000000000000 --- a/drivers/staging/brcm80211/include/pci_core.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _PCI_CORE_H_ -#define _PCI_CORE_H_ - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif - -/* Sonics side: PCI core and host control registers */ -struct sbpciregs { - u32 control; /* PCI control */ - u32 PAD[3]; - u32 arbcontrol; /* PCI arbiter control */ - u32 clkrun; /* Clkrun Control (>=rev11) */ - u32 PAD[2]; - u32 intstatus; /* Interrupt status */ - u32 intmask; /* Interrupt mask */ - u32 sbtopcimailbox; /* Sonics to PCI mailbox */ - u32 PAD[9]; - u32 bcastaddr; /* Sonics broadcast address */ - u32 bcastdata; /* Sonics broadcast data */ - u32 PAD[2]; - u32 gpioin; /* ro: gpio input (>=rev2) */ - u32 gpioout; /* rw: gpio output (>=rev2) */ - u32 gpioouten; /* rw: gpio output enable (>= rev2) */ - u32 gpiocontrol; /* rw: gpio control (>= rev2) */ - u32 PAD[36]; - u32 sbtopci0; /* Sonics to PCI translation 0 */ - u32 sbtopci1; /* Sonics to PCI translation 1 */ - u32 sbtopci2; /* Sonics to PCI translation 2 */ - u32 PAD[189]; - u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ - u16 sprom[36]; /* SPROM shadow Area */ - u32 PAD[46]; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* PCI control */ -#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ -#define PCI_RST 0x02 /* Value driven out to pin */ -#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ -#define PCI_CLK 0x08 /* Gate for clock driven out to pin */ - -/* PCI arbiter control */ -#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */ -#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */ -/* ParkID - for PCI corerev >= 8 */ -#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ -#define PCI_PARKID_SHIFT 2 -#define PCI_PARKID_EXT0 0 /* External master 0 */ -#define PCI_PARKID_EXT1 1 /* External master 1 */ -#define PCI_PARKID_EXT2 2 /* External master 2 */ -#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ -#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */ -#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */ -#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */ -#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */ - -#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */ - -/* Interrupt status/mask */ -#define PCI_INTA 0x01 /* PCI INTA# is asserted */ -#define PCI_INTB 0x02 /* PCI INTB# is asserted */ -#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ -#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ -#define PCI_PME 0x10 /* PCI PME# is asserted */ - -/* (General) PCI/SB mailbox interrupts, two bits per pci function */ -#define MAILBOX_F0_0 0x100 /* function 0, int 0 */ -#define MAILBOX_F0_1 0x200 /* function 0, int 1 */ -#define MAILBOX_F1_0 0x400 /* function 1, int 0 */ -#define MAILBOX_F1_1 0x800 /* function 1, int 1 */ -#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */ -#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */ -#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */ -#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */ - -/* Sonics broadcast address */ -#define BCAST_ADDR_MASK 0xff /* Broadcast register address */ - -/* Sonics to PCI translation types */ -#define SBTOPCI0_MASK 0xfc000000 -#define SBTOPCI1_MASK 0xfc000000 -#define SBTOPCI2_MASK 0xc0000000 -#define SBTOPCI_MEM 0 -#define SBTOPCI_IO 1 -#define SBTOPCI_CFG0 2 -#define SBTOPCI_CFG1 3 -#define SBTOPCI_PREF 0x4 /* prefetch enable */ -#define SBTOPCI_BURST 0x8 /* burst enable */ -#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ -#define SBTOPCI_RC_READ 0x00 /* memory read */ -#define SBTOPCI_RC_READLINE 0x10 /* memory read line */ -#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ - -/* PCI core index in SROM shadow area */ -#define SRSH_PI_OFFSET 0 /* first word */ -#define SRSH_PI_MASK 0xf000 /* bit 15:12 */ -#define SRSH_PI_SHIFT 12 /* bit 15:12 */ - -#endif /* _PCI_CORE_H_ */ diff --git a/drivers/staging/brcm80211/include/rpc_osl.h b/drivers/staging/brcm80211/include/rpc_osl.h deleted file mode 100644 index c59d9ed1397a..000000000000 --- a/drivers/staging/brcm80211/include/rpc_osl.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _rpcosl_h_ -#define _rpcosl_h_ - -typedef struct rpc_osl rpc_osl_t; -extern rpc_osl_t *rpc_osl_attach(struct osl_info *osh); -extern void rpc_osl_detach(rpc_osl_t *rpc_osh); - -#define RPC_OSL_LOCK(rpc_osh) rpc_osl_lock((rpc_osh)) -#define RPC_OSL_UNLOCK(rpc_osh) rpc_osl_unlock((rpc_osh)) -#define RPC_OSL_WAIT(rpc_osh, to, ptimedout) rpc_osl_wait((rpc_osh), (to), (ptimedout)) -#define RPC_OSL_WAKE(rpc_osh) rpc_osl_wake((rpc_osh)) -extern void rpc_osl_lock(rpc_osl_t *rpc_osh); -extern void rpc_osl_unlock(rpc_osl_t *rpc_osh); -extern int rpc_osl_wait(rpc_osl_t *rpc_osh, uint ms, bool *ptimedout); -extern void rpc_osl_wake(rpc_osl_t *rpc_osh); - -#endif /* _rpcosl_h_ */ diff --git a/drivers/staging/brcm80211/include/sbhndpio.h b/drivers/staging/brcm80211/include/sbhndpio.h deleted file mode 100644 index 9eabdb56da73..000000000000 --- a/drivers/staging/brcm80211/include/sbhndpio.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _sbhndpio_h_ -#define _sbhndpio_h_ - -/* PIO structure, - * support two PIO format: 2 bytes access and 4 bytes access - * basic FIFO register set is per channel(transmit or receive) - * a pair of channels is defined for convenience - */ - -/* 2byte-wide pio register set per channel(xmt or rcv) */ -typedef volatile struct { - u16 fifocontrol; - u16 fifodata; - u16 fifofree; /* only valid in xmt channel, not in rcv channel */ - u16 PAD; -} pio2regs_t; - -/* a pair of pio channels(tx and rx) */ -typedef volatile struct { - pio2regs_t tx; - pio2regs_t rx; -} pio2regp_t; - -/* 4byte-wide pio register set per channel(xmt or rcv) */ -typedef volatile struct { - u32 fifocontrol; - u32 fifodata; -} pio4regs_t; - -/* a pair of pio channels(tx and rx) */ -typedef volatile struct { - pio4regs_t tx; - pio4regs_t rx; -} pio4regp_t; - -#endif /* _sbhndpio_h_ */ diff --git a/drivers/staging/brcm80211/include/sbpcmcia.h b/drivers/staging/brcm80211/include/sbpcmcia.h deleted file mode 100644 index 6b9923f551a9..000000000000 --- a/drivers/staging/brcm80211/include/sbpcmcia.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SBPCMCIA_H -#define _SBPCMCIA_H - -/* All the addresses that are offsets in attribute space are divided - * by two to account for the fact that odd bytes are invalid in - * attribute space and our read/write routines make the space appear - * as if they didn't exist. Still we want to show the original numbers - * as documented in the hnd_pcmcia core manual. - */ - -/* PCMCIA Function Configuration Registers */ -#define PCMCIA_FCR (0x700 / 2) - -#define FCR0_OFF 0 -#define FCR1_OFF (0x40 / 2) -#define FCR2_OFF (0x80 / 2) -#define FCR3_OFF (0xc0 / 2) - -#define PCMCIA_FCR0 (0x700 / 2) -#define PCMCIA_FCR1 (0x740 / 2) -#define PCMCIA_FCR2 (0x780 / 2) -#define PCMCIA_FCR3 (0x7c0 / 2) - -/* Standard PCMCIA FCR registers */ - -#define PCMCIA_COR 0 - -#define COR_RST 0x80 -#define COR_LEV 0x40 -#define COR_IRQEN 0x04 -#define COR_BLREN 0x01 -#define COR_FUNEN 0x01 - -#define PCICIA_FCSR (2 / 2) -#define PCICIA_PRR (4 / 2) -#define PCICIA_SCR (6 / 2) -#define PCICIA_ESR (8 / 2) - -#define PCM_MEMOFF 0x0000 -#define F0_MEMOFF 0x1000 -#define F1_MEMOFF 0x2000 -#define F2_MEMOFF 0x3000 -#define F3_MEMOFF 0x4000 - -/* Memory base in the function fcr's */ -#define MEM_ADDR0 (0x728 / 2) -#define MEM_ADDR1 (0x72a / 2) -#define MEM_ADDR2 (0x72c / 2) - -/* PCMCIA base plus Srom access in fcr0: */ -#define PCMCIA_ADDR0 (0x072e / 2) -#define PCMCIA_ADDR1 (0x0730 / 2) -#define PCMCIA_ADDR2 (0x0732 / 2) - -#define MEM_SEG (0x0734 / 2) -#define SROM_CS (0x0736 / 2) -#define SROM_DATAL (0x0738 / 2) -#define SROM_DATAH (0x073a / 2) -#define SROM_ADDRL (0x073c / 2) -#define SROM_ADDRH (0x073e / 2) -#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ -#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ - -/* Values for srom_cs: */ -#define SROM_IDLE 0 -#define SROM_WRITE 1 -#define SROM_READ 2 -#define SROM_WEN 4 -#define SROM_WDS 7 -#define SROM_DONE 8 - -/* Fields in srom_info: */ -#define SRI_SZ_MASK 0x03 -#define SRI_BLANK 0x04 -#define SRI_OTP 0x80 - -#if !defined(ESTA_POSTMOGRIFY_REMOVAL) -/* CIS stuff */ - -/* The CIS stops where the FCRs start */ -#define CIS_SIZE PCMCIA_FCR - -/* CIS tuple length field max */ -#define CIS_TUPLE_LEN_MAX 0xff - -/* Standard tuples we know about */ - -#define CISTPL_NULL 0x00 -#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ -#define CISTPL_MANFID 0x20 /* Manufacturer and device id */ -#define CISTPL_FUNCID 0x21 /* Function identification */ -#define CISTPL_FUNCE 0x22 /* Function extensions */ -#define CISTPL_CFTABLE 0x1b /* Config table entry */ -#define CISTPL_END 0xff /* End of the CIS tuple chain */ - -/* Function identifier provides context for the function extentions tuple */ -#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */ - -/* Function extensions for LANs (assumed for extensions other than SDIO) */ -#define LAN_TECH 1 /* Technology type */ -#define LAN_SPEED 2 /* Raw bit rate */ -#define LAN_MEDIA 3 /* Transmission media */ -#define LAN_NID 4 /* Node identification (aka MAC addr) */ -#define LAN_CONN 5 /* Connector standard */ - -/* CFTable */ -#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ -#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ -#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ - -/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll - * take one for HNBU, and use "extensions" (a la FUNCE) within it. - */ - -#define CISTPL_BRCM_HNBU 0x80 - -/* Subtypes of BRCM_HNBU: */ - -#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ -#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ -#define HNBU_BOARDREV 0x02 /* One byte board revision */ -#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) - * or 9 (sromrev > 1) bytes - */ -#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ -#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ -#define HNBU_AA 0x06 /* Antennas available */ -#define HNBU_AG 0x07 /* Antenna gain */ -#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ -#define HNBU_LEDS 0x09 /* LED set */ -#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) - * in rev 2 - */ -#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ -#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ -#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ -#define HNBU_PAPARMS5G 0x0e /* 5G PA params */ -#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ -#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ -#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, - * 2 bytes, rev 3. - */ -#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ -#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ -#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ -#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ -#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ -#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ -#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ -#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ -#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ -#define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */ -#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ -#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */ -#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */ -#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ -#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */ -#define HNBU_REGREV 0x22 /* 1 byte; */ -#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */ -#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */ -#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */ -#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */ -#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */ -#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */ -#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */ -#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */ -#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */ -#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */ -#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */ -#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */ -#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */ - -#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ -#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */ -#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */ -#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */ -#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */ -#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */ -#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */ -#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */ - -#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */ -#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 - * plus extra info appended. - */ -#define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */ -#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */ -#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */ -#endif /* !defined(ESTA_POSTMOGRIFY_REMOVAL) */ - -/* sbtmstatelow */ -#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ -#define SBTML_INT_EN 0x20000 /* enable sb interrupt */ - -/* sbtmstatehigh */ -#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ - -#endif /* _SBPCMCIA_H */ diff --git a/drivers/staging/brcm80211/include/sbsocram.h b/drivers/staging/brcm80211/include/sbsocram.h deleted file mode 100644 index 0cfe9852b27f..000000000000 --- a/drivers/staging/brcm80211/include/sbsocram.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SBSOCRAM_H -#define _SBSOCRAM_H - -#ifndef _LANGUAGE_ASSEMBLY - -/* cpp contortions to concatenate w/arg prescan */ -#ifndef PAD -#define _PADLINE(line) pad ## line -#define _XSTR(line) _PADLINE(line) -#define PAD _XSTR(__LINE__) -#endif /* PAD */ - -/* Memcsocram core registers */ -typedef volatile struct sbsocramregs { - u32 coreinfo; - u32 bwalloc; - u32 extracoreinfo; - u32 biststat; - u32 bankidx; - u32 standbyctrl; - - u32 errlogstatus; /* rev 6 */ - u32 errlogaddr; /* rev 6 */ - /* used for patching rev 3 & 5 */ - u32 cambankidx; - u32 cambankstandbyctrl; - u32 cambankpatchctrl; - u32 cambankpatchtblbaseaddr; - u32 cambankcmdreg; - u32 cambankdatareg; - u32 cambankmaskreg; - u32 PAD[1]; - u32 bankinfo; /* corev 8 */ - u32 PAD[15]; - u32 extmemconfig; - u32 extmemparitycsr; - u32 extmemparityerrdata; - u32 extmemparityerrcnt; - u32 extmemwrctrlandsize; - u32 PAD[84]; - u32 workaround; - u32 pwrctl; /* corerev >= 2 */ -} sbsocramregs_t; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* Register offsets */ -#define SR_COREINFO 0x00 -#define SR_BWALLOC 0x04 -#define SR_BISTSTAT 0x0c -#define SR_BANKINDEX 0x10 -#define SR_BANKSTBYCTL 0x14 -#define SR_PWRCTL 0x1e8 - -/* Coreinfo register */ -#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ -#define SRCI_PT_SHIFT 16 -/* port types : SRCI_PT__ */ -#define SRCI_PT_OCP_OCP 0 -#define SRCI_PT_AXI_OCP 1 -#define SRCI_PT_ARM7AHB_OCP 2 -#define SRCI_PT_CM3AHB_OCP 3 -#define SRCI_PT_AXI_AXI 4 -#define SRCI_PT_AHB_AXI 5 -/* corerev >= 3 */ -#define SRCI_LSS_MASK 0x00f00000 -#define SRCI_LSS_SHIFT 20 -#define SRCI_LRS_MASK 0x0f000000 -#define SRCI_LRS_SHIFT 24 - -/* In corerev 0, the memory size is 2 to the power of the - * base plus 16 plus to the contents of the memsize field plus 1. - */ -#define SRCI_MS0_MASK 0xf -#define SR_MS0_BASE 16 - -/* - * In corerev 1 the bank size is 2 ^ the bank size field plus 14, - * the memory size is number of banks times bank size. - * The same applies to rom size. - */ -#define SRCI_ROMNB_MASK 0xf000 -#define SRCI_ROMNB_SHIFT 12 -#define SRCI_ROMBSZ_MASK 0xf00 -#define SRCI_ROMBSZ_SHIFT 8 -#define SRCI_SRNB_MASK 0xf0 -#define SRCI_SRNB_SHIFT 4 -#define SRCI_SRBSZ_MASK 0xf -#define SRCI_SRBSZ_SHIFT 0 - -#define SR_BSZ_BASE 14 - -/* Standby control register */ -#define SRSC_SBYOVR_MASK 0x80000000 -#define SRSC_SBYOVR_SHIFT 31 -#define SRSC_SBYOVRVAL_MASK 0x60000000 -#define SRSC_SBYOVRVAL_SHIFT 29 -#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ -#define SRSC_SBYEN_SHIFT 24 - -/* Power control register */ -#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ -#define SRPC_PMU_STBYDIS_SHIFT 4 -#define SRPC_STBYOVRVAL_MASK 0x00000008 -#define SRPC_STBYOVRVAL_SHIFT 3 -#define SRPC_STBYOVR_MASK 0x00000007 -#define SRPC_STBYOVR_SHIFT 0 - -/* Extra core capability register */ -#define SRECC_NUM_BANKS_MASK 0x000000F0 -#define SRECC_NUM_BANKS_SHIFT 4 -#define SRECC_BANKSIZE_MASK 0x0000000F -#define SRECC_BANKSIZE_SHIFT 0 - -#define SRECC_BANKSIZE(value) (1 << (value)) - -/* CAM bank patch control */ -#define SRCBPC_PATCHENABLE 0x80000000 - -#define SRP_ADDRESS 0x0001FFFC -#define SRP_VALID 0x8000 - -/* CAM bank command reg */ -#define SRCMD_WRITE 0x00020000 -#define SRCMD_READ 0x00010000 -#define SRCMD_DONE 0x80000000 - -#define SRCMD_DONE_DLY 1000 - -/* bankidx and bankinfo reg defines corerev >= 8 */ -#define SOCRAM_BANKINFO_SZMASK 0x3f -#define SOCRAM_BANKIDX_ROM_MASK 0x100 - -#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 -/* socram bankinfo memtype */ -#define SOCRAM_MEMTYPE_RAM 0 -#define SOCRAM_MEMTYPE_R0M 1 -#define SOCRAM_MEMTYPE_DEVRAM 2 - -#define SOCRAM_BANKINFO_REG 0x40 -#define SOCRAM_BANKIDX_REG 0x10 -#define SOCRAM_BANKINFO_STDBY_MASK 0x400 -#define SOCRAM_BANKINFO_STDBY_TIMER 0x800 - -/* bankinfo rev >= 10 */ -#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 -#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 -#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 -#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 - -/* extracoreinfo register */ -#define SOCRAM_DEVRAMBANK_MASK 0xF000 -#define SOCRAM_DEVRAMBANK_SHIFT 12 - -/* bank info to calculate bank size */ -#define SOCRAM_BANKINFO_SZBASE 8192 -#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ - -#endif /* _SBSOCRAM_H */ diff --git a/drivers/staging/brcm80211/include/sdioh.h b/drivers/staging/brcm80211/include/sdioh.h deleted file mode 100644 index f96aaf9cec74..000000000000 --- a/drivers/staging/brcm80211/include/sdioh.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SDIOH_H -#define _SDIOH_H - -#define SD_SysAddr 0x000 -#define SD_BlockSize 0x004 -#define SD_BlockCount 0x006 -#define SD_Arg0 0x008 -#define SD_Arg1 0x00A -#define SD_TransferMode 0x00C -#define SD_Command 0x00E -#define SD_Response0 0x010 -#define SD_Response1 0x012 -#define SD_Response2 0x014 -#define SD_Response3 0x016 -#define SD_Response4 0x018 -#define SD_Response5 0x01A -#define SD_Response6 0x01C -#define SD_Response7 0x01E -#define SD_BufferDataPort0 0x020 -#define SD_BufferDataPort1 0x022 -#define SD_PresentState 0x024 -#define SD_HostCntrl 0x028 -#define SD_PwrCntrl 0x029 -#define SD_BlockGapCntrl 0x02A -#define SD_WakeupCntrl 0x02B -#define SD_ClockCntrl 0x02C -#define SD_TimeoutCntrl 0x02E -#define SD_SoftwareReset 0x02F -#define SD_IntrStatus 0x030 -#define SD_ErrorIntrStatus 0x032 -#define SD_IntrStatusEnable 0x034 -#define SD_ErrorIntrStatusEnable 0x036 -#define SD_IntrSignalEnable 0x038 -#define SD_ErrorIntrSignalEnable 0x03A -#define SD_CMD12ErrorStatus 0x03C -#define SD_Capabilities 0x040 -#define SD_Capabilities_Reserved 0x044 -#define SD_MaxCurCap 0x048 -#define SD_MaxCurCap_Reserved 0x04C -#define SD_ADMA_SysAddr 0x58 -#define SD_SlotInterruptStatus 0x0FC -#define SD_HostControllerVersion 0x0FE - -/* SD specific registers in PCI config space */ -#define SD_SlotInfo 0x40 - -#endif /* _SDIOH_H */ diff --git a/drivers/staging/brcm80211/include/sdiovar.h b/drivers/staging/brcm80211/include/sdiovar.h deleted file mode 100644 index d1cfa5f0a982..000000000000 --- a/drivers/staging/brcm80211/include/sdiovar.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _sdiovar_h_ -#define _sdiovar_h_ - -typedef struct sdreg { - int func; - int offset; - int value; -} sdreg_t; - -/* Common msglevel constants */ -#define SDH_ERROR_VAL 0x0001 /* Error */ -#define SDH_TRACE_VAL 0x0002 /* Trace */ -#define SDH_INFO_VAL 0x0004 /* Info */ -#define SDH_DEBUG_VAL 0x0008 /* Debug */ -#define SDH_DATA_VAL 0x0010 /* Data */ -#define SDH_CTRL_VAL 0x0020 /* Control Regs */ -#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ -#define SDH_DMA_VAL 0x0080 /* DMA */ - -#define NUM_PREV_TRANSACTIONS 16 - -#endif /* _sdiovar_h_ */ diff --git a/drivers/staging/brcm80211/include/spid.h b/drivers/staging/brcm80211/include/spid.h deleted file mode 100644 index e0abb8432886..000000000000 --- a/drivers/staging/brcm80211/include/spid.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2010 Broadcom Corporation - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SPI_H -#define _SPI_H - -/* - * Brcm SPI Device Register Map. - * - */ - -typedef volatile struct { - u8 config; /* 0x00, len, endian, clock, speed, polarity, wakeup */ - u8 response_delay; /* 0x01, read response delay in bytes (corerev < 3) */ - u8 status_enable; /* 0x02, status-enable, intr with status, response_delay - * function selection, command/data error check - */ - u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ - u16 intr_reg; /* 0x04, Intr status register */ - u16 intr_en_reg; /* 0x06, Intr mask register */ - u32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ - u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ - u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ - u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ - u32 test_read; /* 0x14, RO 0xfeedbead signature */ - u32 test_rw; /* 0x18, RW */ - u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ - u8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */ - u8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */ - u8 resp_delay_f3; /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */ -} spi_regs_t; - -/* SPI device register offsets */ -#define SPID_CONFIG 0x00 -#define SPID_RESPONSE_DELAY 0x01 -#define SPID_STATUS_ENABLE 0x02 -#define SPID_RESET_BP 0x03 /* (corerev >= 1) */ -#define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */ -#define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */ -#define SPID_STATUS_REG 0x08 /* 32 bits */ -#define SPID_F1_INFO_REG 0x0C /* 16 bits */ -#define SPID_F2_INFO_REG 0x0E /* 16 bits */ -#define SPID_F3_INFO_REG 0x10 /* 16 bits */ -#define SPID_TEST_READ 0x14 /* 32 bits */ -#define SPID_TEST_RW 0x18 /* 32 bits */ -#define SPID_RESP_DELAY_F0 0x1c /* 8 bits (corerev >= 3) */ -#define SPID_RESP_DELAY_F1 0x1d /* 8 bits (corerev >= 3) */ -#define SPID_RESP_DELAY_F2 0x1e /* 8 bits (corerev >= 3) */ -#define SPID_RESP_DELAY_F3 0x1f /* 8 bits (corerev >= 3) */ - -/* Bit masks for SPID_CONFIG device register */ -#define WORD_LENGTH_32 0x1 /* 0/1 16/32 bit word length */ -#define ENDIAN_BIG 0x2 /* 0/1 Little/Big Endian */ -#define CLOCK_PHASE 0x4 /* 0/1 clock phase delay */ -#define CLOCK_POLARITY 0x8 /* 0/1 Idle state clock polarity is low/high */ -#define HIGH_SPEED_MODE 0x10 /* 1/0 High Speed mode / Normal mode */ -#define INTR_POLARITY 0x20 /* 1/0 Interrupt active polarity is high/low */ -#define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */ - -/* Bit mask for SPID_RESPONSE_DELAY device register */ -#define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */ - -/* Bit mask for SPID_STATUS_ENABLE device register */ -#define STATUS_ENABLE 0x1 /* 1/0 Status sent/not sent to host after read/write */ -#define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */ -#define RESP_DELAY_ALL 0x4 /* Applicability of resp delay to F1 or all func's read */ -#define DWORD_PKT_LEN_EN 0x8 /* Packet len denoted in dwords instead of bytes */ -#define CMD_ERR_CHK_EN 0x20 /* Command error check enable */ -#define DATA_ERR_CHK_EN 0x40 /* Data error check enable */ - -/* Bit mask for SPID_RESET_BP device register */ -#define RESET_ON_WLAN_BP_RESET 0x4 /* enable reset for WLAN backplane */ -#define RESET_ON_BT_BP_RESET 0x8 /* enable reset for BT backplane */ -#define RESET_SPI 0x80 /* reset the above enabled logic */ - -/* Bit mask for SPID_INTR_REG device register */ -#define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */ -#define F2_F3_FIFO_RD_UNDERFLOW 0x0002 -#define F2_F3_FIFO_WR_OVERFLOW 0x0004 -#define COMMAND_ERROR 0x0008 /* Cleared by writing 1 */ -#define DATA_ERROR 0x0010 /* Cleared by writing 1 */ -#define F2_PACKET_AVAILABLE 0x0020 -#define F3_PACKET_AVAILABLE 0x0040 -#define F1_OVERFLOW 0x0080 /* Due to last write. Bkplane has pending write requests */ -#define MISC_INTR0 0x0100 -#define MISC_INTR1 0x0200 -#define MISC_INTR2 0x0400 -#define MISC_INTR3 0x0800 -#define MISC_INTR4 0x1000 -#define F1_INTR 0x2000 -#define F2_INTR 0x4000 -#define F3_INTR 0x8000 - -/* Bit mask for 32bit SPID_STATUS_REG device register */ -#define STATUS_DATA_NOT_AVAILABLE 0x00000001 -#define STATUS_UNDERFLOW 0x00000002 -#define STATUS_OVERFLOW 0x00000004 -#define STATUS_F2_INTR 0x00000008 -#define STATUS_F3_INTR 0x00000010 -#define STATUS_F2_RX_READY 0x00000020 -#define STATUS_F3_RX_READY 0x00000040 -#define STATUS_HOST_CMD_DATA_ERR 0x00000080 -#define STATUS_F2_PKT_AVAILABLE 0x00000100 -#define STATUS_F2_PKT_LEN_MASK 0x000FFE00 -#define STATUS_F2_PKT_LEN_SHIFT 9 -#define STATUS_F3_PKT_AVAILABLE 0x00100000 -#define STATUS_F3_PKT_LEN_MASK 0xFFE00000 -#define STATUS_F3_PKT_LEN_SHIFT 21 - -/* Bit mask for 16 bits SPID_F1_INFO_REG device register */ -#define F1_ENABLED 0x0001 -#define F1_RDY_FOR_DATA_TRANSFER 0x0002 -#define F1_MAX_PKT_SIZE 0x01FC - -/* Bit mask for 16 bits SPID_F2_INFO_REG device register */ -#define F2_ENABLED 0x0001 -#define F2_RDY_FOR_DATA_TRANSFER 0x0002 -#define F2_MAX_PKT_SIZE 0x3FFC - -/* Bit mask for 16 bits SPID_F3_INFO_REG device register */ -#define F3_ENABLED 0x0001 -#define F3_RDY_FOR_DATA_TRANSFER 0x0002 -#define F3_MAX_PKT_SIZE 0x3FFC - -/* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */ -#define TEST_RO_DATA_32BIT_LE 0xFEEDBEAD - -/* Maximum number of I/O funcs */ -#define SPI_MAX_IOFUNCS 4 - -#define SPI_MAX_PKT_LEN (2048*4) - -/* Misc defines */ -#define SPI_FUNC_0 0 -#define SPI_FUNC_1 1 -#define SPI_FUNC_2 2 -#define SPI_FUNC_3 3 - -#define WAIT_F2RXFIFORDY 100 -#define WAIT_F2RXFIFORDY_DELAY 20 - -#endif /* _SPI_H */ diff --git a/drivers/staging/brcm80211/util/bcmsrom_tbl.h b/drivers/staging/brcm80211/util/bcmsrom_tbl.h new file mode 100644 index 000000000000..22ae7c1c18fb --- /dev/null +++ b/drivers/staging/brcm80211/util/bcmsrom_tbl.h @@ -0,0 +1,583 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _bcmsrom_tbl_h_ +#define _bcmsrom_tbl_h_ + +#include "sbpcmcia.h" +#include "wlioctl.h" + +typedef struct { + const char *name; + u32 revmask; + u32 flags; + u16 off; + u16 mask; +} sromvar_t; + +#define SRFL_MORE 1 /* value continues as described by the next entry */ +#define SRFL_NOFFS 2 /* value bits can't be all one's */ +#define SRFL_PRHEX 4 /* value is in hexdecimal format */ +#define SRFL_PRSIGN 8 /* value is in signed decimal format */ +#define SRFL_CCODE 0x10 /* value is in country code format */ +#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ +#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ +#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ + +/* Assumptions: + * - Ethernet address spans across 3 consective words + * + * Table rules: + * - Add multiple entries next to each other if a value spans across multiple words + * (even multiple fields in the same word) with each entry except the last having + * it's SRFL_MORE bit set. + * - Ethernet address entry does not follow above rule and must not have SRFL_MORE + * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. + * - The last entry's name field must be NULL to indicate the end of the table. Other + * entries must have non-NULL name. + */ + +static const sromvar_t pci_sromvars[] = { + {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff}, + {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, + {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, + {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, + {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, + {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, + {"", 0, 0, SROM_BFL2, 0xffff}, + {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, + {"", 0, 0, SROM3_BFL2, 0xffff}, + {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff}, + {"", 0, 0, SROM4_BFL1, 0xffff}, + {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff}, + {"", 0, 0, SROM5_BFL1, 0xffff}, + {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff}, + {"", 0, 0, SROM8_BFL1, 0xffff}, + {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff}, + {"", 0, 0, SROM4_BFL3, 0xffff}, + {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff}, + {"", 0, 0, SROM5_BFL3, 0xffff}, + {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff}, + {"", 0, 0, SROM8_BFL3, 0xffff}, + {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, + {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, + {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, + {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, + {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, + {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff}, + {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, + {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, + {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff}, + {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff}, + {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff}, + {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff}, + {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, + {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff}, + {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, + {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff}, + {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, + {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff}, + {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, + {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff}, + {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, + {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff}, + {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, + {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, + {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, + {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, + {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, + {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, + {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, + {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, + {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, + {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, + {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, + {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, + {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, + {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00}, + {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff}, + {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, + {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff}, + {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, + {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, + {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff}, + {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, + {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, + {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00}, + {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, + {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, + {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, + {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, + {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, + {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, + {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff}, + {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00}, + {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff}, + {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00}, + {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, + {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, + {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, + {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, + {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, + {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, + {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, + {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, + {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, + {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, + {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, + {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, + {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, + {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, + {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, + {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, + {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, + {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, + {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, + {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, + {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, + {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, + {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00}, + {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff}, + {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00}, + {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, + {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, + {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, + {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, + {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, + {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800}, + {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700}, + {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0}, + {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f}, + {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, + {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, + {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, + {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, + {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800}, + {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700}, + {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0}, + {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f}, + {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, + {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, + {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, + {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, + {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff}, + {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00}, + {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff}, + {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00}, + {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, + {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, + {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, + {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, + {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, + {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, + {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, + {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, + {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, + {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, + {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, + {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, + {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, + {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, + {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, + {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, + {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, + {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, + {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, + {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, + {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00}, + {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff}, + {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, + {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, + {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, + {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, + {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, + {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, + {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, + {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, + {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, + {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, + {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, + {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, + {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, + {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, + {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, + {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, + + {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, + {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, + {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, + {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff}, + {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, + {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, + {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, + {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, + {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, + {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, + {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff}, + {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff}, + {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff}, + {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff}, + {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, + {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, + {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, + 0x00ff}, + {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, + {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, + 0x0300}, + {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, + 0x000f}, + {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, + {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, + {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, + + {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, + {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, + {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, + {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, + {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, + {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, + {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, + {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, + {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, + {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, + {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, + {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, + {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, + {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, + {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, + {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, + {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, + {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, + {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, + {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, + {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, + {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, + {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, + {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, + {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, + {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, + {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, + {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, + {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, + {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, + {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, + {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, + {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, + {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, + {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, + {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, + {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, + {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, + {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, + {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, + {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, + {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, + {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, + {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, + {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, + {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, + {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, + {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, + {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, + {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, + {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, + {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, + {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, + {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, + {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, + {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, + {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, + {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, + {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, + {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, + {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, + {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, + {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, + {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, + {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, + {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, + {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, + {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, + {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, + {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, + {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, + {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, + {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, + {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, + {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, + {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, + {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, + {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, + {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, + {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, + {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, + {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, + {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, + {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, + {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, + {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, + {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, + {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, + {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, + {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, + + /* power per rate from sromrev 9 */ + {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff}, + {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, + {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20, + 0xffff}, + {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, + {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, + 0xffff}, + {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, + {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, + 0xffff}, + {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, + {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, + {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, + 0xffff}, + {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, + {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, + {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, + 0xffff}, + {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, + {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, + {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, + {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, + {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, + {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, + {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, + {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, + {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, + {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, + {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, + {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, + {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, + {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, + {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, + {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, + {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, + {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, + {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, + {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, + {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, + 0xffff}, + {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, + {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, + {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, + {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff}, + {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff}, + + {NULL, 0, 0, 0, 0} +}; + +static const sromvar_t perpath_pci_sromvars[] = { + {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, + {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, + {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, + {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, + {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, + {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, + {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, + {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, + {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, + {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, + {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, + {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, + {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, + {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, + {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, + {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, + {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, + {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, + {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, + {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, + {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, + {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, + {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff}, + {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00}, + {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00}, + {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, + {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, + {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, + {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff}, + {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff}, + {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00}, + {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, + {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, + {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, + {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, + {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, + {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, + {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, + {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, + {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, + {NULL, 0, 0, 0, 0} +}; + +#if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) +#define PHY_TYPE_N 4 /* N-Phy value */ +#define PHY_TYPE_LP 5 /* LP-Phy value */ +#endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */ +#if !defined(PHY_TYPE_NULL) +#define PHY_TYPE_NULL 0xf /* Invalid Phy value */ +#endif /* !defined(PHY_TYPE_NULL) */ + +typedef struct { + u16 phy_type; + u16 bandrange; + u16 chain; + const char *vars; +} pavars_t; + +static const pavars_t pavars[] = { + /* NPHY */ + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0, + "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1, + "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0, + "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1, + "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, + /* LPPHY */ + {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"}, + {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"}, + {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"}, + {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"}, + {PHY_TYPE_NULL, 0, 0, ""} +}; + +typedef struct { + u16 phy_type; + u16 bandrange; + const char *vars; +} povars_t; + +static const povars_t povars[] = { + /* NPHY */ + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, + "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 " + "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, + "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 " + "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, + "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 " + "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"}, + {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, + "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 " + "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"}, + {PHY_TYPE_NULL, 0, ""} +}; + +typedef struct { + u8 tag; /* Broadcom subtag name */ + u8 len; /* Length field of the tuple, note that it includes the + * subtag name (1 byte): 1 + tuple content length + */ + const char *params; +} cis_tuple_t; + +#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ +#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ +#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ +#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ + +static const cis_tuple_t cis_hnbuvars[] = { + {OTP_RAW1, 0, ""}, /* special case */ + {OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */ + {OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */ + {HNBU_SROMREV, 2, "1sromrev"}, + /* NOTE: subdevid is also written to boardtype. + * Need to write HNBU_BOARDTYPE to change it if it is different. + */ + {HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, + {HNBU_BOARDREV, 3, "2boardrev"}, + {HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, + {HNBU_AA, 3, "1aa2g 1aa5g"}, + {HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */ + {HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"}, + {HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"}, + {HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"}, + {HNBU_CCODE, 4, "2ccode 1cctl"}, + {HNBU_CCKPO, 3, "2cckpo"}, + {HNBU_OFDMPO, 5, "4ofdmpo"}, + {HNBU_RDLID, 3, "2rdlid"}, + {HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */ + {HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */ + {HNBU_XTALFREQ, 5, "4xtalfreq"}, + {HNBU_TRI2G, 2, "1tri2g"}, + {HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"}, + {HNBU_RXPO2G, 2, "1rxpo2g"}, + {HNBU_RXPO5G, 2, "1rxpo5g"}, + {HNBU_BOARDNUM, 3, "2boardnum"}, + {HNBU_MACADDR, 7, "6macaddr"}, /* special case */ + {HNBU_RDLSN, 3, "2rdlsn"}, + {HNBU_BOARDTYPE, 3, "2boardtype"}, + {HNBU_LEDDC, 3, "2leddc"}, + {HNBU_RDLRNDIS, 2, "1rdlndis"}, + {HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"}, + {HNBU_REGREV, 2, "1regrev"}, + {HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g" "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"}, /* special case */ + {HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " + "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 " + "2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 " + "2pa5ghw1a0 2pa5ghw2a0"}, + {HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " + "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 " + "2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 " + "2pa5ghw1a1 2pa5ghw2a1"}, + {HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " + "4ofdm5ghpo"}, + {HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " + "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, + {HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " + "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, + {HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " + "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " + "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " + "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, + {HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"}, + {HNBU_PO_CDD, 3, "2cddpo"}, + {HNBU_PO_STBC, 3, "2stbcpo"}, + {HNBU_PO_40M, 3, "2bw40po"}, + {HNBU_PO_40MDUP, 3, "2bwduppo"}, + {HNBU_RDLRWU, 2, "1rdlrwu"}, + {HNBU_WPS, 3, "1wpsgpio 1wpsled"}, + {HNBU_USBFS, 2, "1usbfs"}, + {HNBU_CUSTOM1, 5, "4customvar1"}, + {OTP_RAW, 0, ""}, /* special case */ + {HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, + {HNBU_USBEPNUM, 3, "2usbepnum"}, + {0xFF, 0, ""} +}; + +#endif /* _bcmsrom_tbl_h_ */ diff --git a/drivers/staging/brcm80211/util/pci_core.h b/drivers/staging/brcm80211/util/pci_core.h new file mode 100644 index 000000000000..9153dcb8160e --- /dev/null +++ b/drivers/staging/brcm80211/util/pci_core.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PCI_CORE_H_ +#define _PCI_CORE_H_ + +#ifndef _LANGUAGE_ASSEMBLY + +/* cpp contortions to concatenate w/arg prescan */ +#ifndef PAD +#define _PADLINE(line) pad ## line +#define _XSTR(line) _PADLINE(line) +#define PAD _XSTR(__LINE__) +#endif + +/* Sonics side: PCI core and host control registers */ +struct sbpciregs { + u32 control; /* PCI control */ + u32 PAD[3]; + u32 arbcontrol; /* PCI arbiter control */ + u32 clkrun; /* Clkrun Control (>=rev11) */ + u32 PAD[2]; + u32 intstatus; /* Interrupt status */ + u32 intmask; /* Interrupt mask */ + u32 sbtopcimailbox; /* Sonics to PCI mailbox */ + u32 PAD[9]; + u32 bcastaddr; /* Sonics broadcast address */ + u32 bcastdata; /* Sonics broadcast data */ + u32 PAD[2]; + u32 gpioin; /* ro: gpio input (>=rev2) */ + u32 gpioout; /* rw: gpio output (>=rev2) */ + u32 gpioouten; /* rw: gpio output enable (>= rev2) */ + u32 gpiocontrol; /* rw: gpio control (>= rev2) */ + u32 PAD[36]; + u32 sbtopci0; /* Sonics to PCI translation 0 */ + u32 sbtopci1; /* Sonics to PCI translation 1 */ + u32 sbtopci2; /* Sonics to PCI translation 2 */ + u32 PAD[189]; + u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ + u16 sprom[36]; /* SPROM shadow Area */ + u32 PAD[46]; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* PCI control */ +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ +#define PCI_RST 0x02 /* Value driven out to pin */ +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */ + +/* PCI arbiter control */ +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */ +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */ +/* ParkID - for PCI corerev >= 8 */ +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ +#define PCI_PARKID_SHIFT 2 +#define PCI_PARKID_EXT0 0 /* External master 0 */ +#define PCI_PARKID_EXT1 1 /* External master 1 */ +#define PCI_PARKID_EXT2 2 /* External master 2 */ +#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ +#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */ +#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */ +#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */ +#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */ + +#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */ + +/* Interrupt status/mask */ +#define PCI_INTA 0x01 /* PCI INTA# is asserted */ +#define PCI_INTB 0x02 /* PCI INTB# is asserted */ +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ +#define PCI_PME 0x10 /* PCI PME# is asserted */ + +/* (General) PCI/SB mailbox interrupts, two bits per pci function */ +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */ +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */ +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */ +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */ +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */ +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */ +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */ +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */ + +/* Sonics broadcast address */ +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */ + +/* Sonics to PCI translation types */ +#define SBTOPCI0_MASK 0xfc000000 +#define SBTOPCI1_MASK 0xfc000000 +#define SBTOPCI2_MASK 0xc0000000 +#define SBTOPCI_MEM 0 +#define SBTOPCI_IO 1 +#define SBTOPCI_CFG0 2 +#define SBTOPCI_CFG1 3 +#define SBTOPCI_PREF 0x4 /* prefetch enable */ +#define SBTOPCI_BURST 0x8 /* burst enable */ +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ +#define SBTOPCI_RC_READ 0x00 /* memory read */ +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */ +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ + +/* PCI core index in SROM shadow area */ +#define SRSH_PI_OFFSET 0 /* first word */ +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */ +#define SRSH_PI_SHIFT 12 /* bit 15:12 */ + +#endif /* _PCI_CORE_H_ */ diff --git a/drivers/staging/brcm80211/util/sbpcmcia.h b/drivers/staging/brcm80211/util/sbpcmcia.h new file mode 100644 index 000000000000..6b9923f551a9 --- /dev/null +++ b/drivers/staging/brcm80211/util/sbpcmcia.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SBPCMCIA_H +#define _SBPCMCIA_H + +/* All the addresses that are offsets in attribute space are divided + * by two to account for the fact that odd bytes are invalid in + * attribute space and our read/write routines make the space appear + * as if they didn't exist. Still we want to show the original numbers + * as documented in the hnd_pcmcia core manual. + */ + +/* PCMCIA Function Configuration Registers */ +#define PCMCIA_FCR (0x700 / 2) + +#define FCR0_OFF 0 +#define FCR1_OFF (0x40 / 2) +#define FCR2_OFF (0x80 / 2) +#define FCR3_OFF (0xc0 / 2) + +#define PCMCIA_FCR0 (0x700 / 2) +#define PCMCIA_FCR1 (0x740 / 2) +#define PCMCIA_FCR2 (0x780 / 2) +#define PCMCIA_FCR3 (0x7c0 / 2) + +/* Standard PCMCIA FCR registers */ + +#define PCMCIA_COR 0 + +#define COR_RST 0x80 +#define COR_LEV 0x40 +#define COR_IRQEN 0x04 +#define COR_BLREN 0x01 +#define COR_FUNEN 0x01 + +#define PCICIA_FCSR (2 / 2) +#define PCICIA_PRR (4 / 2) +#define PCICIA_SCR (6 / 2) +#define PCICIA_ESR (8 / 2) + +#define PCM_MEMOFF 0x0000 +#define F0_MEMOFF 0x1000 +#define F1_MEMOFF 0x2000 +#define F2_MEMOFF 0x3000 +#define F3_MEMOFF 0x4000 + +/* Memory base in the function fcr's */ +#define MEM_ADDR0 (0x728 / 2) +#define MEM_ADDR1 (0x72a / 2) +#define MEM_ADDR2 (0x72c / 2) + +/* PCMCIA base plus Srom access in fcr0: */ +#define PCMCIA_ADDR0 (0x072e / 2) +#define PCMCIA_ADDR1 (0x0730 / 2) +#define PCMCIA_ADDR2 (0x0732 / 2) + +#define MEM_SEG (0x0734 / 2) +#define SROM_CS (0x0736 / 2) +#define SROM_DATAL (0x0738 / 2) +#define SROM_DATAH (0x073a / 2) +#define SROM_ADDRL (0x073c / 2) +#define SROM_ADDRH (0x073e / 2) +#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ +#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ + +/* Values for srom_cs: */ +#define SROM_IDLE 0 +#define SROM_WRITE 1 +#define SROM_READ 2 +#define SROM_WEN 4 +#define SROM_WDS 7 +#define SROM_DONE 8 + +/* Fields in srom_info: */ +#define SRI_SZ_MASK 0x03 +#define SRI_BLANK 0x04 +#define SRI_OTP 0x80 + +#if !defined(ESTA_POSTMOGRIFY_REMOVAL) +/* CIS stuff */ + +/* The CIS stops where the FCRs start */ +#define CIS_SIZE PCMCIA_FCR + +/* CIS tuple length field max */ +#define CIS_TUPLE_LEN_MAX 0xff + +/* Standard tuples we know about */ + +#define CISTPL_NULL 0x00 +#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */ +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */ +#define CISTPL_FUNCID 0x21 /* Function identification */ +#define CISTPL_FUNCE 0x22 /* Function extensions */ +#define CISTPL_CFTABLE 0x1b /* Config table entry */ +#define CISTPL_END 0xff /* End of the CIS tuple chain */ + +/* Function identifier provides context for the function extentions tuple */ +#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */ + +/* Function extensions for LANs (assumed for extensions other than SDIO) */ +#define LAN_TECH 1 /* Technology type */ +#define LAN_SPEED 2 /* Raw bit rate */ +#define LAN_MEDIA 3 /* Transmission media */ +#define LAN_NID 4 /* Node identification (aka MAC addr) */ +#define LAN_CONN 5 /* Connector standard */ + +/* CFTable */ +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */ +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */ +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */ + +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll + * take one for HNBU, and use "extensions" (a la FUNCE) within it. + */ + +#define CISTPL_BRCM_HNBU 0x80 + +/* Subtypes of BRCM_HNBU: */ + +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */ +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */ +#define HNBU_BOARDREV 0x02 /* One byte board revision */ +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1) + * or 9 (sromrev > 1) bytes + */ +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */ +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */ +#define HNBU_AA 0x06 /* Antennas available */ +#define HNBU_AG 0x07 /* Antenna gain */ +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */ +#define HNBU_LEDS 0x09 /* LED set */ +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl) + * in rev 2 + */ +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */ +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */ +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */ +#define HNBU_PAPARMS5G 0x0e /* 5G PA params */ +#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */ +#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */ +#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch, + * 2 bytes, rev 3. + */ +#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch, + * 2 bytes, rev 3. + */ +#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */ +#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */ +#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */ +#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */ +#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */ +#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */ +#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */ +#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */ +#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ +#define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */ +#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ +#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */ +#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */ +#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */ +#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */ +#define HNBU_REGREV 0x22 /* 1 byte; */ +#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */ +#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */ +#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */ +#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */ +#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */ +#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */ +#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */ +#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */ +#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */ +#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */ +#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */ +#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */ +#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */ + +#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */ +#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */ +#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */ +#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */ +#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */ +#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */ +#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */ +#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */ + +#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */ +#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8 + * plus extra info appended. + */ +#define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */ +#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */ +#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */ +#endif /* !defined(ESTA_POSTMOGRIFY_REMOVAL) */ + +/* sbtmstatelow */ +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */ + +/* sbtmstatehigh */ +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ + +#endif /* _SBPCMCIA_H */ diff --git a/drivers/staging/brcm80211/util/sbsocram.h b/drivers/staging/brcm80211/util/sbsocram.h new file mode 100644 index 000000000000..0cfe9852b27f --- /dev/null +++ b/drivers/staging/brcm80211/util/sbsocram.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2010 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SBSOCRAM_H +#define _SBSOCRAM_H + +#ifndef _LANGUAGE_ASSEMBLY + +/* cpp contortions to concatenate w/arg prescan */ +#ifndef PAD +#define _PADLINE(line) pad ## line +#define _XSTR(line) _PADLINE(line) +#define PAD _XSTR(__LINE__) +#endif /* PAD */ + +/* Memcsocram core registers */ +typedef volatile struct sbsocramregs { + u32 coreinfo; + u32 bwalloc; + u32 extracoreinfo; + u32 biststat; + u32 bankidx; + u32 standbyctrl; + + u32 errlogstatus; /* rev 6 */ + u32 errlogaddr; /* rev 6 */ + /* used for patching rev 3 & 5 */ + u32 cambankidx; + u32 cambankstandbyctrl; + u32 cambankpatchctrl; + u32 cambankpatchtblbaseaddr; + u32 cambankcmdreg; + u32 cambankdatareg; + u32 cambankmaskreg; + u32 PAD[1]; + u32 bankinfo; /* corev 8 */ + u32 PAD[15]; + u32 extmemconfig; + u32 extmemparitycsr; + u32 extmemparityerrdata; + u32 extmemparityerrcnt; + u32 extmemwrctrlandsize; + u32 PAD[84]; + u32 workaround; + u32 pwrctl; /* corerev >= 2 */ +} sbsocramregs_t; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* Register offsets */ +#define SR_COREINFO 0x00 +#define SR_BWALLOC 0x04 +#define SR_BISTSTAT 0x0c +#define SR_BANKINDEX 0x10 +#define SR_BANKSTBYCTL 0x14 +#define SR_PWRCTL 0x1e8 + +/* Coreinfo register */ +#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ +#define SRCI_PT_SHIFT 16 +/* port types : SRCI_PT__ */ +#define SRCI_PT_OCP_OCP 0 +#define SRCI_PT_AXI_OCP 1 +#define SRCI_PT_ARM7AHB_OCP 2 +#define SRCI_PT_CM3AHB_OCP 3 +#define SRCI_PT_AXI_AXI 4 +#define SRCI_PT_AHB_AXI 5 +/* corerev >= 3 */ +#define SRCI_LSS_MASK 0x00f00000 +#define SRCI_LSS_SHIFT 20 +#define SRCI_LRS_MASK 0x0f000000 +#define SRCI_LRS_SHIFT 24 + +/* In corerev 0, the memory size is 2 to the power of the + * base plus 16 plus to the contents of the memsize field plus 1. + */ +#define SRCI_MS0_MASK 0xf +#define SR_MS0_BASE 16 + +/* + * In corerev 1 the bank size is 2 ^ the bank size field plus 14, + * the memory size is number of banks times bank size. + * The same applies to rom size. + */ +#define SRCI_ROMNB_MASK 0xf000 +#define SRCI_ROMNB_SHIFT 12 +#define SRCI_ROMBSZ_MASK 0xf00 +#define SRCI_ROMBSZ_SHIFT 8 +#define SRCI_SRNB_MASK 0xf0 +#define SRCI_SRNB_SHIFT 4 +#define SRCI_SRBSZ_MASK 0xf +#define SRCI_SRBSZ_SHIFT 0 + +#define SR_BSZ_BASE 14 + +/* Standby control register */ +#define SRSC_SBYOVR_MASK 0x80000000 +#define SRSC_SBYOVR_SHIFT 31 +#define SRSC_SBYOVRVAL_MASK 0x60000000 +#define SRSC_SBYOVRVAL_SHIFT 29 +#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ +#define SRSC_SBYEN_SHIFT 24 + +/* Power control register */ +#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ +#define SRPC_PMU_STBYDIS_SHIFT 4 +#define SRPC_STBYOVRVAL_MASK 0x00000008 +#define SRPC_STBYOVRVAL_SHIFT 3 +#define SRPC_STBYOVR_MASK 0x00000007 +#define SRPC_STBYOVR_SHIFT 0 + +/* Extra core capability register */ +#define SRECC_NUM_BANKS_MASK 0x000000F0 +#define SRECC_NUM_BANKS_SHIFT 4 +#define SRECC_BANKSIZE_MASK 0x0000000F +#define SRECC_BANKSIZE_SHIFT 0 + +#define SRECC_BANKSIZE(value) (1 << (value)) + +/* CAM bank patch control */ +#define SRCBPC_PATCHENABLE 0x80000000 + +#define SRP_ADDRESS 0x0001FFFC +#define SRP_VALID 0x8000 + +/* CAM bank command reg */ +#define SRCMD_WRITE 0x00020000 +#define SRCMD_READ 0x00010000 +#define SRCMD_DONE 0x80000000 + +#define SRCMD_DONE_DLY 1000 + +/* bankidx and bankinfo reg defines corerev >= 8 */ +#define SOCRAM_BANKINFO_SZMASK 0x3f +#define SOCRAM_BANKIDX_ROM_MASK 0x100 + +#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 +/* socram bankinfo memtype */ +#define SOCRAM_MEMTYPE_RAM 0 +#define SOCRAM_MEMTYPE_R0M 1 +#define SOCRAM_MEMTYPE_DEVRAM 2 + +#define SOCRAM_BANKINFO_REG 0x40 +#define SOCRAM_BANKIDX_REG 0x10 +#define SOCRAM_BANKINFO_STDBY_MASK 0x400 +#define SOCRAM_BANKINFO_STDBY_TIMER 0x800 + +/* bankinfo rev >= 10 */ +#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 +#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 +#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 +#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 + +/* extracoreinfo register */ +#define SOCRAM_DEVRAMBANK_MASK 0xF000 +#define SOCRAM_DEVRAMBANK_SHIFT 12 + +/* bank info to calculate bank size */ +#define SOCRAM_BANKINFO_SZBASE 8192 +#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ + +#endif /* _SBSOCRAM_H */