From: jassi brar Date: Tue, 1 Sep 2009 02:35:08 +0000 (+0900) Subject: ASoC: Debugged improper setting of PLL fields in WM8580 driver X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5c0d38c9478e79ab7deb1b470dd181d2308a608e;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git ASoC: Debugged improper setting of PLL fields in WM8580 driver Bug was caught while trying to use WM8580 as I2S master on SMDK. Symptoms were lesser LRCLK read by CRO(41.02 instead of 44.1 KHz) Solved by referring to WM8580A manual and setting mask value correctly and making the code to not touch 'reserved' bits of PLL4 register. Signed-off-by: Jassi Signed-off-by: Mark Brown --- diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index d5473473a1e3..6bded8c78150 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -458,12 +458,12 @@ static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, return 0; snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); - snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff); + snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff); snd_soc_write(codec, WM8580_PLLA3 + offset, (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); reg = snd_soc_read(codec, WM8580_PLLA4 + offset); - reg &= ~0x3f; + reg &= ~0x1b; reg |= pll_div.prescale | pll_div.postscale << 1 | pll_div.freqmode << 3;