From: Greg Ungerer Date: Tue, 2 Nov 2010 02:05:29 +0000 (+1000) Subject: m68knommu: make Coldfire 548x support more generic X-Git-Tag: MMI-PSA29.97-13-9~20978^2~21 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5b2e6555ac3eb58a4e5eb5020471df08f0c42c01;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git m68knommu: make Coldfire 548x support more generic The ColdFire 547x family of processors is very similar to the ColdFire 548x series. Almost all of the support for them is the same. Make the code supporting the 548x more gneric, so it will be capable of supporting both families. For the most part this is a renaming excerise to make the support code more obviously apply to both families. Signed-off-by: Greg Ungerer --- diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 29f76204ce1d..9246392e1372 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -5,7 +5,7 @@ * (C) Copyright 2000-2004, Greg Ungerer */ #include -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) #include #endif diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 3b0a34d0fe33..213028cbe110 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -32,7 +32,7 @@ */ #define MCF_MBAR 0x10000000 #define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCF_IPSBAR MCF_MBAR #elif defined(CONFIG_M520x) #define MCF_IPSBAR 0xFC000000 diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 1b57adbafad5..c64c7b74cf86 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -37,7 +37,7 @@ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M548x) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) /* These parts have GPIO organized by 8 bit ports */ diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h deleted file mode 100644 index c8ef158a1c4e..000000000000 --- a/arch/m68k/include/asm/m548xgpt.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * File: m548xgpt.h - * Purpose: Register and bit definitions for the MCF548X - * - * Notes: - * - */ - -#ifndef m548xgpt_h -#define m548xgpt_h - -/********************************************************************* -* -* General Purpose Timers (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GMS0 0x000800 -#define MCF_GPT_GCIR0 0x000804 -#define MCF_GPT_GPWM0 0x000808 -#define MCF_GPT_GSR0 0x00080C -#define MCF_GPT_GMS1 0x000810 -#define MCF_GPT_GCIR1 0x000814 -#define MCF_GPT_GPWM1 0x000818 -#define MCF_GPT_GSR1 0x00081C -#define MCF_GPT_GMS2 0x000820 -#define MCF_GPT_GCIR2 0x000824 -#define MCF_GPT_GPWM2 0x000828 -#define MCF_GPT_GSR2 0x00082C -#define MCF_GPT_GMS3 0x000830 -#define MCF_GPT_GCIR3 0x000834 -#define MCF_GPT_GPWM3 0x000838 -#define MCF_GPT_GSR3 0x00083C -#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) -#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) -#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) -#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) - -/* Bit definitions and macros for MCF_GPT_GMS */ -#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF_GPT_GMS_IEN (0x00000100) -#define MCF_GPT_GMS_OD (0x00000200) -#define MCF_GPT_GMS_SC (0x00000400) -#define MCF_GPT_GMS_CE (0x00001000) -#define MCF_GPT_GMS_WDEN (0x00008000) -#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF_GPT_GMS_ICT_ANY (0x00000000) -#define MCF_GPT_GMS_ICT_RISE (0x00010000) -#define MCF_GPT_GMS_ICT_FALL (0x00020000) -#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF_GPT_GMS_TMS_PWM (0x00000003) -#define MCF_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF_GPT_GCIR */ -#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GPWM */ -#define MCF_GPT_GPWM_LOAD (0x00000001) -#define MCF_GPT_GPWM_PWMOP (0x00000100) -#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GSR */ -#define MCF_GPT_GSR_CAPT (0x00000001) -#define MCF_GPT_GSR_COMP (0x00000002) -#define MCF_GPT_GSR_PWMP (0x00000004) -#define MCF_GPT_GSR_TEXP (0x00000008) -#define MCF_GPT_GSR_PIN (0x00000100) -#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* m548xgpt_h */ diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h deleted file mode 100644 index 149135ef30d2..000000000000 --- a/arch/m68k/include/asm/m548xsim.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * m548xsim.h -- ColdFire 547x/548x System Integration Unit support. - */ - -#ifndef m548xsim_h -#define m548xsim_h - -#define MCFINT_VECBASE 64 - -/* - * Interrupt Controller Registers - */ -#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -/* - * Define system peripheral IRQ usage. - */ -#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ -#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ - -/* - * Generic GPIO support - */ -#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ -#define MCFGPIO_IRQ_MAX -1 -#define MCFGPIO_IRQ_VECBASE -1 - -/* - * Some PSC related definitions - */ -#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) -#define MCF_PAR_SDA (0x0008) -#define MCF_PAR_SCL (0x0004) -#define MCF_PAR_PSC_TXD (0x04) -#define MCF_PAR_PSC_RXD (0x08) -#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) -#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) -#define MCF_PAR_PSC_CTS_GPIO (0x00) -#define MCF_PAR_PSC_CTS_BCLK (0x80) -#define MCF_PAR_PSC_CTS_CTS (0xC0) -#define MCF_PAR_PSC_RTS_GPIO (0x00) -#define MCF_PAR_PSC_RTS_FSYNC (0x20) -#define MCF_PAR_PSC_RTS_RTS (0x30) -#define MCF_PAR_PSC_CANRX (0x40) - -#endif /* m548xsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 7d28da4d622a..76d64906aa62 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -45,7 +45,7 @@ #define ICACHE_SIZE 0x4000 /* instruction - 16k */ #define DCACHE_SIZE 0x2000 /* data - 8k */ -#elif defined(CONFIG_M548x) +#elif defined(CONFIG_M54xx) #define ICACHE_SIZE 0x8000 /* instruction - 32k */ #define DCACHE_SIZE 0x8000 /* data - 32k */ diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h new file mode 100644 index 000000000000..47ae5cfec66b --- /dev/null +++ b/arch/m68k/include/asm/m54xxgpt.h @@ -0,0 +1,88 @@ +/* + * File: m54xxgpt.h + * Purpose: Register and bit definitions for the MCF54XX + * + * Notes: + * + */ + +#ifndef m54xxgpt_h +#define m54xxgpt_h + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT_GMS0 0x000800 +#define MCF_GPT_GCIR0 0x000804 +#define MCF_GPT_GPWM0 0x000808 +#define MCF_GPT_GSR0 0x00080C +#define MCF_GPT_GMS1 0x000810 +#define MCF_GPT_GCIR1 0x000814 +#define MCF_GPT_GPWM1 0x000818 +#define MCF_GPT_GSR1 0x00081C +#define MCF_GPT_GMS2 0x000820 +#define MCF_GPT_GCIR2 0x000824 +#define MCF_GPT_GPWM2 0x000828 +#define MCF_GPT_GSR2 0x00082C +#define MCF_GPT_GMS3 0x000830 +#define MCF_GPT_GCIR3 0x000834 +#define MCF_GPT_GPWM3 0x000838 +#define MCF_GPT_GSR3 0x00083C +#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) +#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) +#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) +#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) +#define MCF_GPT_GMS_IEN (0x00000100) +#define MCF_GPT_GMS_OD (0x00000200) +#define MCF_GPT_GMS_SC (0x00000400) +#define MCF_GPT_GMS_CE (0x00001000) +#define MCF_GPT_GMS_WDEN (0x00008000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) +#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) +#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) +#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) +#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) +#define MCF_GPT_GMS_ICT_ANY (0x00000000) +#define MCF_GPT_GMS_ICT_RISE (0x00010000) +#define MCF_GPT_GMS_ICT_FALL (0x00020000) +#define MCF_GPT_GMS_ICT_PULSE (0x00030000) +#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) +#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) +#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) +#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) +#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) +#define MCF_GPT_GMS_TMS_PWM (0x00000003) +#define MCF_GPT_GMS_TMS_GPIO (0x00000004) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x00000001) +#define MCF_GPT_GPWM_PWMOP (0x00000100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x00000001) +#define MCF_GPT_GSR_COMP (0x00000002) +#define MCF_GPT_GSR_PWMP (0x00000004) +#define MCF_GPT_GSR_TEXP (0x00000008) +#define MCF_GPT_GSR_PIN (0x00000100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) + +/********************************************************************/ + +#endif /* m54xxgpt_h */ diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h new file mode 100644 index 000000000000..c46826c900b3 --- /dev/null +++ b/arch/m68k/include/asm/m54xxsim.h @@ -0,0 +1,55 @@ +/* + * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. + */ + +#ifndef m54xxsim_h +#define m54xxsim_h + +#define MCFINT_VECBASE 64 + +/* + * Interrupt Controller Registers + */ +#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +/* + * Define system peripheral IRQ usage. + */ +#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ +#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ + +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ +#define MCFGPIO_IRQ_MAX -1 +#define MCFGPIO_IRQ_VECBASE -1 + +/* + * Some PSC related definitions + */ +#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) +#define MCF_PAR_SDA (0x0008) +#define MCF_PAR_SCL (0x0004) +#define MCF_PAR_PSC_TXD (0x04) +#define MCF_PAR_PSC_RXD (0x08) +#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) +#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) +#define MCF_PAR_PSC_CTS_GPIO (0x00) +#define MCF_PAR_PSC_CTS_BCLK (0x80) +#define MCF_PAR_PSC_CTS_CTS (0xC0) +#define MCF_PAR_PSC_RTS_GPIO (0x00) +#define MCF_PAR_PSC_RTS_FSYNC (0x20) +#define MCF_PAR_PSC_RTS_RTS (0x30) +#define MCF_PAR_PSC_CANRX (0x40) + +#endif /* m54xxsim_h */ diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index 7acb406d601b..1b66018461b8 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -107,7 +107,7 @@ .endm #endif /* CONFIG_M532x */ -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) #include @@ -131,7 +131,7 @@ movec %d0,%CACR nop .endm -#endif /* CONFIG_M5407 || CONFIG_M548x */ +#endif /* CONFIG_M5407 || CONFIG_M54xx */ #if defined(CONFIG_M520x) .macro CACHE_ENABLE diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index 6901fd68165b..ebd0304054ad 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h @@ -41,8 +41,8 @@ #elif defined(CONFIG_M5407) #include #include -#elif defined(CONFIG_M548x) -#include +#elif defined(CONFIG_M54xx) +#include #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index db72e2b889ca..c67dacad7c1c 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -47,11 +47,11 @@ #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#elif defined(CONFIG_M548x) -#define MCFUART_BASE1 0x8600 /* on M548x */ -#define MCFUART_BASE2 0x8700 /* on M548x */ -#define MCFUART_BASE3 0x8800 /* on M548x */ -#define MCFUART_BASE4 0x8900 /* on M548x */ +#elif defined(CONFIG_M54xx) +#define MCFUART_BASE1 0x8600 /* on M54xx */ +#define MCFUART_BASE2 0x8700 /* on M54xx */ +#define MCFUART_BASE3 0x8800 /* on M54xx */ +#define MCFUART_BASE4 0x8900 /* on M54xx */ #endif @@ -217,7 +217,7 @@ struct mcf_platform_uart { #define MCFUART_URF_RXS 0xc0 /* Receiver status */ #endif -#if defined(CONFIG_M548x) +#if defined(CONFIG_M54xx) #define MCFUART_TXFIFOSIZE 512 #elif defined(CONFIG_M5272) #define MCFUART_TXFIFOSIZE 25 diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index fa9f746cf4ae..060f142a1e20 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -181,9 +181,14 @@ config M527x select GENERIC_CLOCKEVENTS default y +config M54xx + bool + depends on M548x + default y + config COLDFIRE bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x) + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M54xx) select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB default y diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile index 026ef16fa68e..0a0b1ddee4b9 100644 --- a/arch/m68knommu/Makefile +++ b/arch/m68knommu/Makefile @@ -25,7 +25,7 @@ platform-$(CONFIG_M528x) := 528x platform-$(CONFIG_M5307) := 5307 platform-$(CONFIG_M532x) := 532x platform-$(CONFIG_M5407) := 5407 -platform-$(CONFIG_M548x) := 548x +platform-$(CONFIG_M54xx) := 54xx PLATFORM := $(platform-y) board-$(CONFIG_PILOT) := pilot @@ -74,7 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire cpuclass-$(CONFIG_M5307) := coldfire cpuclass-$(CONFIG_M532x) := coldfire cpuclass-$(CONFIG_M5407) := coldfire -cpuclass-$(CONFIG_M548x) := coldfire +cpuclass-$(CONFIG_M54xx) := coldfire cpuclass-$(CONFIG_M68328) := 68328 cpuclass-$(CONFIG_M68EZ328) := 68328 cpuclass-$(CONFIG_M68VZ328) := 68328 @@ -102,7 +102,7 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) -cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200) +cflags-$(CONFIG_M54xx) := $(call cc-option,-m5407,-m5200) cflags-$(CONFIG_M68328) := -m68000 cflags-$(CONFIG_M68EZ328) := -m68000 cflags-$(CONFIG_M68VZ328) := -m68000 diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile deleted file mode 100644 index e6035e7a2d3f..000000000000 --- a/arch/m68knommu/platform/548x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT -# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o - diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c deleted file mode 100644 index 9888846bd1cf..000000000000 --- a/arch/m68knommu/platform/548x/config.c +++ /dev/null @@ -1,115 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/548x/config.c - * - * Copyright (C) 2010, Philippe De Muyter - */ - -/***************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/***************************************************************************/ - -static struct mcf_platform_uart m548x_uart_platform[] = { - { - .mapbase = MCF_MBAR + MCFUART_BASE1, - .irq = 64 + 35, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE2, - .irq = 64 + 34, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE3, - .irq = 64 + 33, - }, - { - .mapbase = MCF_MBAR + MCFUART_BASE4, - .irq = 64 + 32, - }, -}; - -static struct platform_device m548x_uart = { - .name = "mcfuart", - .id = 0, - .dev.platform_data = m548x_uart_platform, -}; - -static struct platform_device *m548x_devices[] __initdata = { - &m548x_uart, -}; - - -/***************************************************************************/ - -static void __init m548x_uart_init_line(int line, int irq) -{ - int rts_cts; - - /* enable io pins */ - switch (line) { - case 0: - rts_cts = 0; break; - case 1: - rts_cts = MCF_PAR_PSC_RTS_RTS; break; - case 2: - rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break; - case 3: - rts_cts = 0; break; - } - __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD, - MCF_MBAR + MCF_PAR_PSC(line)); -} - -static void __init m548x_uarts_init(void) -{ - const int nrlines = ARRAY_SIZE(m548x_uart_platform); - int line; - - for (line = 0; (line < nrlines); line++) - m548x_uart_init_line(line, m548x_uart_platform[line].irq); -} - -/***************************************************************************/ - -static void mcf548x_reset(void) -{ - /* disable interrupts and enable the watchdog */ - asm("movew #0x2700, %sr\n"); - __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); - __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); - __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), - MCF_MBAR + MCF_GPT_GMS0); -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_reset = mcf548x_reset; - m548x_uarts_init(); -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - - platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile new file mode 100644 index 000000000000..e6035e7a2d3f --- /dev/null +++ b/arch/m68knommu/platform/54xx/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the m68knommu linux kernel. +# + +# +# If you want to play with the HW breakpoints then you will +# need to add define this, which will give you a stack backtrace +# on the console port whenever a DBG interrupt occurs. You have to +# set up you HW breakpoints to trigger a DBG interrupt: +# +# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT +# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT +# + +asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 + +obj-y := config.o + diff --git a/arch/m68knommu/platform/54xx/config.c b/arch/m68knommu/platform/54xx/config.c new file mode 100644 index 000000000000..78130984db95 --- /dev/null +++ b/arch/m68knommu/platform/54xx/config.c @@ -0,0 +1,115 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/54xx/config.c + * + * Copyright (C) 2010, Philippe De Muyter + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +static struct mcf_platform_uart m54xx_uart_platform[] = { + { + .mapbase = MCF_MBAR + MCFUART_BASE1, + .irq = 64 + 35, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE2, + .irq = 64 + 34, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE3, + .irq = 64 + 33, + }, + { + .mapbase = MCF_MBAR + MCFUART_BASE4, + .irq = 64 + 32, + }, +}; + +static struct platform_device m54xx_uart = { + .name = "mcfuart", + .id = 0, + .dev.platform_data = m54xx_uart_platform, +}; + +static struct platform_device *m54xx_devices[] __initdata = { + &m54xx_uart, +}; + + +/***************************************************************************/ + +static void __init m54xx_uart_init_line(int line, int irq) +{ + int rts_cts; + + /* enable io pins */ + switch (line) { + case 0: + rts_cts = 0; break; + case 1: + rts_cts = MCF_PAR_PSC_RTS_RTS; break; + case 2: + rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break; + case 3: + rts_cts = 0; break; + } + __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD, + MCF_MBAR + MCF_PAR_PSC(line)); +} + +static void __init m54xx_uarts_init(void) +{ + const int nrlines = ARRAY_SIZE(m54xx_uart_platform); + int line; + + for (line = 0; (line < nrlines); line++) + m54xx_uart_init_line(line, m54xx_uart_platform[line].irq); +} + +/***************************************************************************/ + +static void mcf54xx_reset(void) +{ + /* disable interrupts and enable the watchdog */ + asm("movew #0x2700, %sr\n"); + __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); + __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); + __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), + MCF_MBAR + MCF_GPT_GMS0); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_reset = mcf54xx_reset; + m54xx_uarts_init(); +} + +/***************************************************************************/ + +static int __init init_BSP(void) +{ + + platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices)); + return 0; +} + +arch_initcall(init_BSP); + +/***************************************************************************/ diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 45f501fa4525..53a27e1a7904 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o intc.o obj-$(CONFIG_M532x) += timers.o intc-simr.o obj-$(CONFIG_M5407) += timers.o intc.o -obj-$(CONFIG_M548x) += sltimers.o intc-2.o +obj-$(CONFIG_M54xx) += sltimers.o intc-2.o obj-y += pinmux.o gpio.o extra-y := head.o