From: Dave Jiang Date: Tue, 19 May 2015 20:59:34 +0000 (-0400) Subject: NTB: Enable link for Intel root port mode in probe X-Git-Tag: MMI-PSA29.97-13-9~9769^2~17 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5ae0beb6bcb781ba0439618a4883fdb243916f46;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git NTB: Enable link for Intel root port mode in probe Link training should be enabled in the driver probe for root port mode. We should not have to wait for transport to be loaded for this to happen. Otherwise the ntb device will not show up on the transparent bridge side of the link. Signed-off-by: Dave Jiang Signed-off-by: Jon Mason --- diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 686091756ba4..3810ad11cfdf 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -1317,6 +1317,9 @@ static int snb_poll_link(struct intel_ntb_dev *ndev) static int snb_link_is_up(struct intel_ntb_dev *ndev) { + if (ndev->ntb.topo == NTB_TOPO_SEC) + return 1; + return NTB_LNK_STA_ACTIVE(ndev->lnk_sta); } @@ -1613,6 +1616,7 @@ static int snb_setup_b2b_mw(struct intel_ntb_dev *ndev, static int snb_init_ntb(struct intel_ntb_dev *ndev) { int rc; + u32 ntb_ctl; if (ndev->bar4_split) ndev->mw_count = HSX_SPLIT_BAR_MW_COUNT; @@ -1629,6 +1633,12 @@ static int snb_init_ntb(struct intel_ntb_dev *ndev) dev_err(ndev_dev(ndev), "NTB Primary config disabled\n"); return -EINVAL; } + + /* enable link to allow secondary side device to appear */ + ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); + ntb_ctl &= ~NTB_CTL_DISABLE; + iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); + /* use half the spads for the peer */ ndev->spad_count >>= 1; ndev->self_reg = &snb_pri_reg;