From: Yen Lin <yelin@nvidia.com>
Date: Wed, 6 Mar 2013 11:47:24 +0000 (+0000)
Subject: clk: tegra: Fix periph_clk_to_bit macro
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5a88b0d10f198ddd5f988f40d34b52f34c87a5c6;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

clk: tegra: Fix periph_clk_to_bit macro

The parameter name should be "gate", not "periph".  This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.

Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7b..d87e1cece9fa 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 #define write_rst_clr(val, gate) \
 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
-#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
 
 /* Peripheral gate clock ops */
 static int clk_periph_is_enabled(struct clk_hw *hw)