From: Andrew Bresticker Date: Wed, 25 Sep 2013 21:12:52 +0000 (-0700) Subject: ARM: dts: exynos5420: add input clocks to audss clock controller X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=59d711e9ddd2f68822a2a99fc939e11a9288b73e;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git ARM: dts: exynos5420: add input clocks to audss clock controller Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in) for the AudioSS clock controller. Signed-off-by: Andrew Bresticker Acked-by: Mike Turquette Acked-by: Kukjin Kim Signed-off-by: Tomasz Figa --- diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 09aa06cb3d3a..25a1120d88a5 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -76,8 +76,8 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 148>; - clock-names = "sclk_audio"; + clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; codec@11000000 {