From: Michal Simek Date: Mon, 26 Apr 2010 11:43:23 +0000 (+0200) Subject: microblaze: Define correct L1_CACHE_SHIFT value X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=598acab44dcbda0e300d9d080e81566334138e7d;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git microblaze: Define correct L1_CACHE_SHIFT value Microblaze cacheline length is configurable and current cpu uses two cacheline length 4 and 8. We are taking conservative maximum value to be sure that cacheline alignment is satisfied for all cases. Here is the calculation for cacheline lenght 8 32bit=4Byte values which is corresponding with SHIFT 5. Signed-off-by: Michal Simek --- diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h index e52210891d78..4efe96a036f7 100644 --- a/arch/microblaze/include/asm/cache.h +++ b/arch/microblaze/include/asm/cache.h @@ -15,7 +15,7 @@ #include -#define L1_CACHE_SHIFT 2 +#define L1_CACHE_SHIFT 5 /* word-granular cache in microblaze */ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)