From: Andreea-Cristina Bernat <bernat.ada@gmail.com>
Date: Mon, 10 Mar 2014 10:31:31 +0000 (+0200)
Subject: /drivers/staging/sbe2t3e3: Fixed left brace to be on the previous line
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=58c991d5380c609b542efcdeeec1e5b7348abe9e;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

/drivers/staging/sbe2t3e3: Fixed left brace to be on the previous line

This patch solves the error: that open brace { should be on the previous line.

Signed-off-by: Andreea-Cristina Bernat <bernat.ada@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
---

diff --git a/drivers/staging/sbe-2t3e3/maps.c b/drivers/staging/sbe-2t3e3/maps.c
index 7084fbe7b794..e5494502cde1 100644
--- a/drivers/staging/sbe-2t3e3/maps.c
+++ b/drivers/staging/sbe-2t3e3/maps.c
@@ -13,8 +13,7 @@
 #include <linux/kernel.h>
 #include "2t3e3.h"
 
-const u32 cpld_reg_map[][2] =
-{
+const u32 cpld_reg_map[][2] = {
 	{ 0x0000, 0x0080 }, /* 0 - Port Control Register A (PCRA) */
 	{ 0x0004, 0x0084 }, /* 1 - Port Control Register B (PCRB) */
 	{ 0x0008, 0x0088 }, /* 2 - LCV Count Register (PLCR) */
@@ -35,8 +34,7 @@ const u32 cpld_reg_map[][2] =
 	{ 0x0070, 0x00f0 }, /* 17 - Port Bandwidth Stop (PBWL) */
 };
 
-const u32 cpld_val_map[][2] =
-{
+const u32 cpld_val_map[][2] = {
 	{ 0x01, 0x02 }, /* LIU1 / LIU2 select for Serial Chip Select */
 	{ 0x04, 0x08 }, /* DAC1 / DAC2 select for Serial Chip Select */
 	{ 0x00, 0x04 }, /* LOOP1 / LOOP2 - select of loop timing source */
@@ -94,8 +92,7 @@ const u32 t3e3_framer_reg_map[] = {
 	0x81  /* 47 - LINE_INTERFACE_SCAN */
 };
 
-const u32 t3e3_liu_reg_map[] =
-{
+const u32 t3e3_liu_reg_map[] = {
 	0x00, /* REG0 */
 	0x01, /* REG1 */
 	0x02, /* REG2 */