From: Jeff Kirsher Date: Sat, 28 Dec 2013 12:28:18 +0000 (-0800) Subject: pci_regs.h: Add PCI bus link speed and width defines X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=55fdbfe7beb68c71060a27965a72f7eed09fa81d;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git pci_regs.h: Add PCI bus link speed and width defines Add missing PCI bus link speed 8.0 GT/s and bus link widths of x1, x2, x4 and x8. CC: CC: Bjorn Helgaas Signed-off-by: Jeff Kirsher Acked-by: Bjorn Helgaas --- diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4a98e85438a7..c870c2a71d65 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -489,7 +489,12 @@ #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ +#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ +#define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ +#define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */