From: Larry Finger Date: Thu, 25 Aug 2011 16:48:16 +0000 (-0500) Subject: staging: rtl8192e: Cleanup checkpatch -f warnings and errors - Part IV X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=547d0c34b71b1ced82d9652c78143bbcbe08ccdf;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git staging: rtl8192e: Cleanup checkpatch -f warnings and errors - Part IV Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rtl8192e/r8192E_phy.c b/drivers/staging/rtl8192e/r8192E_phy.c index 9c1d16b5fb69..96ccbd5b25d1 100644 --- a/drivers/staging/rtl8192e/r8192E_phy.c +++ b/drivers/staging/rtl8192e/r8192E_phy.c @@ -47,26 +47,29 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = { /*************************Define local function prototype**********************/ -static u32 phy_FwRFSerialRead(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset); -static void phy_FwRFSerialWrite(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data); +static u32 phy_FwRFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset); +static void phy_FwRFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset, u32 Data); u32 rtl8192_CalculateBitShift(u32 dwBitMask) { u32 i; - for (i=0; i<=31; i++) - { - if (((dwBitMask>>i)&0x1) == 1) + for (i = 0; i <= 31; i++) { + if (((dwBitMask >> i) & 0x1) == 1) break; } return i; } -u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) + +u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) { u8 ret = 1; struct r8192_priv *priv = rtllib_priv(dev); if (priv->rf_type == RF_2T4R) ret = 0; - else if (priv->rf_type == RF_1T2R) - { + else if (priv->rf_type == RF_1T2R) { if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) ret = 1; else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) @@ -74,22 +77,25 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) } return ret; } -void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) + +void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, + u32 dwData) { u32 OriginalValue, BitShift, NewValue; - if (dwBitMask!= bMaskDWord) - { + if (dwBitMask != bMaskDWord) { OriginalValue = read_nic_dword(dev, dwRegAddr); BitShift = rtl8192_CalculateBitShift(dwBitMask); - NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); + NewValue = (((OriginalValue) & (~dwBitMask)) | + (dwData << BitShift)); write_nic_dword(dev, dwRegAddr, NewValue); - }else + } else write_nic_dword(dev, dwRegAddr, dwData); return; } -u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) + +u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) { u32 Ret = 0, OriginalValue, BitShift; @@ -97,60 +103,55 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) BitShift = rtl8192_CalculateBitShift(dwBitMask); Ret = (OriginalValue & dwBitMask) >> BitShift; - return (Ret); + return Ret; } -u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset) +u32 rtl8192_phy_RFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) { struct r8192_priv *priv = rtllib_priv(dev); u32 ret = 0; u32 NewOffset = 0; - struct bb_reg_definition* pPhyReg = &priv->PHYRegDef[eRFPath]; + struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; Offset &= 0x3f; - if (priv->rf_chip == RF_8256) - { + if (priv->rf_chip == RF_8256) { rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); - if (Offset >= 31) - { + if (Offset >= 31) { priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); - NewOffset = Offset -30; - } - else if (Offset >= 16) - { + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); + NewOffset = Offset - 30; + } else if (Offset >= 16) { priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath]<<16)); NewOffset = Offset - 15; - } - else + } else NewOffset = Offset; - } - else - { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); + } else { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need" + " to be 8256\n"); NewOffset = Offset; } - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, + NewOffset); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + mdelay(1); - msleep(1); - - ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, + bLSSIReadBackData); - - if (priv->rf_chip == RF_8256) - { + if (priv->rf_chip == RF_8256) { priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -160,36 +161,36 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPat } -void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) +void rtl8192_phy_RFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset, + u32 Data) { struct r8192_priv *priv = rtllib_priv(dev); u32 DataAndAddr = 0, NewOffset = 0; struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; Offset &= 0x3f; - if (priv->rf_chip == RF_8256) - { + if (priv->rf_chip == RF_8256) { rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); - if (Offset >= 31) - { + if (Offset >= 31) { priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); NewOffset = Offset - 30; - } - else if (Offset >= 16) - { + } else if (Offset >= 16) { priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); NewOffset = Offset - 15; - } - else + } else NewOffset = Offset; - } - else - { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); + } else { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be" + " 8256\n"); NewOffset = Offset; } @@ -197,14 +198,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); - - if (Offset==0x0) + if (Offset == 0x0) priv->RfReg0Value[eRFPath] = Data; - if (priv->rf_chip == RF_8256) - { - if (Offset != 0) - { + if (priv->rf_chip == RF_8256) { + if (Offset != 0) { priv->RfReg0Value[eRFPath] &= 0xebf; rtl8192_setBBreg( dev, @@ -214,11 +212,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP } rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } - return; } -void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask, u32 Data) { struct r8192_priv *priv = rtllib_priv(dev); u32 Original_Value, BitShift, New_Value; @@ -229,36 +227,37 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, return; RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); - if (priv->Rf_Mode == RF_OP_By_FW) - { - if (BitMask != bMask12Bits) - { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + if (priv->Rf_Mode == RF_OP_By_FW) { + if (BitMask != bMask12Bits) { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, + RegAddr); BitShift = rtl8192_CalculateBitShift(BitMask); - New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); + New_Value = (((Original_Value) & (~BitMask)) | + (Data << BitShift)); phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); - }else + } else phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); udelay(200); - } - else - { - if (BitMask != bMask12Bits) - { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); + } else { + if (BitMask != bMask12Bits) { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, + RegAddr); BitShift = rtl8192_CalculateBitShift(BitMask); - New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); + New_Value = (((Original_Value) & (~BitMask)) | + (Data << BitShift)); - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); - }else + rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, + New_Value); + } else rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); } return; } -u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask) +u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask) { u32 Original_Value, Readback_Value, BitShift; struct r8192_priv *priv = rtllib_priv(dev); @@ -267,79 +266,61 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) return 0; down(&priv->rf_sem); - if (priv->Rf_Mode == RF_OP_By_FW) - { + if (priv->Rf_Mode == RF_OP_By_FW) { Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); udelay(200); - } - else - { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); - + } else { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, + RegAddr); } BitShift = rtl8192_CalculateBitShift(BitMask); Readback_Value = (Original_Value & BitMask) >> BitShift; up(&priv->rf_sem); - return (Readback_Value); + return Readback_Value; } -static u32 phy_FwRFSerialRead( - struct net_device* dev, - enum rf90_radio_path eRFPath, - u32 Offset ) +static u32 phy_FwRFSerialRead(struct net_device *dev, + enum rf90_radio_path eRFPath, u32 Offset) { u32 retValue = 0; u32 Data = 0; u8 time = 0; - Data |= ((Offset&0xFF)<<12); - Data |= ((eRFPath&0x3)<<20); + Data |= ((Offset & 0xFF) << 12); + Data |= ((eRFPath & 0x3) << 20); Data |= 0x80000000; - while (read_nic_dword(dev, QPNR)&0x80000000) - { + while (read_nic_dword(dev, QPNR)&0x80000000) { if (time++ < 100) - { udelay(10); - } else break; } write_nic_dword(dev, QPNR, Data); - while (read_nic_dword(dev, QPNR)&0x80000000) - { + while (read_nic_dword(dev, QPNR) & 0x80000000) { if (time++ < 100) - { udelay(10); - } else - return (0); + return 0; } retValue = read_nic_dword(dev, RF_DATA); - return (retValue); + return retValue; } /* phy_FwRFSerialRead */ -static void -phy_FwRFSerialWrite( - struct net_device* dev, - enum rf90_radio_path eRFPath, - u32 Offset, - u32 Data ) +static void phy_FwRFSerialWrite(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 Offset, u32 Data) { u8 time = 0; - - Data |= ((Offset&0xFF)<<12); - Data |= ((eRFPath&0x3)<<20); + Data |= ((Offset & 0xFF) << 12); + Data |= ((eRFPath & 0x3) << 20); Data |= 0x400000; Data |= 0x80000000; - while (read_nic_dword(dev, QPNR)&0x80000000) - { + while (read_nic_dword(dev, QPNR) & 0x80000000) { if (time++ < 100) - { udelay(10); - } else break; } @@ -348,82 +329,81 @@ phy_FwRFSerialWrite( } /* phy_FwRFSerialWrite */ -void rtl8192_phy_configmac(struct net_device* dev) +void rtl8192_phy_configmac(struct net_device *dev) { u32 dwArrayLen = 0, i = 0; - u32* pdwArray = NULL; + u32 *pdwArray = NULL; struct r8192_priv *priv = rtllib_priv(dev); - if (priv->bTXPowerDataReadFromEEPORM) - { + + if (priv->bTXPowerDataReadFromEEPORM) { RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); dwArrayLen = MACPHY_Array_PGLength; pdwArray = Rtl819XMACPHY_Array_PG; - } - else - { - RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n"); + } else { + RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n"); dwArrayLen = MACPHY_ArrayLength; pdwArray = Rtl819XMACPHY_Array; } - for (i = 0; irf_type == RF_2T4R) - { - PHY_REGArrayLen = PHY_REGArrayLength; - Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; - } - else if (priv->rf_type == RF_1T2R) - { - PHY_REGArrayLen = PHY_REG_1T2RArrayLength; - Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; - } + + AGCTAB_ArrayLen = AGCTAB_ArrayLength; + Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; + if (priv->rf_type == RF_2T4R) { + PHY_REGArrayLen = PHY_REGArrayLength; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; + } else if (priv->rf_type == RF_1T2R) { + PHY_REGArrayLen = PHY_REG_1T2RArrayLength; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; } - if (ConfigType == BaseBand_Config_PHY_REG) - { - for (i=0; iPHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; @@ -510,37 +490,45 @@ void rtl8192_InitBBRFRegDef(struct net_device* dev) priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; } -bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath) + +bool rtl8192_phy_checkBBAndRF(struct net_device *dev, + enum hw90_block CheckBlock, + enum rf90_radio_path eRFPath) { bool ret = true; u32 i, CheckTimes = 4, dwRegRead = 0; u32 WriteAddr[4]; u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; + WriteAddr[HW90_BLOCK_MAC] = 0x100; WriteAddr[HW90_BLOCK_PHY0] = 0x900; WriteAddr[HW90_BLOCK_PHY1] = 0x800; WriteAddr[HW90_BLOCK_RF] = 0x3; - RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock); - for (i=0 ; i < CheckTimes ; i++) - { - - switch (CheckBlock) - { + RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, + CheckBlock); + for (i = 0; i < CheckTimes; i++) { + switch (CheckBlock) { case HW90_BLOCK_MAC: - RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); + RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write " + "0x100 here!"); break; case HW90_BLOCK_PHY0: case HW90_BLOCK_PHY1: - write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); + write_nic_dword(dev, WriteAddr[CheckBlock], + WriteData[i]); dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); break; case HW90_BLOCK_RF: WriteData[i] &= 0xfff; - rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); + rtl8192_phy_SetRFReg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMask12Bits, WriteData[i]); mdelay(10); - dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); + dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, + WriteAddr[HW90_BLOCK_RF], + bMaskDWord); mdelay(10); break; @@ -550,9 +538,9 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock } - if (dwRegRead != WriteData[i]) - { - RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); + if (dwRegRead != WriteData[i]) { + RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, " + "WriteData: %x\n", dwRegRead, WriteData[i]); ret = false; break; } @@ -561,27 +549,27 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock return ret; } -bool rtl8192_BB_Config_ParaFile(struct net_device* dev) +bool rtl8192_BB_Config_ParaFile(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); bool rtStatus = true; u8 bRegValue = 0, eCheckItem = 0; u32 dwRegValue = 0; - /************************************** - **************************************/ bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); - write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); + write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); dwRegValue = read_nic_dword(dev, CPU_GEN); write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); - for (eCheckItem=(enum hw90_block)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) - { - rtStatus = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block)eCheckItem, (enum rf90_radio_path)0); - if (rtStatus != true) - { - RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); + for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; + eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { + rtStatus = rtl8192_phy_checkBBAndRF(dev, + (enum hw90_block)eCheckItem, + (enum rf90_radio_path)0); + if (rtStatus != true) { + RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():" + "Check PHY%d Fail!!\n", eCheckItem-1); return rtStatus; } } @@ -593,14 +581,11 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev) rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); - if (priv->IC_Cut > VERSION_8190_BD) - { + if (priv->IC_Cut > VERSION_8190_BD) { if (priv->rf_type == RF_2T4R) - { - dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 | - priv->AntennaTxPwDiff[1]<<4 | - priv->AntennaTxPwDiff[0]); - } + dwRegValue = (priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0]); else dwRegValue = 0x0; rtl8192_setBBreg(dev, rFPGA0_TxGainStage, @@ -608,22 +593,25 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev) dwRegValue = priv->CrystalCap; - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, + dwRegValue); } return rtStatus; } -bool rtl8192_BBConfig(struct net_device* dev) +bool rtl8192_BBConfig(struct net_device *dev) { bool rtStatus = true; + rtl8192_InitBBRFRegDef(dev); rtStatus = rtl8192_BB_Config_ParaFile(dev); return rtStatus; } -void rtl8192_phy_getTxPower(struct net_device* dev) +void rtl8192_phy_getTxPower(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); + priv->MCSTxPowerLevelOriginalOffset[0] = read_nic_dword(dev, rTxAGC_Rate18_06); priv->MCSTxPowerLevelOriginalOffset[1] = @@ -641,44 +629,39 @@ void rtl8192_phy_getTxPower(struct net_device* dev) priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); - RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", + RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, " + "c60=0x%x, c68=0x%x)\n", priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); - RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", + RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", rOFDM0_RxDetector3, priv->framesync); priv->SifsTime = read_nic_word(dev, SIFS); return; } -void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) +void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); - u8 powerlevel = 0,powerlevelOFDM24G = 0; + u8 powerlevel = 0, powerlevelOFDM24G = 0; char ant_pwr_diff; u32 u4RegValue; - if (priv->epromtype == EEPROM_93C46) - { + if (priv->epromtype == EEPROM_93C46) { powerlevel = priv->TxPowerLevelCCK[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; - } - else if (priv->epromtype == EEPROM_93C56) - { - if (priv->rf_type == RF_1T2R) - { + } else if (priv->epromtype == EEPROM_93C56) { + if (priv->rf_type == RF_1T2R) { powerlevel = priv->TxPowerLevelCCK_C[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; - } - else if (priv->rf_type == RF_2T4R) - { + } else if (priv->rf_type == RF_2T4R) { powerlevel = priv->TxPowerLevelCCK_A[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] - -priv->TxPowerLevelOFDM24G_A[channel-1]; + - priv->TxPowerLevelOFDM24G_A[channel-1]; priv->RF_C_TxPwDiff = ant_pwr_diff; @@ -688,9 +671,9 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); priv->AntennaTxPwDiff[0] = 0; - u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | - priv->AntennaTxPwDiff[1]<<4 | - priv->AntennaTxPwDiff[0]); + u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0]); rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); @@ -706,97 +689,105 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) case RF_8258: break; default: - RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __func__); + RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", + __func__); break; } return; } -bool rtl8192_phy_RFConfig(struct net_device* dev) +bool rtl8192_phy_RFConfig(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); bool rtStatus = true; - switch (priv->rf_chip) - { - case RF_8225: - break; - case RF_8256: - rtStatus = PHY_RF8256_Config(dev); - break; + switch (priv->rf_chip) { + case RF_8225: + break; + case RF_8256: + rtStatus = PHY_RF8256_Config(dev); + break; - case RF_8258: - break; - case RF_PSEUDO_11N: + case RF_8258: + break; + case RF_PSEUDO_11N: break; - default: - RT_TRACE(COMP_ERR, "error chip id\n"); - break; + default: + RT_TRACE(COMP_ERR, "error chip id\n"); + break; } return rtStatus; } -void rtl8192_phy_updateInitGain(struct net_device* dev) +void rtl8192_phy_updateInitGain(struct net_device *dev) { return; } -u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath) +u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, + enum rf90_radio_path eRFPath) { int i; u8 ret = 0; - switch (eRFPath){ - case RF90_PATH_A: - for (i = 0;iTxPowerLevelCCK[channel-1]; u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; - switch (priv->rf_chip) - { + switch (priv->rf_chip) { case RF_8225: break; @@ -818,31 +808,28 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) case RF_8258: break; default: - RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); + RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower" + "Level()\n"); break; } return; } -u8 rtl8192_phy_SetSwChnlCmdArray( - struct sw_chnl_cmd* CmdTable, - u32 CmdTableIdx, - u32 CmdTableSz, - enum sw_chnl_cmd_id CmdID, - u32 Para1, - u32 Para2, - u32 msDelay - ) + +u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx, + u32 CmdTableSz, enum sw_chnl_cmd_id CmdID, + u32 Para1, u32 Para2, u32 msDelay) { - struct sw_chnl_cmd* pCmd; + struct sw_chnl_cmd *pCmd; - if (CmdTable == NULL) - { - RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); + if (CmdTable == NULL) { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot " + "be NULL.\n"); return false; } - if (CmdTableIdx >= CmdTableSz) - { - RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", + if (CmdTableIdx >= CmdTableSz) { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid" + " index, please check size of the table, CmdTableIdx:" + "%d, CmdTableSz:%d\n", CmdTableIdx, CmdTableSz); return false; } @@ -855,7 +842,9 @@ u8 rtl8192_phy_SetSwChnlCmdArray( return true; } -u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) + +u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, + u8 *step, u32 *delay) { struct r8192_priv *priv = rtllib_priv(dev); struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; @@ -867,50 +856,58 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u struct sw_chnl_cmd *CurrentCmd = NULL; u8 eRFPath; - RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel); + RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", + __func__, *stage, *step, channel); - if (!IsLegalChannel(priv->rtllib, channel)) - { - RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); + if (!IsLegalChannel(priv->rtllib, channel)) { + RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", + channel); return true; } { PreCommonCmdCnt = 0; - rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_SetTxPowerLevel, 0, 0, 0); - rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_End, 0, 0, 0); + rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, + MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, + 0, 0, 0); + rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, + MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); PostCommonCmdCnt = 0; - rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, - CmdID_End, 0, 0, 0); + rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, + MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); RfDependCmdCnt = 0; - switch ( priv->rf_chip ) - { + switch (priv->rf_chip) { case RF_8225: - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); + if (!(channel >= 1 && channel <= 14)) { + RT_TRACE(COMP_ERR, "illegal channel for Zebra " + "8225: %d\n", channel); return false; } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, + RF_CHANNEL_TABLE_ZEBRA[channel], 10); + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_End, 0, 0, 0); break; case RF_8256: - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); + if (!(channel >= 1 && channel <= 14)) { + RT_TRACE(COMP_ERR, "illegal channel for Zebra" + " 8256: %d\n", channel); return false; } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, + RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, channel, + 10); + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, + RfDependCmdCnt++, + MAX_RFDEPENDCMD_CNT, CmdID_End, 0, 0, 0); break; @@ -918,68 +915,70 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u break; default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", + priv->rf_chip); return false; break; } - do{ - switch (*stage) - { + do { + switch (*stage) { case 0: - CurrentCmd=&PreCommonCmd[*step]; + CurrentCmd = &PreCommonCmd[*step]; break; case 1: - CurrentCmd=&RfDependCmd[*step]; + CurrentCmd = &RfDependCmd[*step]; break; case 2: - CurrentCmd=&PostCommonCmd[*step]; + CurrentCmd = &PostCommonCmd[*step]; break; } - if (CurrentCmd->CmdID==CmdID_End) - { - if ((*stage)==2) - { + if (CurrentCmd->CmdID == CmdID_End) { + if ((*stage) == 2) { return true; - } - else - { + } else { (*stage)++; - (*step)=0; + (*step) = 0; continue; } } - switch (CurrentCmd->CmdID) - { + switch (CurrentCmd->CmdID) { case CmdID_SetTxPowerLevel: if (priv->IC_Cut > (u8)VERSION_8190_BD) - rtl8192_SetTxPowerLevel(dev,channel); + rtl8192_SetTxPowerLevel(dev, channel); break; case CmdID_WritePortUlong: - write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); + write_nic_dword(dev, CurrentCmd->Para1, + CurrentCmd->Para2); break; case CmdID_WritePortUshort: - write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); + write_nic_word(dev, CurrentCmd->Para1, + (u16)CurrentCmd->Para2); break; case CmdID_WritePortUchar: - write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); + write_nic_byte(dev, CurrentCmd->Para1, + (u8)CurrentCmd->Para2); break; case CmdID_RF_WriteReg: - for (eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) - rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); + for (eRFPath = 0; eRFPath < + priv->NumTotalRFPath; eRFPath++) + rtl8192_phy_SetRFReg(dev, + (enum rf90_radio_path)eRFPath, + CurrentCmd->Para1, bMask12Bits, + CurrentCmd->Para2<<7); break; default: break; } break; - }while(true); - }/*for (Number of RF paths)*/ + } while (true); + } /*for (Number of RF paths)*/ - (*delay)=CurrentCmd->msDelay; + (*delay) = CurrentCmd->msDelay; (*step)++; return false; } @@ -987,14 +986,14 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); - u32 delay = 0; + u32 delay = 0; - while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) - { - if (delay>0) + while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, + &priv->SwChnlStep, &delay)) { + if (delay > 0) msleep(delay); if (IS_NIC_DOWN(priv)) - break; + break; } } void rtl8192_SwChnl_WorkItem(struct net_device *dev) @@ -1004,44 +1003,43 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev) RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); - RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv); + RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, + priv->chan, priv); rtl8192_phy_FinishSwChnlNow(dev , priv->chan); RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); } -u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) +u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); - if (IS_NIC_DOWN(priv)) - { - RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n",__func__); + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__); return false; } if (priv->SwChnlInProgress) return false; - switch (priv->rtllib->mode) - { + switch (priv->rtllib->mode) { case WIRELESS_MODE_A: case WIRELESS_MODE_N_5G: - if (channel<=14){ + if (channel <= 14) { RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); return false; } break; case WIRELESS_MODE_B: - if (channel>14){ + if (channel > 14) { RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); return false; } break; case WIRELESS_MODE_G: case WIRELESS_MODE_N_24G: - if (channel>14){ + if (channel > 14) { RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); return false; } @@ -1052,71 +1050,77 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) if (channel == 0) channel = 1; - priv->chan=channel; + priv->chan = channel; - priv->SwChnlStage=0; - priv->SwChnlStep=0; + priv->SwChnlStage = 0; + priv->SwChnlStep = 0; - if (!IS_NIC_DOWN(priv)){ + if (!IS_NIC_DOWN(priv)) rtl8192_SwChnl_WorkItem(dev); - } priv->SwChnlInProgress = false; return true; } -static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) +static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - switch (priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - priv->CCKPresentAttentuation = - priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; - - if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) - priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; - if (priv->CCKPresentAttentuation < 0) - priv->CCKPresentAttentuation = 0; - - RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_20Mdefault + + priv->CCKPresentAttentuation_difference; - if (priv->rtllib->current_network.channel== 14 && !priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = true; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = false; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + if (priv->CCKPresentAttentuation > + (CCKTxBBGainTableLength-1)) + priv->CCKPresentAttentuation = + CCKTxBBGainTableLength-1; + if (priv->CCKPresentAttentuation < 0) + priv->CCKPresentAttentuation = 0; + + RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent" + "Attentuation = %d\n", + priv->CCKPresentAttentuation); + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else if (priv->rtllib->current_network.channel != + 14 && priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else { + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } break; - case HT_CHANNEL_WIDTH_20_40: + case HT_CHANNEL_WIDTH_20_40: + priv->CCKPresentAttentuation = + priv->CCKPresentAttentuation_40Mdefault + + priv->CCKPresentAttentuation_difference; + + RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent" + "Attentuation = %d\n", + priv->CCKPresentAttentuation); + if (priv->CCKPresentAttentuation > + (CCKTxBBGainTableLength - 1)) priv->CCKPresentAttentuation = - priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; - - RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); - if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1)) - priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; - if (priv->CCKPresentAttentuation < 0) - priv->CCKPresentAttentuation = 0; - - if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = true; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = false; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + CCKTxBBGainTableLength-1; + if (priv->CCKPresentAttentuation < 0) + priv->CCKPresentAttentuation = 0; + + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else if (priv->rtllib->current_network.channel != 14 + && priv->bcck_in_ch14) { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } else { + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } break; } } @@ -1125,24 +1129,29 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) + if (priv->rtllib->current_network.channel == 14 && + !priv->bcck_in_ch14) priv->bcck_in_ch14 = true; - else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) + else if (priv->rtllib->current_network.channel != 14 && + priv->bcck_in_ch14) priv->bcck_in_ch14 = false; - switch (priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - if (priv->Record_CCK_20Mindex == 0) - priv->Record_CCK_20Mindex = 6; - priv->CCK_index = priv->Record_CCK_20Mindex; - RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index); - break; - - case HT_CHANNEL_WIDTH_20_40: - priv->CCK_index = priv->Record_CCK_40Mindex; - RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); - break; + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + if (priv->Record_CCK_20Mindex == 0) + priv->Record_CCK_20Mindex = 6; + priv->CCK_index = priv->Record_CCK_20Mindex; + RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_" + "Switch_ThermalMeter(),CCK_index = %d\n", + priv->CCK_index); + break; + + case HT_CHANNEL_WIDTH_20_40: + priv->CCK_index = priv->Record_CCK_40Mindex; + RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_" + "Switch_ThermalMeter(), CCK_index = %d\n", + priv->CCK_index); + break; } dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } @@ -1163,108 +1172,107 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) struct r8192_priv *priv = rtllib_priv(dev); u8 regBwOpMode; - RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ - priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") + RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s " + "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? + "20MHz" : "40MHz") - if (priv->rf_chip== RF_PSEUDO_11N) - { - priv->SetBWModeInProgress= false; + if (priv->rf_chip == RF_PSEUDO_11N) { + priv->SetBWModeInProgress = false; return; } - if (IS_NIC_DOWN(priv)){ - RT_TRACE(COMP_ERR,"%s(): ERR!! driver is not up\n",__func__); + if (IS_NIC_DOWN(priv)) { + RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__); return; } regBwOpMode = read_nic_byte(dev, BW_OPMODE); - switch (priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - regBwOpMode |= BW_OPMODE_20MHZ; - write_nic_byte(dev, BW_OPMODE, regBwOpMode); - break; + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; - case HT_CHANNEL_WIDTH_20_40: - regBwOpMode &= ~BW_OPMODE_20MHZ; - write_nic_byte(dev, BW_OPMODE, regBwOpMode); - break; + case HT_CHANNEL_WIDTH_20_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; - default: - RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); - break; + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " + "Bandwidth: %#X\n", priv->CurrentChannelBW); + break; } - switch (priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); - - if (!priv->btxpower_tracking) - { - write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); - } - else - CCK_Tx_Power_Track_BW_Switch(dev); - - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); + switch (priv->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + + if (!priv->btxpower_tracking) { + write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + } else { + CCK_Tx_Power_Track_BW_Switch(dev); + } - break; - case HT_CHANNEL_WIDTH_20_40: - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); - - if (!priv->btxpower_tracking) - { - write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); - } - else - CCK_Tx_Power_Track_BW_Switch(dev); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); - rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); - rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + break; + case HT_CHANNEL_WIDTH_20_40: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + + if (!priv->btxpower_tracking) { + write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); + } else { + CCK_Tx_Power_Track_BW_Switch(dev); + } + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, + (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, + priv->nCur40MhzPrimeSC); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); - break; - default: - RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); - break; + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); + break; + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown " + "Bandwidth: %#X\n", priv->CurrentChannelBW); + break; } - switch ( priv->rf_chip ) - { - case RF_8225: - break; + switch (priv->rf_chip) { + case RF_8225: + break; - case RF_8256: - PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); - break; + case RF_8256: + PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; - case RF_8258: - break; + case RF_8258: + break; - case RF_PSEUDO_11N: - break; + case RF_PSEUDO_11N: + break; - default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); - break; + default: + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + break; } atomic_dec(&(priv->rtllib->atm_swbw)); - priv->SetBWModeInProgress= false; + priv->SetBWModeInProgress = false; RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); } -void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset) +void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, + enum ht_extchnl_offset Offset) { struct r8192_priv *priv = rtllib_priv(dev); @@ -1272,14 +1280,14 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, if (priv->SetBWModeInProgress) return; - atomic_inc(&(priv->rtllib->atm_swbw)); - priv->SetBWModeInProgress= true; + atomic_inc(&(priv->rtllib->atm_swbw)); + priv->SetBWModeInProgress = true; priv->CurrentChannelBW = Bandwidth; - if (Offset==HT_EXTCHNL_OFFSET_LOWER) + if (Offset == HT_EXTCHNL_OFFSET_LOWER) priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; - else if (Offset==HT_EXTCHNL_OFFSET_UPPER) + else if (Offset == HT_EXTCHNL_OFFSET_UPPER) priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; else priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; @@ -1288,79 +1296,107 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, } - void InitialGain819xPci(struct net_device *dev, u8 Operation) { #define SCAN_RX_INITIAL_GAIN 0x17 #define POWER_DETECTION_TH 0x08 struct r8192_priv *priv = rtllib_priv(dev); - u32 BitMask; - u8 initial_gain; - - if (!IS_NIC_DOWN(priv)){ - switch (Operation) - { - case IG_Backup: - RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); - initial_gain = SCAN_RX_INITIAL_GAIN; - BitMask = bMaskByte0; - if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); - priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); - priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); - priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); - priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); - BitMask = bMaskByte2; - priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); - - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); - - RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); - write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); - RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); - write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); - break; - case IG_Restore: - RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); - BitMask = 0x7f; - if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); - - rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); - rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); - rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); - rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); - BitMask = bMaskByte2; - rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); - - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); - - rtl8192_phy_setTxPower(dev,priv->rtllib->current_network.channel); - - - if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); - break; - default: - RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); - break; + u32 BitMask; + u8 initial_gain; + + if (!IS_NIC_DOWN(priv)) { + switch (Operation) { + case IG_Backup: + RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial" + " gain.\n"); + initial_gain = SCAN_RX_INITIAL_GAIN; + BitMask = bMaskByte0; + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + priv->initgain_backup.xaagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, + BitMask); + priv->initgain_backup.xbagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, + BitMask); + priv->initgain_backup.xcagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, + BitMask); + priv->initgain_backup.xdagccore1 = + (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, + BitMask); + BitMask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, + rCCK0_CCA, BitMask); + + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is" + " %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is" + " %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is" + " %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is" + " %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is" + " %x\n", priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", + initial_gain); + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", + POWER_DETECTION_TH); + write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + break; + case IG_Restore: + RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial " + "gain.\n"); + BitMask = 0x7f; + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); + + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, + (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, + (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, + (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, + (u32)priv->initgain_backup.xdagccore1); + BitMask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, + (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50" + " is %x\n", priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58" + " is %x\n", priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60" + " is %x\n", priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68" + " is %x\n", priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a" + " is %x\n", priv->initgain_backup.cca); + + rtl8192_phy_setTxPower(dev, + priv->rtllib->current_network.channel); + + if (dm_digtable.dig_algorithm == + DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); + break; + default: + RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); + break; } } } -extern void -PHY_SetRtl8192eRfOff(struct net_device* dev ) +void PHY_SetRtl8192eRfOff(struct net_device *dev) { rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); @@ -1374,14 +1410,12 @@ PHY_SetRtl8192eRfOff(struct net_device* dev ) } -bool -SetRFPowerState8190( - struct net_device* dev, - enum rt_rf_power_state eRFPowerState - ) +bool SetRFPowerState8190(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) { struct r8192_priv *priv = rtllib_priv(dev); - struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)(&(priv->rtllib->PowerSaveControl)); + struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) + (&(priv->rtllib->PowerSaveControl)); bool bResult = true; u8 i = 0, QueueID = 0; struct rtl8192_tx_ring *ring = NULL; @@ -1391,137 +1425,142 @@ SetRFPowerState8190( RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); priv->SetRFPowerStateInProgress = true; - switch (priv->rf_chip) - { - case RF_8256: - switch ( eRFPowerState ) - { - case eRfOn: - RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n"); - if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) - { - bool rtstatus = true; - u32 InitilizeCount = 3; - do - { - InitilizeCount--; - priv->RegRfOff = false; - rtstatus = NicIFEnableNIC(dev); - }while( (rtstatus != true) &&(InitilizeCount >0) ); - - if (rtstatus != true) - { - RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__func__); - priv->SetRFPowerStateInProgress = false; - return false; - } - - RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); - } else { + switch (priv->rf_chip) { + case RF_8256: + switch (eRFPowerState) { + case eRfOn: + RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n"); + if ((priv->rtllib->eRFPowerState == eRfOff) && + RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { + bool rtstatus = true; + u32 InitilizeCount = 3; + do { + InitilizeCount--; + priv->RegRfOff = false; + rtstatus = NicIFEnableNIC(dev); + } while ((rtstatus != true) && + (InitilizeCount > 0)); + + if (rtstatus != true) { + RT_TRACE(COMP_ERR, "%s():Initialize Ada" + "pter fail,return\n", + __func__); + priv->SetRFPowerStateInProgress = false; + return false; + } + + RT_CLEAR_PS_LEVEL(pPSC, + RT_RF_OFF_LEVL_HALT_NIC); + } else { write_nic_byte(dev, ANAPAR, 0x37); mdelay(1); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x4, 0x1); priv->bHwRfOffAction = 0; - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, + BIT4, 0x1); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, + 0x300, 0x3); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x18, 0x3); + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, + 0x3); + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, + 0x3); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, + 0x60, 0x3); - } + } - break; + break; + + case eRfSleep: + if (priv->rtllib->eRFPowerState == eRfOff) + break; - case eRfSleep: - { - if (priv->rtllib->eRFPowerState == eRfOff) - break; + for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { + ring = &priv->tx_ring[QueueID]; - { - for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) - { - ring = &priv->tx_ring[QueueID]; - - if (skb_queue_len(&ring->queue) == 0) { - QueueID++; - continue; - } - else - { - RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); - udelay(10); - i++; - } - - if (i >= MAX_DOZE_WAITING_TIMES_9x) - { - RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); - break; - } - } + if (skb_queue_len(&ring->queue) == 0) { + QueueID++; + continue; + } else { + RT_TRACE((COMP_POWER|COMP_RF), "eRf Off" + "/Sleep: %d times TcbBusyQueue" + "[%d] !=0 before doze!\n", + (i+1), QueueID); + udelay(10); + i++; } - { - PHY_SetRtl8192eRfOff(dev); + if (i >= MAX_DOZE_WAITING_TIMES_9x) { + RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! " + "SetRFPowerState8190(): eRfOff" + ": %d times TcbBusyQueue[%d] " + "!= 0 !!!\n", + MAX_DOZE_WAITING_TIMES_9x, + QueueID); + break; } } - break; - - case eRfOff: - RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n"); - - - for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { - ring = &priv->tx_ring[QueueID]; - - if (skb_queue_len(&ring->queue) == 0) { - QueueID++; - continue; - } - else - { - RT_TRACE(COMP_POWER, - "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); - udelay(10); - i++; - } - - if (i >= MAX_DOZE_WAITING_TIMES_9x) - { - RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); - break; - } - } - - { - if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) - { - - NicIFDisableNIC(dev); - RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); - } - else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) - { - PHY_SetRtl8192eRfOff(dev); - } + PHY_SetRtl8192eRfOff(dev); + break; + + case eRfOff: + RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/" + "Sleep !\n"); + + for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { + ring = &priv->tx_ring[QueueID]; + + if (skb_queue_len(&ring->queue) == 0) { + QueueID++; + continue; + } else { + RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d" + " times TcbBusyQueue[%d] !=0 b" + "efore doze!\n", (i+1), + QueueID); + udelay(10); + i++; } + if (i >= MAX_DOZE_WAITING_TIMES_9x) { + RT_TRACE(COMP_POWER, "\n\n\n SetZebra: " + "RFPowerState8185B(): eRfOff:" + " %d times TcbBusyQueue[%d] " + "!= 0 !!!\n", + MAX_DOZE_WAITING_TIMES_9x, + QueueID); break; + } + } - default: - bResult = false; - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); - break; - } + if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && + !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { + NicIFDisableNIC(dev); + RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); + } else if (!(pPSC->RegRfPsLevel & + RT_RF_OFF_LEVL_HALT_NIC)) { + PHY_SetRtl8192eRfOff(dev); + } - break; + break; default: - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); + bResult = false; + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state" + " to set: 0x%X!!!\n", eRFPowerState); break; + } + + break; + + default: + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); + break; } if (bResult) { @@ -1532,62 +1571,60 @@ SetRFPowerState8190( break; default: - RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); + RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown " + "RF type\n"); break; } } priv->SetRFPowerStateInProgress = false; - RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); + RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", + bResult); return bResult; } - - -bool -SetRFPowerState( - struct net_device* dev, - enum rt_rf_power_state eRFPowerState - ) +bool SetRFPowerState(struct net_device *dev, + enum rt_rf_power_state eRFPowerState) { struct r8192_priv *priv = rtllib_priv(dev); bool bResult = false; - RT_TRACE(COMP_PS,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); - if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) { - RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); + RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n", + eRFPowerState); + if (eRFPowerState == priv->rtllib->eRFPowerState && + priv->bHwRfOffAction == 0) { + RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the " + "request for eRFPowerState(%d) is the same.\n", + eRFPowerState); return bResult; } bResult = SetRFPowerState8190(dev, eRFPowerState); - RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", bResult); + RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", + bResult); return bResult; } -extern void -PHY_ScanOperationBackup8192( - struct net_device* dev, - u8 Operation - ) +extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation) { struct r8192_priv *priv = rtllib_priv(dev); if (priv->up) { switch (Operation) { - case SCAN_OPT_BACKUP: - priv->rtllib->InitialGainHandler(dev,IG_Backup); - break; + case SCAN_OPT_BACKUP: + priv->rtllib->InitialGainHandler(dev, IG_Backup); + break; - case SCAN_OPT_RESTORE: - priv->rtllib->InitialGainHandler(dev,IG_Restore); - break; + case SCAN_OPT_RESTORE: + priv->rtllib->InitialGainHandler(dev, IG_Restore); + break; - default: - RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n"); - break; + default: + RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n"); + break; } } diff --git a/drivers/staging/rtl8192e/r8192E_phy.h b/drivers/staging/rtl8192e/r8192E_phy.h index 79adc8096bd4..86c6acd0c546 100644 --- a/drivers/staging/rtl8192e/r8192E_phy.h +++ b/drivers/staging/rtl8192e/r8192E_phy.h @@ -25,25 +25,25 @@ #define MAX_RFDEPENDCMD_CNT 16 #define MAX_POSTCMD_CNT 16 -#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE -#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE -#define RadioA_ArrayLength RadioA_ArrayLengthPciE -#define RadioB_ArrayLength RadioB_ArrayLengthPciE +#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE +#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE +#define RadioA_ArrayLength RadioA_ArrayLengthPciE +#define RadioB_ArrayLength RadioB_ArrayLengthPciE #define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE -#define RadioC_ArrayLength RadioC_ArrayLengthPciE -#define RadioD_ArrayLength RadioD_ArrayLengthPciE -#define PHY_REGArrayLength PHY_REGArrayLengthPciE -#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE +#define RadioC_ArrayLength RadioC_ArrayLengthPciE +#define RadioD_ArrayLength RadioD_ArrayLengthPciE +#define PHY_REGArrayLength PHY_REGArrayLengthPciE +#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE #define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG -#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array -#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array -#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array -#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array -#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array -#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array -#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray -#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray +#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array +#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array +#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array +#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array +#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array +#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array +#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray +#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray @@ -57,7 +57,7 @@ enum sw_chnl_cmd_id { CmdID_RF_WriteReg, }; -/*--------------------------------Define structure--------------------------------*/ +/*--------------------------------Define structure----------------------------*/ struct sw_chnl_cmd { enum sw_chnl_cmd_id CmdID; u32 Para1; @@ -97,23 +97,35 @@ enum rf90_radio_path { #define bMaskLWord 0x0000ffff #define bMaskDWord 0xffffffff -extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); -extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); -extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); -extern void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); -extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask); -extern void rtl8192_phy_configmac(struct net_device* dev); -extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); -extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath); -extern bool rtl8192_BBConfig(struct net_device* dev); -extern void rtl8192_phy_getTxPower(struct net_device* dev); -extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); -extern bool rtl8192_phy_RFConfig(struct net_device* dev); -extern void rtl8192_phy_updateInitGain(struct net_device* dev); -extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath); - -extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); -extern void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset); +extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, + u32 eRFPath); +extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask, u32 dwData); +extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, + u32 dwBitMask); +extern void rtl8192_phy_SetRFReg(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask, u32 Data); +extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev, + enum rf90_radio_path eRFPath, + u32 RegAddr, u32 BitMask); +extern void rtl8192_phy_configmac(struct net_device *dev); +extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType); +extern bool rtl8192_phy_checkBBAndRF(struct net_device *dev, + enum hw90_block CheckBlock, + enum rf90_radio_path eRFPath); +extern bool rtl8192_BBConfig(struct net_device *dev); +extern void rtl8192_phy_getTxPower(struct net_device *dev); +extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel); +extern bool rtl8192_phy_RFConfig(struct net_device *dev); +extern void rtl8192_phy_updateInitGain(struct net_device *dev); +extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, + enum rf90_radio_path eRFPath); + +extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel); +extern void rtl8192_SetBWMode(struct net_device *dev, + enum ht_channel_width Bandwidth, + enum ht_extchnl_offset Offset); extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); extern void rtl8192_SetBWModeWorkItem(struct net_device *dev); extern void InitialGain819xPci(struct net_device *dev, u8 Operation); @@ -122,11 +134,11 @@ extern void PHY_SetRtl8192eRfOff(struct net_device *dev); bool SetRFPowerState( - struct net_device* dev, + struct net_device *dev, enum rt_rf_power_state eRFPowerState ); #define PHY_SetRFPowerState SetRFPowerState -extern void PHY_ScanOperationBackup8192(struct net_device* dev,u8 Operation); +extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation); #endif