From: Fabio Estevam Date: Thu, 18 Sep 2014 23:23:49 +0000 (-0300) Subject: ARM: dts: imx51: Improve SSI clocks description X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=53ec874846d9a0a8da5ca95a8891372c7e734367;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git ARM: dts: imx51: Improve SSI clocks description SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode. Add the extra 'baud' clock so that we can have SSI functional in master mode. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 92660e1fe1fc..c0116cffc513 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -214,7 +214,9 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -504,7 +506,9 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -560,7 +564,9 @@ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx";