From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Date: Tue, 8 Sep 2015 11:03:55 +0000 (+0300)
Subject: intel_th: pci: Add Denverton SOC support
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=5118ccd34780f4637a9360be580f41f4c1feab48;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

intel_th: pci: Add Denverton SOC support

This adds Intel(R) Trace Hub PCI ID for Denverton SOC.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
---

diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c
index 0bba3842336e..04bd57b0100a 100644
--- a/drivers/hwtracing/intel_th/pci.c
+++ b/drivers/hwtracing/intel_th/pci.c
@@ -85,6 +85,11 @@ static const struct pci_device_id intel_th_pci_id_table[] = {
 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
 		.driver_data = (kernel_ulong_t)0,
 	},
+	{
+		/* Denverton */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
+		.driver_data = (kernel_ulong_t)0,
+	},
 	{ 0 },
 };