From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Fri, 23 May 2014 20:16:45 +0000 (-0700)
Subject: drm/i915/vlv: add pll assertion when disabling DPIO common well
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=4dfbd12c33a7f76cdf38b9edcc21b06223b33268;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git

drm/i915/vlv: add pll assertion when disabling DPIO common well

When doing this, all PLLs should be disabled.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cca93d06894c..b86edac51be2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5711,9 +5711,11 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
 			  enum punit_power_well power_well_id, bool enable)
 {
+	struct drm_device *dev = dev_priv->dev;
 	u32 mask;
 	u32 state;
 	u32 ctrl;
+	enum pipe pipe;
 
 	if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		if (enable) {
@@ -5727,6 +5729,8 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv,
 				   DPLL_INTEGRATED_CRI_CLK_VLV);
 			udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 		} else {
+			for_each_pipe(pipe)
+				assert_pll_disabled(dev_priv, pipe);
 			/* Assert common reset */
 			I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
 				   ~DPIO_CMNRST);