From: FUJITA Tomonori Date: Tue, 29 Jun 2010 07:32:42 +0000 (+0900) Subject: tile: remove homegrown L1_CACHE_ALIGN macro X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git tile: remove homegrown L1_CACHE_ALIGN macro Let's use the standard L1_CACHE_ALIGN macro instead. Signed-off-by: FUJITA Tomonori Acked-by: Chris Metcalf --- diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index c2b7dcfe5327..ee597147e5cd 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -20,7 +20,6 @@ /* bytes per L1 data cache line */ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES) /* bytes per L1 instruction cache line */ #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()