From: Axel Lin Date: Mon, 24 Oct 2011 03:32:41 +0000 (+0800) Subject: ASoC: wm8940: Fix setting PLL Output clock division ratio X-Git-Tag: MMI-PSA29.97-13-9~16612^2~523 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git ASoC: wm8940: Fix setting PLL Output clock division ratio According to the datasheet: The PLL Output clock division ratio is controlled by BIT[5:4] of WM8940_GPIO register(08h). Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong. Signed-off-by: Axel Lin Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c index a4abfdfb217b..3cc3bce61316 100644 --- a/sound/soc/codecs/wm8940.c +++ b/sound/soc/codecs/wm8940.c @@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5)); break; case WM8940_OPCLKDIV: - reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF; - ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4)); + reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF; + ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4)); break; } return ret;