From: Tony Lindgren Date: Tue, 28 Jun 2016 06:30:02 +0000 (-0700) Subject: ARM: OMAP2+: Fix build if CONFIG_SMP is not set X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=44e7475d40eb26b8d3a6e2b2f7a5f12a5fe0942e;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git ARM: OMAP2+: Fix build if CONFIG_SMP is not set Looks like I only partially fixed up things if CONFIG_SMP is not set for the recent kexec changes. We don't have boot_secondary available without SMP as reported by Arnd. Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec") Reported-by: Arnd Bergmann Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 6d1dffca6c7b..fe36ce2734d4 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -24,6 +24,16 @@ #define AUX_CORE_BOOT0_PA 0x48281800 #define API_HYP_ENTRY 0x102 +ENTRY(omap_secondary_startup) +#ifdef CONFIG_SMP + b secondary_startup +#else +/* Should never get here */ +again: wfi + b again +#endif +#ENDPROC(omap_secondary_startup) + /* * OMAP5 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which @@ -39,7 +49,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 and r4, r4, #0x0f cmp r0, r4 bne wait - b secondary_startup + b omap_secondary_startup ENDPROC(omap5_secondary_startup) /* * Same as omap5_secondary_startup except we call into the ROM to @@ -59,7 +69,7 @@ wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 adr r0, hyp_boot smc #0 hyp_boot: - b secondary_startup + b omap_secondary_startup ENDPROC(omap5_secondary_hyp_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM @@ -82,7 +92,7 @@ hold: ldr r12,=0x103 * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ - b secondary_startup + b omap_secondary_startup ENDPROC(omap4_secondary_startup) ENTRY(omap4460_secondary_startup) @@ -119,5 +129,5 @@ hold_2: ldr r12,=0x103 * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ - b secondary_startup + b omap_secondary_startup ENDPROC(omap4460_secondary_startup)