From: Scott Wood Date: Sun, 25 Jun 2017 02:39:05 +0000 (-0500) Subject: powerpc/ipic: Support edge on IRQ0 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=446183e4069e0b62cedfd72ccb90b801b7a5aa98;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git powerpc/ipic: Support edge on IRQ0 External IRQ0 (index 48) has the same capabilities as the other IRQ1-7 and is handled by the same register IPIC_SEPNR. When this register is not specified for "ack" in "ipic_info", you cannot configure this IRQ as IRQ_TYPE_EDGE_FALLING. This oversight was probably due to the non-contiguous hwirq numbering of IRQ0 in the IPIC. Signed-off-by: Jurgen Schindele [scottwood: Cleaned up commit message and posted as a proper patch] Signed-off-by: Scott Wood Signed-off-by: Michael Ellerman --- diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index f267ee0afc08..16f1edd78c40 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c @@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = { .prio_mask = 7, }, [48] = { + .ack = IPIC_SEPNR, .mask = IPIC_SEMSR, .prio = IPIC_SMPRR_A, .force = IPIC_SEFCR,