From: Paul Mundt <lethal@linux-sh.org>
Date: Wed, 9 Apr 2008 08:58:22 +0000 (+0900)
Subject: sh: Fix up L2 cache probe.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=440fc172ae333c52c458401fe059afcc6e91eebf;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

sh: Fix up L2 cache probe.

SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6ea87af7247e..ebceb0dadff5 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
 	 * SH-4A's have an optional PIPT L2.
 	 */
 	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+		/* Bug if we can't decode the L2 info */
+		BUG_ON(!(cvr & 0xf));
+
+		/* Silicon and specifications have clearly never met.. */
+		cvr ^= 0xf;
+
 		/*
 		 * Size calculation is much more sensible
 		 * than it is for the L1.