From: Ralph Metzler Date: Sun, 3 Jul 2011 16:42:18 +0000 (-0300) Subject: [media] DRX-K: Initial check-in X-Git-Tag: MMI-PSA29.97-13-9~18729^2~135 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=43dd07f758d81fc55a7a1ff24b7689b10cc75bf2;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git [media] DRX-K: Initial check-in Driver for the DRX-K DVB-C/T demodulator. Signed-off-by: Ralph Metzler Signed-off-by: Oliver Endriss Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/media/dvb/frontends/drxk.h b/drivers/media/dvb/frontends/drxk.h new file mode 100644 index 000000000000..d1c133e065ff --- /dev/null +++ b/drivers/media/dvb/frontends/drxk.h @@ -0,0 +1,10 @@ +#ifndef _DRXK_H_ +#define _DRXK_H_ + +#include +#include + +extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, + u8 adr, + struct dvb_frontend **fe_t); +#endif diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c new file mode 100644 index 000000000000..e6b1499186a5 --- /dev/null +++ b/drivers/media/dvb/frontends/drxk_hard.c @@ -0,0 +1,5016 @@ +/* + * drxk_hard: DRX-K DVB-C/T demodulator driver + * + * Copyright (C) 2010-2011 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" +#include "drxk.h" +#include "drxk_hard.h" + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); +static int PowerDownQAM(struct drxk_state *state); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int SetQAMStandard(struct drxk_state *state,enum OperationMode oMode); +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode); +static int DVBTStart(struct drxk_state *state); +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, + s32 tunerFreqOffset); +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); +static int SwitchAntennaToQAM(struct drxk_state *state); +static int SwitchAntennaToDVBT(struct drxk_state *state); + +static bool IsDVBT(struct drxk_state *state) +{ + return state->m_OperationMode == OM_DVBT; +} + +static bool IsQAM(struct drxk_state *state) +{ + return state->m_OperationMode == OM_QAM_ITU_A || + state->m_OperationMode == OM_QAM_ITU_B || + state->m_OperationMode == OM_QAM_ITU_C; +} + +bool IsA1WithPatchCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_PATCH_CODE; +} + +bool IsA1WithRomCode(struct drxk_state *state) +{ + return state->m_DRXK_A1_ROM_CODE; +} + +#define NOA1ROM 0 + +#ifndef CHK_ERROR + #define CHK_ERROR(s) if ((status = s) < 0) break +#endif + +#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) +#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) + +#define DEFAULT_MER_83 165 +#define DEFAULT_MER_93 250 + +#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02) +#endif + +#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH +#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03) +#endif + +#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH +#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06) +#endif + +#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700 +#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500 + +#ifndef DRXK_KI_RAGC_ATV +#define DRXK_KI_RAGC_ATV 4 +#endif +#ifndef DRXK_KI_IAGC_ATV +#define DRXK_KI_IAGC_ATV 6 +#endif +#ifndef DRXK_KI_DAGC_ATV +#define DRXK_KI_DAGC_ATV 7 +#endif + +#ifndef DRXK_KI_RAGC_QAM +#define DRXK_KI_RAGC_QAM 3 +#endif +#ifndef DRXK_KI_IAGC_QAM +#define DRXK_KI_IAGC_QAM 4 +#endif +#ifndef DRXK_KI_DAGC_QAM +#define DRXK_KI_DAGC_QAM 7 +#endif +#ifndef DRXK_KI_RAGC_DVBT +#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2) +#endif +#ifndef DRXK_KI_IAGC_DVBT +#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2) +#endif +#ifndef DRXK_KI_DAGC_DVBT +#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7) +#endif + +#ifndef DRXK_AGC_DAC_OFFSET +#define DRXK_AGC_DAC_OFFSET (0x800) +#endif + +#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ +#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +#endif + +#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ +#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +#endif + +#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ +#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) +#endif + +#ifndef DRXK_QAM_SYMBOLRATE_MAX +#define DRXK_QAM_SYMBOLRATE_MAX (7233000) +#endif + +#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64 +#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0 +#define DRXK_BL_ROM_OFFSET_TAPS_BG 24 +#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32 +#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40 +#define DRXK_BL_ROM_OFFSET_TAPS_FM 48 +#define DRXK_BL_ROM_OFFSET_UCODE 0 + +#define DRXK_BLC_TIMEOUT 100 + +#define DRXK_BLCC_NR_ELEMENTS_TAPS 2 +#define DRXK_BLCC_NR_ELEMENTS_UCODE 6 + +#define DRXK_BLDC_NR_ELEMENTS_TAPS 28 + +#ifndef DRXK_OFDM_NE_NOTCH_WIDTH +#define DRXK_OFDM_NE_NOTCH_WIDTH (4) +#endif + +#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960) +#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480) +#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008) +#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992) +#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) + +inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64 = (u64)a * (u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +inline u32 Frac28a(u32 a, u32 c) +{ + int i = 0; + u32 Q1 = 0; + u32 R0 = 0; + + R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ + Q1 = a / c; /* integer part, only the 4 least significant bits + will be visible in the result */ + + /* division using radix 16, 7 nibbles in the result */ + for (i = 0; i < 7; i++) { + Q1 = (Q1 << 4) | (R0 / c); + R0 = (R0 % c) << 4; + } + /* rounding */ + if ((R0 >> 3) >= c) + Q1++; + + return Q1; +} + +static u32 Log10Times100(u32 x) +{ + static const u8 scale = 15; + static const u8 indexWidth = 5; + u8 i = 0; + u32 y = 0; + u32 d = 0; + u32 k = 0; + u32 r = 0; + /* + log2lut[n] = (1< 0; k--) { + if (x & (((u32)1) << scale)) + break; + x <<= 1; + } + } else { + for (k = scale; k < 31 ; k++) { + if ((x & (((u32)(-1)) << (scale+1))) == 0) + break; + x >>= 1; + } + } + /* + Now x has binary point between bit[scale] and bit[scale-1] + and 1.0 <= x < 2.0 */ + + /* correction for divison: log(x) = log(x/y)+log(y) */ + y = k * ((((u32)1) << scale) * 200); + + /* remove integer part */ + x &= ((((u32)1) << scale)-1); + /* get index */ + i = (u8) (x >> (scale - indexWidth)); + /* compute delta (x - a) */ + d = x & ((((u32)1) << (scale - indexWidth)) - 1); + /* compute log, multiplication (d* (..)) must be within range ! */ + y += log2lut[i] + + ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); + /* Conver to log10() */ + y /= 108853; /* (log2(10) << scale) */ + r = (y >> 1); + /* rounding */ + if (y & ((u32)1)) + r++; + return (r); +} + +/****************************************************************************/ +/* I2C **********************************************************************/ +/****************************************************************************/ + +static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) +{ + struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, + .buf = val, .len = 1 }}; + return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; +} + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = + {.addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { + printk("i2c_write error\n"); + return -1; + } + return 0; +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, + .buf = msg, .len = len}, + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { + printk("i2c_read error\n"); + return -1; + } + return 0; +} + +static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) +{ + u8 adr=state->demod_address, mm1[4], mm2[2], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8); + return 0; +} + +static int Read16_0(struct drxk_state *state, u32 reg, u16 *data) +{ + return Read16(state, reg, data, 0); +} + +static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) +{ + u8 adr = state->demod_address, mm1[4], mm2[4], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm1[0] = (((reg << 1) & 0xFF) | 0x01); + mm1[1] = ((reg >> 16) & 0xFF); + mm1[2] = ((reg >> 24) & 0xFF) | flags; + mm1[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm1[0] = ((reg << 1) & 0xFF); + mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0) + return -1; + if (data) + *data = mm2[0] | (mm2[1] << 8) | + (mm2[2] << 16) | (mm2[3] << 24); + return 0; +} + +static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) +{ + u8 adr = state->demod_address, mm[6], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >>8) & 0xff; + if (i2c_write(state->i2c, adr, mm, len + 2) < 0) + return -1; + return 0; +} + +static int Write16_0(struct drxk_state *state, u32 reg, u16 data) +{ + return Write16(state, reg, data, 0); +} + +static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) +{ + u8 adr = state->demod_address, mm[8], len; +#ifdef I2C_LONG_ADR + flags |= 0xC0; +#endif + if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { + mm[0] = (((reg << 1) & 0xFF) | 0x01); + mm[1] = ((reg >> 16) & 0xFF); + mm[2] = ((reg >> 24) & 0xFF) | flags; + mm[3] = ((reg >> 7) & 0xFF); + len = 4; + } else { + mm[0] = ((reg << 1) & 0xFF); + mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); + len = 2; + } + mm[len] = data & 0xff; + mm[len+1] = (data >> 8) & 0xff; + mm[len+2] = (data >> 16) & 0xff; + mm[len+3] = (data >> 24) & 0xff; + if (i2c_write(state->i2c, adr, mm, len+4) < 0) + return -1; + return 0; +} + +static int WriteBlock(struct drxk_state *state, u32 Address, + const int BlockSize, const u8 pBlock[], u8 Flags) +{ + int status = 0, BlkSize = BlockSize; +#ifdef I2C_LONG_ADR + Flags |= 0xC0; +#endif + while (BlkSize > 0) { + int Chunk = BlkSize > state->m_ChunkSize ? + state->m_ChunkSize : BlkSize ; + u8 *AdrBuf = &state->Chunk[0]; + u32 AdrLength = 0; + + if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { + AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); + AdrBuf[1] = ((Address >> 16) & 0xFF); + AdrBuf[2] = ((Address >> 24) & 0xFF); + AdrBuf[3] = ((Address >> 7) & 0xFF); + AdrBuf[2] |= Flags; + AdrLength = 4; + if (Chunk == state->m_ChunkSize) + Chunk -= 2; + } else { + AdrBuf[0] = ((Address << 1) & 0xFF); + AdrBuf[1] = (((Address >> 16) & 0x0F) | + ((Address >> 18) & 0xF0)); + AdrLength = 2; + } + memcpy(&state->Chunk[AdrLength], pBlock, Chunk); + status = i2c_write(state->i2c, state->demod_address, + &state->Chunk[0], Chunk+AdrLength); + if (status<0) { + printk("I2C Write error\n"); + break; + } + pBlock += Chunk; + Address += (Chunk >> 1); + BlkSize -= Chunk; + } + return status; +} + +#ifndef DRXK_MAX_RETRIES_POWERUP +#define DRXK_MAX_RETRIES_POWERUP 20 +#endif + +int PowerUpDevice(struct drxk_state *state) +{ + int status; + u8 data = 0; + u16 retryCount = 0; + + status = i2c_read1(state->i2c, state->demod_address, &data); + if (status<0) + do { + data = 0; + if (i2c_write(state->i2c, + state->demod_address, &data, 1) < 0) + printk("powerup failed\n"); + msleep(10); + retryCount++ ; + } while (i2c_read1(state->i2c, + state->demod_address, &data) < 0 && + (retryCount < DRXK_MAX_RETRIES_POWERUP)); + if (retryCount >= DRXK_MAX_RETRIES_POWERUP) + return -1; + do { + /* Make sure all clk domains are active */ + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + SIO_CC_PWD_MODE_LEVEL_NONE)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + /* Enable pll lock tests */ + CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); + state->m_currentPowerMode = DRX_POWER_UP; + } while (0); + return status; +} + + +static int init_state(struct drxk_state *state) +{ + u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBIfAgcOutputLevel = 0; + u32 ulVSBIfAgcMinLevel = 0; + u32 ulVSBIfAgcMaxLevel = 0x7FFF; + u32 ulVSBIfAgcSpeed = 3; + + u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulVSBRfAgcOutputLevel = 0; + u32 ulVSBRfAgcMinLevel = 0; + u32 ulVSBRfAgcMaxLevel = 0x7FFF; + u32 ulVSBRfAgcSpeed = 3; + u32 ulVSBRfAgcTop = 9500; + u32 ulVSBRfAgcCutOffCurrent = 4000; + + u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; + u32 ulATVIfAgcOutputLevel = 0; + u32 ulATVIfAgcMinLevel = 0; + u32 ulATVIfAgcMaxLevel = 0; + u32 ulATVIfAgcSpeed = 3; + + u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; + u32 ulATVRfAgcOutputLevel = 0; + u32 ulATVRfAgcMinLevel = 0; + u32 ulATVRfAgcMaxLevel = 0; + u32 ulATVRfAgcTop = 9500; + u32 ulATVRfAgcCutOffCurrent = 4000; + u32 ulATVRfAgcSpeed = 3; + + u32 ulQual83 = DEFAULT_MER_83; + u32 ulQual93 = DEFAULT_MER_93; + + u32 ulDVBTStaticTSClock = 1; + u32 ulDVBCStaticTSClock = 1; + + u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + + /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ + /* io_pad_cfg_mode output mode is drive always */ + /* io_pad_cfg_drive is set to power 2 (23 mA) */ + u32 ulGPIOCfg = 0x0113; + u32 ulGPIO = 0; + u32 ulSerialMode = 1; + u32 ulInvertTSClock = 0; + u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; + u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; + u32 ulDVBTBitrate = 50000000; + u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; + + u32 ulInsertRSByte = 0; + + u32 ulRfMirror = 1; + u32 ulPowerDown = 0; + + u32 ulAntennaDVBT = 1; + u32 ulAntennaDVBC = 0; + u32 ulAntennaSwitchDVBTDVBC = 0; + + state->m_hasLNA = false; + state->m_hasDVBT= false; + state->m_hasDVBC= false; + state->m_hasATV= false; + state->m_hasOOB = false; + state->m_hasAudio = false; + + state->m_ChunkSize = 124; + + state->m_oscClockFreq = 0; + state->m_smartAntInverted = false; + state->m_bPDownOpenBridge = false; + + /* real system clock frequency in kHz */ + state->m_sysClockFreq = 151875; + /* Timing div, 250ns/Psys */ + /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ + state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * + HI_I2C_DELAY) / 1000; + /* Clipping */ + if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) + state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; + state->m_HICfgWakeUpKey = (state->demod_address << 1); + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + + state->m_bPowerDown = (ulPowerDown != 0); + + state->m_DRXK_A1_PATCH_CODE = false; + state->m_DRXK_A1_ROM_CODE = false; + state->m_DRXK_A2_ROM_CODE = false; + state->m_DRXK_A3_ROM_CODE = false; + state->m_DRXK_A2_PATCH_CODE = false; + state->m_DRXK_A3_PATCH_CODE = false; + + /* Init AGC and PGA parameters */ + /* VSB IF */ + state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); + state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); + state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); + state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); + state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); + state->m_vsbPgaCfg = 140; + + /* VSB RF */ + state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); + state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); + state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); + state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); + state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); + state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); + state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); + state->m_vsbPreSawCfg.reference = 0x07; + state->m_vsbPreSawCfg.usePreSaw = true; + + state->m_Quality83percent = DEFAULT_MER_83; + state->m_Quality93percent = DEFAULT_MER_93; + if (ulQual93 <= 500 && ulQual83 < ulQual93) { + state->m_Quality83percent = ulQual83; + state->m_Quality93percent = ulQual93; + } + + /* ATV IF */ + state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); + state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); + state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); + state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); + state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); + + /* ATV RF */ + state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); + state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); + state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); + state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); + state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); + state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); + state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); + state->m_atvPreSawCfg.reference = 0x04; + state->m_atvPreSawCfg.usePreSaw = true; + + + /* DVBT RF */ + state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_dvbtRfAgcCfg.outputLevel = 0; + state->m_dvbtRfAgcCfg.minOutputLevel = 0; + state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; + state->m_dvbtRfAgcCfg.top = 0x2100; + state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; + state->m_dvbtRfAgcCfg.speed = 1; + + + /* DVBT IF */ + state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_dvbtIfAgcCfg.outputLevel = 0; + state->m_dvbtIfAgcCfg.minOutputLevel = 0; + state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; + state->m_dvbtIfAgcCfg.top = 13424; + state->m_dvbtIfAgcCfg.cutOffCurrent = 0; + state->m_dvbtIfAgcCfg.speed = 3; + state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; + state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; + // state->m_dvbtPgaCfg = 140; + + state->m_dvbtPreSawCfg.reference = 4; + state->m_dvbtPreSawCfg.usePreSaw = false; + + /* QAM RF */ + state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; + state->m_qamRfAgcCfg.outputLevel = 0; + state->m_qamRfAgcCfg.minOutputLevel = 6023; + state->m_qamRfAgcCfg.maxOutputLevel = 27000; + state->m_qamRfAgcCfg.top = 0x2380; + state->m_qamRfAgcCfg.cutOffCurrent = 4000; + state->m_qamRfAgcCfg.speed = 3; + + /* QAM IF */ + state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; + state->m_qamIfAgcCfg.outputLevel = 0; + state->m_qamIfAgcCfg.minOutputLevel = 0; + state->m_qamIfAgcCfg.maxOutputLevel = 9000; + state->m_qamIfAgcCfg.top = 0x0511; + state->m_qamIfAgcCfg.cutOffCurrent = 0; + state->m_qamIfAgcCfg.speed = 3; + state->m_qamIfAgcCfg.IngainTgtMax = 5119; + state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; + + state->m_qamPgaCfg = 140; + state->m_qamPreSawCfg.reference = 4; + state->m_qamPreSawCfg.usePreSaw = false; + + state->m_OperationMode = OM_NONE; + state->m_DrxkState = DRXK_UNINITIALIZED; + + /* MPEG output configuration */ + state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ + state->m_insertRSByte = false; /* If TRUE; insert RS byte */ + state->m_enableParallel = true; /* If TRUE; + parallel out otherwise serial */ + state->m_invertDATA = false; /* If TRUE; invert DATA signals */ + state->m_invertERR = false; /* If TRUE; invert ERR signal */ + state->m_invertSTR = false; /* If TRUE; invert STR signals */ + state->m_invertVAL = false; /* If TRUE; invert VAL signals */ + state->m_invertCLK = + (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ + state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0); + state->m_DVBCStaticCLK = + (ulDVBCStaticTSClock != 0); + /* If TRUE; static MPEG clockrate will be used; + otherwise clockrate will adapt to the bitrate of the TS */ + + state->m_DVBTBitrate = ulDVBTBitrate; + state->m_DVBCBitrate = ulDVBCBitrate; + + state->m_TSDataStrength = (ulTSDataStrength & 0x07); + state->m_TSClockkStrength = (ulTSClockkStrength & 0x07); + + /* Maximum bitrate in b/s in case static clockrate is selected */ + state->m_mpegTsStaticBitrate = 19392658; + state->m_disableTEIhandling = false; + + if (ulInsertRSByte) + state->m_insertRSByte = true; + + state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; + if (ulMpegLockTimeOut < 10000) + state->m_MpegLockTimeOut = ulMpegLockTimeOut; + state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; + if (ulDemodLockTimeOut < 10000) + state->m_DemodLockTimeOut = ulDemodLockTimeOut; + + // QAM defaults + state->m_Constellation = DRX_CONSTELLATION_AUTO; + state->m_qamInterleaveMode = DRXK_QAM_I12_J17; + state->m_fecRsPlen = 204*8; /* fecRsPlen annex A*/ + state->m_fecRsPrescale = 1; + + state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; + state->m_agcFastClipCtrlDelay = 0; + + state->m_GPIOCfg = (ulGPIOCfg); + state->m_GPIO = (ulGPIO == 0 ? 0 : 1); + + state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1); + state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1); + state->m_AntennaSwitchDVBTDVBC = + (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1); + + state->m_bPowerDown = false; + state->m_currentPowerMode = DRX_POWER_DOWN; + + state->m_enableParallel = (ulSerialMode == 0); + + state->m_rfmirror = (ulRfMirror == 0); + state->m_IfAgcPol = false; + return 0; +} + +static int DRXX_Open(struct drxk_state *state) +{ + int status = 0; + u32 jtag = 0; + u16 bid = 0; + u16 key = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + /* Check device id */ + CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); + CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); + } while(0); + return status; +} + +static int GetDeviceCapabilities(struct drxk_state *state) +{ + u16 sioPdrOhwCfg = 0; + u32 sioTopJtagidLo = 0; + int status; + + do { + /* driver 0.9.0 */ + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + CHK_ERROR(Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + + switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { + case 0: + /* ignore (bypass ?) */ + break; + case 1: + /* 27 MHz */ + state->m_oscClockFreq = 27000; + break; + case 2: + /* 20.25 MHz */ + state->m_oscClockFreq = 20250; + break; + case 3: + /* 4 MHz */ + state->m_oscClockFreq = 20250; + break; + default: + return -1; + } + /* + Determine device capabilities + Based on pinning v14 + */ + CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, + &sioTopJtagidLo, 0)); + /* driver 0.9.0 */ + switch((sioTopJtagidLo >> 29) & 0xF) { + case 0: + state->m_deviceSpin = DRXK_SPIN_A1; + break; + case 2: + state->m_deviceSpin = DRXK_SPIN_A2; + break; + case 3: + state->m_deviceSpin = DRXK_SPIN_A3; + break; + default: + state->m_deviceSpin = DRXK_SPIN_UNKNOWN; + status = -1; + break; + } + switch ((sioTopJtagidLo>>12)&0xFF) { + case 0x13: + /* typeId = DRX3913K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = false; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = false; + state->m_hasGPIO1 = false; + state->m_hasIRQN = false; + break; + case 0x15: + /* typeId = DRX3915K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x16: + /* typeId = DRX3916K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x18: + /* typeId = DRX3918K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x21: + /* typeId = DRX3921K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x23: + /* typeId = DRX3923K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x25: + /* typeId = DRX3925K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + case 0x26: + /* typeId = DRX3926K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; + break; + default: + printk("DeviceID not supported = %02x\n", + ((sioTopJtagidLo>>12)&0xFF)); + status = -1; + break; + } + } while(0); + return status; +} + +static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) +{ + int status; + bool powerdown_cmd; + + //printk("%s\n", __FUNCTION__); + + /* Write command */ + status = Write16_0(state, SIO_HI_RA_RAM_CMD__A, cmd); + if (status < 0) + return status; + if (cmd == SIO_HI_RA_RAM_CMD_RESET) + msleep(1); + + powerdown_cmd = + (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && + ((state->m_HICfgCtrl) & + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); + if (powerdown_cmd == false) { + /* Wait until command rdy */ + u32 retryCount = 0; + u16 waitCmd; + + do { + msleep(1); + retryCount += 1; + status = Read16(state, SIO_HI_RA_RAM_CMD__A, + &waitCmd, 0); + } while ((status < 0) && + (retryCount < DRXK_MAX_RETRIES) && (waitCmd != 0)); + + if (status == 0) + status = Read16(state, SIO_HI_RA_RAM_RES__A, + pResult, 0); + } + return status; +} + +static int HI_CfgCommand(struct drxk_state *state) +{ + int status; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_6__A, + state->m_HICfgTimeout)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_5__A, + state->m_HICfgCtrl)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_4__A, + state->m_HICfgWakeUpKey)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_3__A, + state->m_HICfgBridgeDelay)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_2__A, + state->m_HICfgTimingDiv)); + CHK_ERROR(Write16_0(state,SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); + + state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + } while(0); + mutex_unlock(&state->mutex); + return status; +} + +static int InitHI(struct drxk_state *state) +{ + state->m_HICfgWakeUpKey = (state->demod_address<<1); + state->m_HICfgTimeout = 0x96FF; + /* port/bridge/power down ctrl */ + state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; + return HI_CfgCommand(state); +} + +static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) +{ + int status = -1; + u16 sioPdrMclkCfg = 0; + u16 sioPdrMdxCfg = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* MPEG TS pad configuration */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); + + if (mpegEnable == false) { + /* Set MPEG TS pads to inputmode */ + CHK_ERROR(Write16_0(state, + SIO_PDR_MSTRT_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MERR_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MCLK_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, + SIO_PDR_MVAL_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000)); + } else { + /* Enable MPEG output */ + sioPdrMdxCfg = + ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); + sioPdrMclkCfg = ((state->m_TSClockkStrength << + SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); + + CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, + 0x0000)); // Disable + CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, + 0x0000)); // Disable + if (state->m_enableParallel == true) { + /* paralel -> enable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + sioPdrMdxCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + sioPdrMdxCfg)); + } else { + sioPdrMdxCfg = ((state->m_TSDataStrength << + SIO_PDR_MD0_CFG_DRIVE__B) | + 0x0003); + /* serial -> disable MD1 to MD7 */ + CHK_ERROR(Write16_0(state, SIO_PDR_MD1_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD2_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD3_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD4_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD5_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD6_CFG__A, + 0x0000)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD7_CFG__A, + 0x0000)); + } + CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, + sioPdrMclkCfg)); + CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, + sioPdrMdxCfg)); + } + /* Enable MB output over MPEG pads and ctl input */ + CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); + /* Write nomagic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while(0); + return status; +} + +static int MPEGTSDisable(struct drxk_state *state) +{ + return MPEGTSConfigurePins(state, false); +} + +static int BLChainCmd(struct drxk_state *state, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + int status; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, + SIO_BL_MODE_CHAIN)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, + romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, + nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, + SIO_BL_ENABLE_ON)); + end=jiffies+msecs_to_jiffies(timeOut); + + do { + msleep(1); + CHK_ERROR(Read16(state, SIO_BL_STATUS__A, + &blStatus, 0)); + } while ((blStatus == 0x1) && + ((time_is_after_jiffies(end)))); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; +} + + +static int DownloadMicrocode(struct drxk_state *state, + const u8 pMCImage[], + u32 Length) +{ + const u8 *pSrc = pMCImage; + u16 Flags; + u16 Drain; + u32 Address; + u16 nBlocks; + u16 BlockSize; + u16 BlockCRC; + u32 offset = 0; + u32 i; + int status; + + /* down the drain (we don care about MAGIC_WORD) */ + Drain = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + nBlocks = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + for (i = 0; i < nBlocks; i += 1) { + Address = (pSrc[0] << 24) | (pSrc[1] << 16) | + (pSrc[2] << 8) | pSrc[3]; + pSrc += sizeof(u32); offset += sizeof(u32); + + BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); + pSrc += sizeof(u16); offset += sizeof(u16); + + Flags = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + BlockCRC = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + status = WriteBlock(state, Address, BlockSize, pSrc, 0); + if (status<0) + break; + pSrc += BlockSize; + offset += BlockSize; + } + return status; +} + +static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) +{ + int status; + u16 data = 0; + u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; + u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; + unsigned long end; + + if (enable == false) { + desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; + desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; + } + + status = (Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + + if (data == desiredStatus) { + /* tokenring already has correct status */ + return status; + } + /* Disable/enable dvbt tokenring bridge */ + status = Write16_0(state,SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); + + end=jiffies+msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); + do + CHK_ERROR(Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); + while ((data != desiredStatus) && + ((time_is_after_jiffies(end)))); + if (data != desiredStatus) { + printk("SIO not ready\n"); + return -1; + } + return status; +} + +static int MPEGTSStop(struct drxk_state *state) +{ + int status = 0; + u16 fecOcSncMode = 0; + u16 fecOcIprMode = 0; + + do { + /* Gracefull shutdown (byte boundaries) */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + + /* Suppress MCLK during absence of data */ + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); + fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode)); + } while (0); + return status; +} + +static int scu_command(struct drxk_state *state, + u16 cmd, u8 parameterLen, + u16 * parameter, u8 resultLen, u16 * result) +{ +#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 +#error DRXK register mapping no longer compatible with this routine! +#endif + u16 curCmd = 0; + int status; + unsigned long end; + + if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || + ((resultLen > 0) && (result == NULL))) + return -1; + + mutex_lock(&state->mutex); + do { + /* assume that the command register is ready + since it is checked afterwards */ + u8 buffer[34]; + int cnt = 0, ii; + + for (ii=parameterLen-1; ii >= 0; ii -= 1) { + buffer[cnt++] = (parameter[ii] & 0xFF); + buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); + } + buffer[cnt++] = (cmd & 0xFF); + buffer[cnt++] = ((cmd >> 8) & 0xFF); + + WriteBlock(state, SCU_RAM_PARAM_0__A - + (parameterLen-1), cnt, buffer, 0x00); + /* Wait until SCU has processed command */ + end=jiffies+msecs_to_jiffies(DRXK_MAX_WAITTIME); + do { + msleep(1); + CHK_ERROR(Read16_0(state, SCU_RAM_COMMAND__A, &curCmd)); + } while (! (curCmd == DRX_SCU_READY) && + (time_is_after_jiffies(end))); + if (curCmd != DRX_SCU_READY) { + printk("SCU not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* read results */ + if ((resultLen > 0) && (result != NULL)) { + s16 err; + int ii; + + for(ii=resultLen-1; ii >= 0; ii -= 1) { + CHK_ERROR(Read16_0(state, + SCU_RAM_PARAM_0__A - ii, + &result[ii])); + } + + /* Check if an error was reported by SCU */ + err = (s16)result[0]; + + /* check a few fixed error codes */ + if (err == SCU_RESULT_UNKSTD) { + printk("SCU_RESULT_UNKSTD\n"); + mutex_unlock(&state->mutex); + return -1; + } else if (err == SCU_RESULT_UNKCMD) { + printk("SCU_RESULT_UNKCMD\n"); + mutex_unlock(&state->mutex); + return -1; + } + /* here it is assumed that negative means error, + and positive no error */ + else if (err < 0) { + printk("%s ERROR\n", __FUNCTION__); + mutex_unlock(&state->mutex); + return -1; + } + } + } while(0); + mutex_unlock(&state->mutex); + if (status<0) + { + printk("%s: status = %d\n", __FUNCTION__, status); + } + + return status; +} + +static int SetIqmAf(struct drxk_state *state, bool active) +{ + u16 data = 0; + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",active)); + //printk("%s\n", __FUNCTION__); + + do + { + /* Configure IQM */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data));; + if (!active) { + data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY + | IQM_AF_STDBY_STDBY_AMP_STANDBY + | IQM_AF_STDBY_STDBY_PD_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY + | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY + ); + // break; + //default: + // break; + //} + } else /* active */ { + data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY) + & (~IQM_AF_STDBY_STDBY_AMP_STANDBY) + & (~IQM_AF_STDBY_STDBY_PD_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) + ); + // break; + //default: + // break; + //} + } + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + }while(0); + return status; +} + +static int CtrlPowerMode(struct drxk_state *state, + pDRXPowerMode_t mode) +{ + int status = 0; + u16 sioCcPwdMode = 0; + + //printk("%s\n", __FUNCTION__); + /* Check arguments */ + if (mode == NULL) + return -1; + + switch (*mode) { + case DRX_POWER_UP: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; + break; + case DRXK_POWER_DOWN_OFDM: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; + break; + case DRXK_POWER_DOWN_CORE: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; + break; + case DRXK_POWER_DOWN_PLL: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; + break; + case DRX_POWER_DOWN: + sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; + break; + default: + /* Unknow sleep mode */ + return -1; + break; + } + + /* If already in requested power mode, do nothing */ + if (state->m_currentPowerMode == *mode) + return 0; + + /* For next steps make sure to start from DRX_POWER_UP mode */ + if (state->m_currentPowerMode != DRX_POWER_UP) + { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); + } while(0); + } + + if (*mode == DRX_POWER_UP) { + /* Restore analog & pin configuartion */ + } else { + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected + to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + /* stop all comm_exec */ + /* Stop and power down previous standard */ + do { + switch (state->m_OperationMode) { + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state, false)); + break; + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + break; + default: + break; + } + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, + sioCcPwdMode)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, + SIO_CC_UPDATE_KEY)); + + if (*mode != DRXK_POWER_DOWN_OFDM) { + state->m_HICfgCtrl |= + SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + } while(0); + } + state->m_currentPowerMode = *mode; + return (status); +} + +static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 cmdResult = 0; + u16 data = 0; + int status; + + do { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) { + /* Send OFDM stop command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0, NULL, 1, &cmdResult)); + /* Send OFDM reset command */ + CHK_ERROR(scu_command(state, + SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_RESET, + 0, NULL, 1, &cmdResult)); + } + + /* Reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, + OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, + OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, + IQM_COMM_EXEC_B_STOP)); + + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state,false)); + + /* powerdown to OFDM mode */ + if (setPowerMode) { + CHK_ERROR(CtrlPowerMode(state,&powerMode)); + } + } while(0); + return status; +} + +static int SetOperationMode(struct drxk_state *state, enum OperationMode oMode) +{ + int status = 0; + + /* + Stop and power down previous standard + TODO investigate total power down instead of partial + power down depending on "previous" standard. + */ + do { + /* disable HW lock indicator */ + CHK_ERROR (Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + if (state->m_OperationMode != oMode) { + switch (state->m_OperationMode) { + // OM_NONE was added for start up + case OM_NONE: + break; + case OM_DVBT: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownDVBT(state,true)); + state->m_OperationMode = OM_NONE; + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(PowerDownQAM(state)); + state->m_OperationMode = OM_NONE; + break; + default: + status = -1; + } + CHK_ERROR(status); + + /* + Power up new standard + */ + switch (oMode) + { + case OM_DVBT: + state->m_OperationMode = oMode; + CHK_ERROR(SetDVBTStandard(state, oMode)); + break; + case OM_QAM_ITU_B: + status = -1; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + state->m_OperationMode = oMode; + CHK_ERROR(SetQAMStandard(state,oMode)); + break; + default: + status = -1; + } + } + CHK_ERROR(status); + } while(0); + return 0; +} + +static int Start(struct drxk_state *state, s32 offsetFreq, + s32 IntermediateFrequency) +{ + int status; + + do { + u16 IFreqkHz; + s32 OffsetkHz = offsetFreq / 1000; + + if (state->m_DrxkState != DRXK_STOPPED && + state->m_DrxkState != DRXK_DTV_STARTED) { + status = -1; + break; + } + state->m_bMirrorFreqSpect = + (state->param.inversion == INVERSION_ON); + + if (IntermediateFrequency < 0) { + state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; + IntermediateFrequency = -IntermediateFrequency; + } + + switch(state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(SetQAM(state,IFreqkHz, OffsetkHz)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + case OM_DVBT: + IFreqkHz = (IntermediateFrequency / 1000); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(SetDVBT(state,IFreqkHz, OffsetkHz)); + CHK_ERROR(DVBTStart(state)); + state->m_DrxkState = DRXK_DTV_STARTED; + break; + default: + break; + } + } while(0); + return status; +} + +static int ShutDown(struct drxk_state *state) +{ + MPEGTSStop(state); + return 0; +} + +static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, u32 Time) +{ + int status; + + if (pLockStatus == NULL) + return -1; + + *pLockStatus = NOT_LOCKED; + + /* define the SCU command code */ + switch (state->m_OperationMode) { + case OM_QAM_ITU_A: + case OM_QAM_ITU_B: + case OM_QAM_ITU_C: + status = GetQAMLockStatus(state, pLockStatus); + break; + case OM_DVBT: + status = GetDVBTLockStatus(state, pLockStatus); + break; + default: + break; + } + return status; +} + +static int MPEGTSStart(struct drxk_state *state) +{ + int status = 0; + + u16 fecOcSncMode = 0; + + do { + /* Allow OC to sync again */ + CHK_ERROR(Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); + fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; + CHK_ERROR(Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); + } while (0); + return status; +} + +static int MPEGTSDtoInit(struct drxk_state *state) +{ + int status = -1; + + do { + /* Rate integration settings */ + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); + CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); + CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); + + /* Additional configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); + } while (0); + return status; +} + +static int MPEGTSDtoSetup(struct drxk_state *state, enum OperationMode oMode) +{ + int status = -1; + + u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ + u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ + u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ + u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ + u16 fecOcTmdMode = 0; + u16 fecOcTmdIntUpdRate = 0; + u32 maxBitRate = 0; + bool staticCLK = false; + + do { + /* Check insertion of the Reed-Solomon parity bytes */ + CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); + CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, + &fecOcRegIprMode)); + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); + if (state->m_insertRSByte == true) { + /* enable parity symbol forward */ + fecOcRegMode |= FEC_OC_MODE_PARITY__M; + /* MVAL disable during parity bytes */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; + /* TS burst length to 204 */ + fecOcDtoBurstLen = 204 ; + } + + /* Check serial or parrallel output */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); + if (state->m_enableParallel == false) { + /* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; + } + + switch (oMode) { + case OM_DVBT: + maxBitRate = state->m_DVBTBitrate; + fecOcTmdMode = 3; + fecOcRcnCtlRate = 0xC00000; + staticCLK = state->m_DVBTStaticCLK; + break; + case OM_QAM_ITU_A: /* fallthrough */ + case OM_QAM_ITU_C: + fecOcTmdMode = 0x0004; + fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ + maxBitRate = state->m_DVBCBitrate; + staticCLK = state->m_DVBCStaticCLK; + break; + default: + status = -1; + } /* switch (standard) */ + CHK_ERROR(status); + + /* Configure DTO's */ + if (staticCLK ) { + u32 bitRate = 0; + + /* Rational DTO for MCLK source (static MCLK rate), + Dynamic DTO for optimal grouping + (avoid intra-packet gaps), + DTO offset enable to sync TS burst with MSTRT */ + fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | + FEC_OC_DTO_MODE_OFFSET_ENABLE__M); + fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | + FEC_OC_FCT_MODE_VIRT_ENA__M); + + /* Check user defined bitrate */ + bitRate = maxBitRate; + if (bitRate > 75900000UL) + { /* max is 75.9 Mb/s */ + bitRate = 75900000UL; + } + /* Rational DTO period: + dto_period = (Fsys / bitrate) - 2 + + Result should be floored, + to make sure >= requested bitrate + */ + fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) + * 1000) / bitRate); + if (fecOcDtoPeriod <= 2) + fecOcDtoPeriod = 0; + else + fecOcDtoPeriod -= 2; + fecOcTmdIntUpdRate = 8; + } else { + /* (commonAttr->staticCLK == false) => dynamic mode */ + fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; + fecOcFctMode = FEC_OC_FCT_MODE__PRE; + fecOcTmdIntUpdRate = 5; + } + + /* Write appropriate registers with requested configuration */ + CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, + fecOcDtoBurstLen)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, + fecOcDtoPeriod)); + CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, + fecOcDtoMode)); + CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, + fecOcFctMode)); + CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, + fecOcRegMode)); + CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, + fecOcRegIprMode)); + + /* Rate integration settings */ + CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, + fecOcRcnCtlRate ,0)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, + fecOcTmdIntUpdRate)); + CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, + fecOcTmdMode)); + } while (0); + return status; +} + +static int MPEGTSConfigurePolarity(struct drxk_state *state) +{ + int status; + u16 fecOcRegIprInvert = 0; + + /* Data mask for the output data byte */ + u16 InvertDataMask = + FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | + FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | + FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | + FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M; + + /* Control selective inversion of output bits */ + fecOcRegIprInvert &= (~(InvertDataMask)); + if (state->m_invertDATA == true) + fecOcRegIprInvert |= InvertDataMask; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); + if (state->m_invertERR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); + if (state->m_invertSTR == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); + if (state->m_invertVAL == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; + fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); + if (state->m_invertCLK == true) + fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; + status = Write16_0(state,FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); + return status; +} + +#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 + +static int SetAgcRf(struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + int status = 0; + struct SCfgAgc *pIfAgcSettings; + + if (pAgcCfg == NULL) + return -1; + + do { + u16 data = 0; + + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, + &data, 0)); + + /* Enable SCU RF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + + /* Polarity */ + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, + &data, 0)); + + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_RAGC_RED__B) + & SCU_RAM_AGC_KI_RED_RAGC_RED__M); + + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_KI_RED__A, data)); + + if (IsDVBT(state)) + pIfAgcSettings = &state->m_dvbtIfAgcCfg; + else if (IsQAM(state)) + pIfAgcSettings = &state->m_qamIfAgcCfg; + else + pIfAgcSettings = &state->m_atvIfAgcCfg; + if (pIfAgcSettings == NULL) + return -1; + + /* Set TOP, only if IF-AGC is in AUTO mode */ + if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->top)); + + /* Cut-Off current */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_RF_IACCU_HI_CO__A, + pAgcCfg->cutOffCurrent)); + + /* Max. output level */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, + pAgcCfg->maxOutputLevel)); + + break; + + case DRXK_AGC_CTRL_USER: + /* Enable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + if (state->m_RfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, + data)); + + /* SCU c.o.c. to 0, enabling full control range */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, + 0)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + /* Disable RF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU RF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + + default: + return -1; + + } /* switch (agcsettings->ctrlMode) */ + } while(0); + return status; +} + +#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 + +static int SetAgcIf (struct drxk_state *state, + struct SCfgAgc *pAgcCfg, bool isDTV) +{ + u16 data = 0; + int status = 0; + struct SCfgAgc *pRfAgcSettings; + + do { + switch (pAgcCfg->ctrlMode) { + case DRXK_AGC_CTRL_AUTO: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, + &data)); + + /* Enable SCU IF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Set speed (using complementary reduction value) */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, + &data)); + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; + data |= (~(pAgcCfg->speed << + SCU_RAM_AGC_KI_RED_IAGC_RED__B) + & SCU_RAM_AGC_KI_RED_IAGC_RED__M); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A , + data)); + + if (IsQAM(state)) + pRfAgcSettings = &state->m_qamRfAgcCfg; + else + pRfAgcSettings = &state->m_atvRfAgcCfg; + if (pRfAgcSettings == NULL) + return -1; + /* Restore TOP */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pRfAgcSettings->top)); + break; + + case DRXK_AGC_CTRL_USER: + + /* Enable IF AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + + /* Disable SCU IF AGC loop */ + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + + /* Polarity */ + if (state->m_IfAgcPol) + data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + + /* Write value to output pin */ + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + pAgcCfg->outputLevel)); + break; + + case DRXK_AGC_CTRL_OFF: + + /* Disable If AGC DAC */ + CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A , &data)); + data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; + CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A , data)); + + /* Disable SCU IF AGC loop */ + CHK_ERROR(Read16_0(state, + SCU_RAM_AGC_CONFIG__A, &data)); + data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; + CHK_ERROR(Write16_0(state, + SCU_RAM_AGC_CONFIG__A, data)); + break; + } /* switch (agcSettingsIf->ctrlMode) */ + + /* always set the top to support + configurations without if-loop */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + pAgcCfg->top)); + + + } while(0); + return status; +} + +static int ReadIFAgc(struct drxk_state *state, u32 *pValue) +{ + u16 agcDacLvl; + int status = Read16_0(state, IQM_AF_AGC_IF__A, &agcDacLvl); + + *pValue = 0; + + if (status==0) { + u16 Level = 0; + if (agcDacLvl > DRXK_AGC_DAC_OFFSET) + Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; + if (Level < 14000) + *pValue = (14000 - Level) / 4 ; + else + *pValue = 0; + } + return status; +} + +static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + do { + /* MER calculation */ + u16 qamSlErrPower = 0; /* accum. error between + raw and sliced symbols */ + u32 qamSlSigPower = 0; /* used for MER, depends of + QAM constellation */ + u32 qamSlMer = 0; /* QAM MER */ + + /* get the register value needed for MER */ + CHK_ERROR(Read16_0(state,QAM_SL_ERR_POWER__A, &qamSlErrPower)); + + switch(state->param.u.qam.modulation) { + case QAM_16: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; + break; + case QAM_32: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; + break; + case QAM_64: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; + break; + case QAM_128: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; + break; + default: + case QAM_256: + qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; + break; + } + + if (qamSlErrPower > 0) { + qamSlMer = Log10Times100(qamSlSigPower) - + Log10Times100((u32) qamSlErrPower); + } + *pSignalToNoise = qamSlMer; + } while(0); + return status; +} + +static int GetDVBTSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + int status = 0; + + u16 regData = 0; + u32 EqRegTdSqrErrI = 0; + u32 EqRegTdSqrErrQ = 0; + u16 EqRegTdSqrErrExp = 0; + u16 EqRegTdTpsPwrOfs = 0; + u16 EqRegTdReqSmbCnt = 0; + u32 tpsCnt = 0; + u32 SqrErrIQ = 0; + u32 a = 0; + u32 b = 0; + u32 c = 0; + u32 iMER = 0; + u16 transmissionParams = 0; + + do { + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, + &EqRegTdTpsPwrOfs)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, + &EqRegTdReqSmbCnt)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, + &EqRegTdSqrErrExp)); + CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, + ®Data)); + /* Extend SQR_ERR_I operational range */ + EqRegTdSqrErrI = (u32) regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrI < 0x00000FFFUL)) { + EqRegTdSqrErrI += 0x00010000UL; + } + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A, + ®Data)); + /* Extend SQR_ERR_Q operational range */ + EqRegTdSqrErrQ = (u32)regData; + if ((EqRegTdSqrErrExp > 11) && + (EqRegTdSqrErrQ < 0x00000FFFUL)) + EqRegTdSqrErrQ += 0x00010000UL; + + CHK_ERROR(Read16_0(state,OFDM_SC_RA_RAM_OP_PARAM__A, + &transmissionParams)); + + /* Check input data for MER */ + + /* MER calculation (in 0.1 dB) without math.h */ + if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) + iMER = 0; + else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { + /* No error at all, this must be the HW reset value + * Apparently no first measurement yet + * Set MER to 0.0 */ + iMER = 0; + } else { + SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << + EqRegTdSqrErrExp; + if ((transmissionParams & + OFDM_SC_RA_RAM_OP_PARAM_MODE__M) + == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) + tpsCnt = 17; + else + tpsCnt = 68; + + /* IMER = 100 * log10 (x) + where x = (EqRegTdTpsPwrOfs^2 * + EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ + + => IMER = a + b -c + where a = 100 * log10 (EqRegTdTpsPwrOfs^2) + b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) + c = 100 * log10 (SqrErrIQ) + */ + + /* log(x) x = 9bits * 9bits->18 bits */ + a = Log10Times100(EqRegTdTpsPwrOfs*EqRegTdTpsPwrOfs); + /* log(x) x = 16bits * 7bits->23 bits */ + b = Log10Times100(EqRegTdReqSmbCnt*tpsCnt); + /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ + c = Log10Times100(SqrErrIQ); + + iMER = a + b; + /* No negative MER, clip to zero */ + if (iMER > c) + iMER -= c; + else + iMER = 0; + } + *pSignalToNoise = iMER; + } while(0); + + return status; +} + +static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) +{ + *pSignalToNoise = 0; + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTSignalToNoise(state, pSignalToNoise); + case OM_QAM_ITU_A: + case OM_QAM_ITU_C: + return GetQAMSignalToNoise(state, pSignalToNoise); + default: + break; + } + return 0; +} + +#if 0 +static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) +{ + /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ + int status = 0; + + static s32 QE_SN[] = + { + 51, // QPSK 1/2 + 69, // QPSK 2/3 + 79, // QPSK 3/4 + 89, // QPSK 5/6 + 97, // QPSK 7/8 + 108, // 16-QAM 1/2 + 131, // 16-QAM 2/3 + 146, // 16-QAM 3/4 + 156, // 16-QAM 5/6 + 160, // 16-QAM 7/8 + 165, // 64-QAM 1/2 + 187, // 64-QAM 2/3 + 202, // 64-QAM 3/4 + 216, // 64-QAM 5/6 + 225, // 64-QAM 7/8 + }; + + *pQuality = 0; + + do { + s32 SignalToNoise = 0; + u16 Constellation = 0; + u16 CodeRate = 0; + u32 SignalToNoiseRel; + u32 BERQuality; + + CHK_ERROR(GetDVBTSignalToNoise(state,&SignalToNoise)); + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CONST__A, + &Constellation)); + Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; + + CHK_ERROR(Read16_0(state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A, + &CodeRate)); + CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; + + if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || + CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) + break; + SignalToNoiseRel = SignalToNoise - + QE_SN[Constellation * 5 + CodeRate]; + BERQuality = 100; + + if (SignalToNoiseRel < -70) *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + return 0; +}; + +static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) +{ + int status = 0; + *pQuality = 0; + + do { + u32 SignalToNoise = 0; + u32 BERQuality = 100; + u32 SignalToNoiseRel = 0; + + CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); + + switch(state->param.u.qam.modulation) { + case QAM_16: + SignalToNoiseRel = SignalToNoise - 200; + break; + case QAM_32: + SignalToNoiseRel = SignalToNoise - 230; + break; /* Not in NorDig */ + case QAM_64: + SignalToNoiseRel = SignalToNoise - 260; + break; + case QAM_128: + SignalToNoiseRel = SignalToNoise - 290; + break; + default: + case QAM_256: + SignalToNoiseRel = SignalToNoise - 320; + break; + } + + if (SignalToNoiseRel < -70) + *pQuality = 0; + else if (SignalToNoiseRel < 30) + *pQuality = ((SignalToNoiseRel + 70) * + BERQuality) / 100; + else + *pQuality = BERQuality; + } while(0); + + return status; +} + +static int GetQuality(struct drxk_state *state, s32 *pQuality) +{ + switch(state->m_OperationMode) { + case OM_DVBT: + return GetDVBTQuality(state, pQuality); + case OM_QAM_ITU_A: + return GetDVBCQuality(state, pQuality); + default: + break; + } + + return 0; +} +#endif + +/* Free data ram in SIO HI */ +#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define SIO_HI_RA_RAM_USR_END__A 0x420060 + +#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A) +#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7) +#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ +#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE + +#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F) +#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) +#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) + +static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) +{ + int status; + + if (state->m_DrxkState == DRXK_UNINITIALIZED) + return -1; + if (state->m_DrxkState == DRXK_POWERED_DOWN) + return -1; + + do { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, + SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); + if (bEnableBridge) { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); + } else { + CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, + SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); + } + + CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL,0)); + } while(0); + return status; +} + +static int SetPreSaw(struct drxk_state *state, struct SCfgPreSaw *pPreSawCfg) +{ + int status; + + if ((pPreSawCfg == NULL) || (pPreSawCfg->reference>IQM_AF_PDREF__M)) + return -1; + + status = Write16_0(state, IQM_AF_PDREF__A, pPreSawCfg->reference); + return status; +} + +static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, + u16 romOffset, u16 nrOfElements, u32 timeOut) +{ + u16 blStatus = 0; + u16 offset = (u16)((targetAddr >> 0) & 0x00FFFF); + u16 blockbank = (u16)((targetAddr >> 16) & 0x000FFF); + int status ; + unsigned long end; + + mutex_lock(&state->mutex); + do { + CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); + CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); + CHK_ERROR(Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements)); + CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); + + end=jiffies+msecs_to_jiffies(timeOut); + do { + CHK_ERROR(Read16_0(state, SIO_BL_STATUS__A, &blStatus)); + } while ((blStatus == 0x1) && + time_is_after_jiffies(end)); + if (blStatus == 0x1) { + printk("SIO not ready\n"); + mutex_unlock(&state->mutex); + return -1; + } + } while(0); + mutex_unlock(&state->mutex); + return status; + +} + +static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) +{ + u16 data = 0; + int status; + + do { + /* Start measurement */ + CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, + IQM_AF_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state,IQM_AF_START_LOCK__A, 1)); + + *count = 0; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE0__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE1__A, &data)); + if (data == 127) + *count = *count+1; + CHK_ERROR(Read16_0(state,IQM_AF_PHASE2__A, &data)); + if (data == 127) + *count = *count+1; + } while(0); + return status; +} + +static int ADCSynchronization(struct drxk_state *state) +{ + u16 count = 0; + int status; + + do { + CHK_ERROR(ADCSyncMeasurement(state, &count)); + + if (count==1) { + /* Try sampling on a diffrent edge */ + u16 clkNeg = 0; + + CHK_ERROR(Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg)); + if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; + } else { + clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); + clkNeg |= + IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; + } + CHK_ERROR(Write16_0(state, IQM_AF_CLKNEG__A, clkNeg)); + CHK_ERROR(ADCSyncMeasurement(state, &count)); + } + + if (count < 2) + status = -1; + } while (0); + return status; +} + +static int SetFrequencyShifter(struct drxk_state *state, + u16 intermediateFreqkHz, + s32 tunerFreqOffset, + bool isDTV) +{ + bool selectPosImage = false; + u32 rfFreqResidual = tunerFreqOffset; + u32 fmFrequencyShift = 0; + bool tunerMirror = !state->m_bMirrorFreqSpect; + u32 adcFreq; + bool adcFlip; + int status; + u32 ifFreqActual; + u32 samplingFrequency = (u32)(state->m_sysClockFreq / 3); + u32 frequencyShift; + bool imageToSelect; + + /* + Program frequency shifter + No need to account for mirroring on RF + */ + if (isDTV) { + if ((state->m_OperationMode == OM_QAM_ITU_A) || + (state->m_OperationMode == OM_QAM_ITU_C) || + (state->m_OperationMode == OM_DVBT)) + selectPosImage = true; + else + selectPosImage = false; + } + if (tunerMirror) + /* tuner doesn't mirror */ + ifFreqActual = intermediateFreqkHz + + rfFreqResidual + fmFrequencyShift; + else + /* tuner mirrors */ + ifFreqActual = intermediateFreqkHz - + rfFreqResidual - fmFrequencyShift; + if (ifFreqActual > samplingFrequency / 2) { + /* adc mirrors */ + adcFreq = samplingFrequency - ifFreqActual; + adcFlip = true; + } else { + /* adc doesn't mirror */ + adcFreq = ifFreqActual; + adcFlip = false; + } + + frequencyShift = adcFreq; + imageToSelect = state->m_rfmirror ^ tunerMirror ^ + adcFlip ^ selectPosImage; + state->m_IqmFsRateOfs = Frac28a((frequencyShift), samplingFrequency); + + if (imageToSelect) + state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; + + /* Program frequency shifter with tuner offset compensation */ + /* frequencyShift += tunerFreqOffset; TODO */ + status = Write32(state, IQM_FS_RATE_OFS_LO__A , + state->m_IqmFsRateOfs, 0); + return status; +} + +static int InitAGC(struct drxk_state *state, bool isDTV) +{ + u16 ingainTgt = 0; + u16 ingainTgtMin = 0; + u16 ingainTgtMax = 0; + u16 clpCyclen = 0; + u16 clpSumMin = 0; + u16 clpDirTo = 0; + u16 snsSumMin = 0; + u16 snsSumMax = 0; + u16 clpSumMax = 0; + u16 snsDirTo = 0; + u16 kiInnergainMin = 0; + u16 ifIaccuHiTgt = 0; + u16 ifIaccuHiTgtMin = 0; + u16 ifIaccuHiTgtMax = 0; + u16 data = 0; + u16 fastClpCtrlDelay = 0; + u16 clpCtrlMode = 0; + int status = 0; + + do { + /* Common settings */ + snsSumMax = 1023; + ifIaccuHiTgtMin = 2047; + clpCyclen = 500; + clpSumMax = 1023; + + if (IsQAM(state)) { + /* Standard specific settings */ + clpSumMin = 8; + clpDirTo = (u16) - 9; + clpCtrlMode = 0; + snsSumMin = 8; + snsDirTo = (u16) - 9; + kiInnergainMin = (u16) - 1030; + } else + status = -1; + CHK_ERROR((status)); + if (IsQAM(state)) { + ifIaccuHiTgtMax = 0x2380; + ifIaccuHiTgt = 0x2380; + ingainTgtMin = 0x0511; + ingainTgt = 0x0511; + ingainTgtMax = 5119; + fastClpCtrlDelay = + state->m_qamIfAgcCfg.FastClipCtrlDelay; + } else { + ifIaccuHiTgtMax = 0x1200; + ifIaccuHiTgt = 0x1200; + ingainTgtMin = 13424; + ingainTgt = 13424; + ingainTgtMax = 30000; + fastClpCtrlDelay = + state->m_dvbtIfAgcCfg.FastClipCtrlDelay; + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + fastClpCtrlDelay)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, + clpCtrlMode)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, + ingainTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, + ingainTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + ingainTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, + ifIaccuHiTgtMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, + ifIaccuHiTgtMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, + clpSumMax)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, + snsSumMax)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, + kiInnergainMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, + ifIaccuHiTgt)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, + clpCyclen)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, + 1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, + (u16) -1023)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, + 50)); + + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, + 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, + clpSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, + snsSumMin)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, + clpDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, + snsDirTo)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); + + /* Initialize inner-loop KI gain factors */ + CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); + if (IsQAM(state)) { + data = 0x0657; + data &= ~SCU_RAM_AGC_KI_RF__M; + data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B); + data &= ~SCU_RAM_AGC_KI_IF__M; + data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); + } + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); + } while(0); + return status; +} + +static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 * packetErr) +{ + int status; + + do { + if (packetErr == NULL) { + CHK_ERROR(Write16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + 0)); + } else { + CHK_ERROR(Read16_0(state, + SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, + packetErr)); + } + } while (0); + return status; +} + +static int DVBTScCommand(struct drxk_state *state, + u16 cmd, u16 subcmd, + u16 param0, u16 param1, u16 param2, + u16 param3, u16 param4) +{ + u16 curCmd = 0; + u16 errCode = 0; + u16 retryCnt = 0; + u16 scExec = 0; + int status; + + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &scExec); + if (scExec != 1) { + /* SC is not running */ + return -1; + } + + /* Wait until sc is ready to receive command */ + retryCnt =0; + do { + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + /* Write sub-command */ + switch (cmd) { + /* All commands using sub-cmd */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); + break; + default: + /* Do nothing */ + break; + } /* switch (cmd->cmd) */ + + /* Write needed parameters and the command */ + switch (cmd) { + /* All commands using 5 parameters */ + /* All commands using 4 parameters */ + /* All commands using 3 parameters */ + /* All commands using 2 parameters */ + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM1__A, param1); + /* All commands using 1 parameters */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_USER_IO: + status = Write16_0(state, OFDM_SC_RA_RAM_PARAM0__A, param0); + /* All commands using 0 parameters */ + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + /* Write command */ + status = Write16_0(state, OFDM_SC_RA_RAM_CMD__A, cmd); + break; + default: + /* Unknown command */ + return -EINVAL; + } /* switch (cmd->cmd) */ + + /* Wait until sc is ready processing command */ + retryCnt = 0; + do{ + msleep(1); + status = Read16_0(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); + retryCnt++; + } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); + if (retryCnt >= DRXK_MAX_RETRIES) + return -1; + + /* Check for illegal cmd */ + status = Read16_0(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); + if (errCode == 0xFFFF) + { + /* illegal command */ + return -EINVAL; + } + + /* Retreive results parameters from SC */ + switch (cmd) { + /* All commands yielding 5 results */ + /* All commands yielding 4 results */ + /* All commands yielding 3 results */ + /* All commands yielding 2 results */ + /* All commands yielding 1 result */ + case OFDM_SC_RA_RAM_CMD_USER_IO: + case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: + status = Read16_0(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); + /* All commands yielding 0 results */ + case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: + case OFDM_SC_RA_RAM_CMD_SET_TIMER: + case OFDM_SC_RA_RAM_CMD_PROC_START: + case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM: + case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM: + case OFDM_SC_RA_RAM_CMD_NULL: + break; + default: + /* Unknown command */ + return -EINVAL; + break; + } /* switch (cmd->cmd) */ + return status; +} + +static int PowerUpDVBT (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRX_POWER_UP; + int status; + + do { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + } while (0); + return status; +} + +static int DVBTCtrlSetIncEnable (struct drxk_state *state, bool* enabled) +{ + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (*enabled == true) + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 0); + } + else + { + status = Write16_0(state, IQM_CF_BYPASSDET__A, 1); + } + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + #define DEFAULT_FR_THRES_8K 4000 +static int DVBTCtrlSetFrEnable (struct drxk_state *state, bool* enabled) +{ + + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + if (*enabled == true) + { + /* write mask to 1 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, + DEFAULT_FR_THRES_8K); + } + else + { + /* write mask to 0 */ + status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetEchoThreshold (struct drxk_state *state, + struct DRXKCfgDvbtEchoThres_t* echoThres) +{ + u16 data = 0; + int status; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + do { + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); + + switch (echoThres->fftMode) + { + case DRX_FFTMODE_2K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_2K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_2K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); + break; + case DRX_FFTMODE_8K: + data &= ~ OFDM_SC_RA_RAM_ECHO_THRES_8K__M; + data |= ((echoThres->threshold << OFDM_SC_RA_RAM_ECHO_THRES_8K__B) & + (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); + break; + default: + return -1; + break; + } + + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, + enum DRXKCfgDvbtSqiSpeed* speed) +{ + int status; + + switch (*speed) { + case DRXK_DVBT_SQI_SPEED_FAST: + case DRXK_DVBT_SQI_SPEED_MEDIUM: + case DRXK_DVBT_SQI_SPEED_SLOW: + break; + default: + return -EINVAL; + } + status = Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, + (u16) *speed); + return status; +} + +/*============================================================================*/ + +/** +* \brief Activate DVBT specific presets +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* Called in DVBTSetStandard +* +*/ +static int DVBTActivatePresets (struct drxk_state *state) +{ + int status; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + struct DRXKCfgDvbtEchoThres_t echoThres2k = {0, DRX_FFTMODE_2K}; + struct DRXKCfgDvbtEchoThres_t echoThres8k = {0, DRX_FFTMODE_8K}; + + do { + bool setincenable = false; + bool setfrenable = true; + CHK_ERROR(DVBTCtrlSetIncEnable (state, &setincenable)); + CHK_ERROR(DVBTCtrlSetFrEnable (state, &setfrenable)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); + CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, + state->m_dvbtIfAgcCfg.IngainTgtMax)); + } while (0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} +/*============================================================================*/ + +/** +* \brief Initialize channelswitch-independent settings for DVBT. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* +* For ROM code channel filter taps are loaded from the bootloader. For microcode +* the DVB-T taps from the drxk_filters.h are used. +*/ +static int SetDVBTStandard (struct drxk_state *state,enum OperationMode oMode) +{ + u16 cmdResult = 0; + u16 data = 0; + int status; + + //printk("%s\n", __FUNCTION__); + + PowerUpDVBT(state); + + do { + /* added antenna switch */ + SwitchAntennaToDVBT(state); + /* send OFDM reset command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + + /* send OFDM setenv command */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,0,NULL,1,&cmdResult)); + + /* reset datapath for OFDM, processors first */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP )); + + /* IQM setup */ + /* synchronize on ofdstate->m_festart */ + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); + /* window size for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + /* window size for for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + /* sense threshold for sense pre-SAW detection */ + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + CHK_ERROR(SetIqmAf(state,true)); + + CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); + + /* Impulse noise cruncher setup */ + CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); + + /* virtual clipping threshold for clipping ADC detection */ + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ + + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_DVBT, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); + /* enable power measurement interrupt */ + CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization(state)); + CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)) ; + CHK_ERROR(SetAgcIf (state, &state->m_dvbtIfAgcCfg, true)); + + /* Set Noise Estimation notch width and enable DC fix */ + CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data)); + data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state,SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + if (!state->m_DRXK_A3_ROM_CODE) + { + /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ + CHK_ERROR(Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, + state->m_dvbtIfAgcCfg.FastClipCtrlDelay)); + } + + /* OFDM_SC setup */ +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); +#endif + + /* FEC setup */ + CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ + + +#ifdef COMPILE_FOR_NONRT + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x400)); +#else + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A , 0x1000)); +#endif + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A , 0x0001)); + + /* Setup MPEG bus */ + CHK_ERROR(MPEGTSDtoSetup (state,OM_DVBT)); + /* Set DVBT Presets */ + CHK_ERROR (DVBTActivatePresets (state)); + + } while (0); + + if (status<0) + { + printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + +/*============================================================================*/ +/** +* \brief Start dvbt demodulating for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +*/ +static int DVBTStart(struct drxk_state *state) +{ + u16 param1; + + int status; +// DRXKOfdmScCmd_t scCmd; + + //printk("%s\n",__FUNCTION__); + /* Start correct processes to get in lock */ + /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ + do { + param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; + CHK_ERROR(DVBTScCommand(state,OFDM_SC_RA_RAM_CMD_PROC_START,0,OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M,param1,0,0,0)); + /* Start FEC OC */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state,FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + } while (0); + return (status); +} + + +/*============================================================================*/ + +/** +* \brief Set up dvbt demodulator for channel. +* \param demod instance of demodulator. +* \return DRXStatus_t. +* // original DVBTSetChannel() +*/ +static int SetDVBT (struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + u16 cmdResult = 0; + u16 transmissionParams = 0; + u16 operationMode = 0; + u32 iqmRcRateOfs = 0; + u32 bandwidth = 0; + u16 param1; + int status; + + //printk("%s IF =%d, TFO = %d\n",__FUNCTION__,IntermediateFreqkHz,tunerFreqOffset); + do { + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_OFDM | + SCU_RAM_COMMAND_CMD_DEMOD_STOP, + 0,NULL,1,&cmdResult)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* Stop processors */ + CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP)); + + /* Mandatory fix, always stop CP, required to set spl offset back to + hardware default (is set to 0 by ucode during pilot detection */ + CHK_ERROR(Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP)); + + /*== Write channel settings to device =====================================*/ + + /* mode */ + switch(state->param.u.ofdm.transmission_mode) { + case TRANSMISSION_MODE_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; + /* fall through , try first guess DRX_FFTMODE_8K */ + case TRANSMISSION_MODE_8K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; + break; + case TRANSMISSION_MODE_2K: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; + break; + } + + /* guard */ + switch(state->param.u.ofdm.guard_interval) { + default: + case GUARD_INTERVAL_AUTO: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; + /* fall through , try first guess DRX_GUARD_1DIV4 */ + case GUARD_INTERVAL_1_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; + break; + case GUARD_INTERVAL_1_32: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; + break; + case GUARD_INTERVAL_1_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; + break; + case GUARD_INTERVAL_1_8: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; + break; + } + + /* hierarchy */ + switch(state->param.u.ofdm.hierarchy_information) { + case HIERARCHY_AUTO: + case HIERARCHY_NONE: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; + /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ + // transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; + //break; + case HIERARCHY_1: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; + break; + case HIERARCHY_2: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; + break; + case HIERARCHY_4: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; + break; + } + + + /* constellation */ + switch(state->param.u.ofdm.constellation) { + case QAM_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; + /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ + case QAM_64: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; + break; + case QPSK: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; + break; + case QAM_16: + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; + break; + } +#if 0 + // No hierachical channels support in BDA + /* Priority (only for hierarchical channels) */ + switch (channel->priority) { + case DRX_PRIORITY_LOW : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_LO); + break; + case DRX_PRIORITY_HIGH : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + WR16(devAddr, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); + break; + case DRX_PRIORITY_UNKNOWN : /* fall through */ + default: + return (DRX_STS_INVALID_ARG); + break; + } +#else + // Set Priorty high + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; + CHK_ERROR(Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI)); +#endif + + /* coderate */ + switch(state->param.u.ofdm.code_rate_HP) { + case FEC_AUTO: + default: + operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; + /* fall through , try first guess DRX_CODERATE_2DIV3 */ + case FEC_2_3 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; + break; + case FEC_1_2 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; + break; + case FEC_3_4 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; + break; + case FEC_5_6 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; + break; + case FEC_7_8 : + transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; + break; + } + + /* SAW filter selection: normaly not necesarry, but if wanted + the application can select a SAW filter via the driver by using UIOs */ + /* First determine real bandwidth (Hz) */ + /* Also set delay for impulse noise cruncher */ + /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed + by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC + functions */ + switch(state->param.u.ofdm.bandwidth) { + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052)); + /* cochannel protection for PAL 8 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; + case BANDWIDTH_7_MHZ: + bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491)); + /* cochannel protection for PAL 7 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; + case BANDWIDTH_6_MHZ: + bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073)); + /* cochannel protection for NTSC 6 MHz */ + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14)); + CHK_ERROR(Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1)); + break; + } + + if (iqmRcRateOfs == 0) + { + /* Now compute IQM_RC_RATE_OFS + (((SysFreq/BandWidth)/2)/2) -1) * 2^23) + => + ((SysFreq / BandWidth) * (2^21)) - (2^23) + */ + /* (SysFreq / BandWidth) * (2^28) */ + /* assert (MAX(sysClk)/MIN(bandwidth) < 16) + => assert(MAX(sysClk) < 16*MIN(bandwidth)) + => assert(109714272 > 48000000) = true so Frac 28 can be used */ + iqmRcRateOfs = Frac28a((u32)((state->m_sysClockFreq * 1000)/3), bandwidth); + /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ + if ((iqmRcRateOfs & 0x7fL) >= 0x40) + { + iqmRcRateOfs += 0x80L; + } + iqmRcRateOfs = iqmRcRateOfs >> 7 ; + /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ + iqmRcRateOfs = iqmRcRateOfs - (1<<23); + } + + iqmRcRateOfs &= ((((u32)IQM_RC_RATE_OFS_HI__M)<m_DRXK_A3_ROM_CODE) + CHK_ERROR (DVBTCtrlSetSqiSpeed(state,&state->m_sqiSpeed)); + + } while(0); + if (status<0) { + //printk("%s status - %08x\n",__FUNCTION__,status); + } + + return status; +} + + +/*============================================================================*/ + +/** +* \brief Retreive lock status . +* \param demod Pointer to demodulator instance. +* \param lockStat Pointer to lock status structure. +* \return DRXStatus_t. +* +*/ +static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | + OFDM_SC_RA_RAM_LOCK_FEC__M ); + const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); + const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M ; + + u16 ScRaRamLock = 0; + u16 ScCommExec = 0; + + /* driver 0.9.0 */ + /* Check if SC is running */ + status = Read16_0(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); + if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) + { + /* SC not active; return DRX_NOT_LOCKED */ + *pLockStatus = NOT_LOCKED; + return status; + } + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + + status = Read16_0(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "RamLock: %04X\n",ScRaRamLock)); + + if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { + *pLockStatus = MPEG_LOCK; + } else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) { + *pLockStatus = FEC_LOCK; + } else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) { + *pLockStatus = DEMOD_LOCK; + } else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) { + *pLockStatus = NEVER_LOCK; + } else { + *pLockStatus = NOT_LOCKED; + } + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + + return status; +} + +static int PowerUpQAM (struct drxk_state *state) +{ + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/// Power Down QAM +static int PowerDownQAM(struct drxk_state *state) +{ + u16 data = 0; + u16 cmdResult; + + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); + if (data == SCU_COMM_EXEC_ACTIVE) + { + /* + STOP demodulator + QAM and HW blocks + */ + /* stop all comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP,0,NULL,1,&cmdResult)); + } + /* powerdown AFE */ + CHK_ERROR(SetIqmAf(state, false)); + } + while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} +/*============================================================================*/ + +/** +* \brief Setup of the QAM Measurement intervals for signal quality +* \param demod instance of demod. +* \param constellation current constellation. +* \return DRXStatus_t. +* +* NOTE: +* Take into account that for certain settings the errorcounters can overflow. +* The implementation does not check this. +* +*/ +static int SetQAMMeasurement(struct drxk_state *state, + enum EDrxkConstellation constellation, + u32 symbolRate) +{ + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ "(%d,%d) om = %d\n", constellation, symbolRate,state->m_OperationMode)); + + u32 fecBitsDesired = 0; /* BER accounting period */ + u32 fecRsPeriodTotal = 0; /* Total period */ + u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ + u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ + int status = 0; + + fecRsPrescale = 1; + + do { + + /* fecBitsDesired = symbolRate [kHz] * + FrameLenght [ms] * + (constellation + 1) * + SyncLoss (== 1) * + ViterbiLoss (==1) + */ + switch (constellation) + { + case DRX_CONSTELLATION_QAM16: + fecBitsDesired = 4 * symbolRate; + break; + case DRX_CONSTELLATION_QAM32: + fecBitsDesired = 5 * symbolRate; + break; + case DRX_CONSTELLATION_QAM64: + fecBitsDesired = 6 * symbolRate; + break; + case DRX_CONSTELLATION_QAM128: + fecBitsDesired = 7 * symbolRate; + break; + case DRX_CONSTELLATION_QAM256: + fecBitsDesired = 8 * symbolRate; + break; + default: + status = -EINVAL; + } + CHK_ERROR(status); + + fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ + fecBitsDesired *= 500; /* meas. period [ms] */ + + /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ + /* fecRsPeriodTotal = fecBitsDesired / 1632 */ + fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil*/ + + /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ + fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); + if (fecRsPrescale == 0) { + /* Divide by zero (though impossible) */ + status = -1; + } + CHK_ERROR(status); + fecRsPeriod = ((u16) fecRsPeriodTotal + (fecRsPrescale >> 1)) / + fecRsPrescale; + + /* write corresponding registers */ + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod)); + CHK_ERROR(Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale)); + CHK_ERROR(Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); + + } while (0); + + if (status<0) { + printk("%s: status - %08x\n",__FUNCTION__,status); + } + return status; +} + +static int SetQAM16 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16)); + + /* QAM Loop Controller Coeficients */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)-127)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM32 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM32 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM64 specific setup +* \param demod instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM64 (struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM128 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM128(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM128)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + +/*============================================================================*/ + +/** +* \brief QAM256 specific setup +* \param demod: instance of demod. +* \return DRXStatus_t. +*/ +static int SetQAM256(struct drxk_state *state) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + do + { + /* QAM Equalizer Setup */ + /* Equalizer */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); + + /* Decision Feedback Equalizer */ + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); + CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); + + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); + CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); + + /* QAM Slicer Settings */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A,DRXK_QAM_SL_SIG_POWER_QAM256)); + + + /* QAM Loop Controller Coeficients */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); + + + /* QAM State Machine (FSM) Thresholds */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); + + + /* QAM FSM Tracking Parameters */ + + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0)); + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8)); + }while(0); + + if (status<0) + { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + } + return status; +} + + +/*============================================================================*/ +/** +* \brief Reset QAM block. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMResetQAM(struct drxk_state *state) +{ + int status; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + do + { + /* Stop QAM comstate->m_exec */ + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET,0,NULL,1,&cmdResult)); + } while (0); + + /* All done, all OK */ + return status; +} + +/*============================================================================*/ + +/** +* \brief Set QAM symbolrate. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ +static int QAMSetSymbolrate(struct drxk_state *state) +{ + u32 adcFrequency = 0; + u32 symbFreq = 0; + u32 iqmRcRate = 0; + u16 ratesel = 0; + u32 lcSymbRate = 0; + int status; + + do + { + /* Select & calculate correct IQM rate */ + adcFrequency = (state->m_sysClockFreq * 1000) / 3; + ratesel = 0; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " state->m_SymbolRate = %d\n",state->m_SymbolRate)); + //printk("SR %d\n", state->param.u.qam.symbol_rate); + if (state->param.u.qam.symbol_rate <= 1188750) + { + ratesel = 3; + } + else if (state->param.u.qam.symbol_rate <= 2377500) + { + ratesel = 2; + } + else if (state->param.u.qam.symbol_rate <= 4755000) + { + ratesel = 1; + } + CHK_ERROR(Write16_0(state,IQM_FD_RATESEL__A, ratesel)); + + /* + IqmRcRate = ((Fadc / (symbolrate * (4<param.u.qam.symbol_rate * (1 << ratesel); + if (symbFreq == 0) + { + /* Divide by zero */ + return -1; + } + iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + + (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - + (1 << 23); + CHK_ERROR(Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate,0)); + state->m_iqmRcRate = iqmRcRate; + /* + LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) + */ + symbFreq = state->param.u.qam.symbol_rate; + if (adcFrequency == 0) + { + /* Divide by zero */ + return -1; + } + lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + + (Frac28a((symbFreq % adcFrequency), adcFrequency) >> 16); + if (lcSymbRate > 511) + { + lcSymbRate = 511; + } + CHK_ERROR(Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate)); + } while (0); + + return status; +} + +/*============================================================================*/ + +/** +* \brief Get QAM lock status. +* \param demod: instance of demod. +* \param channel: pointer to channel data. +* \return DRXStatus_t. +*/ + +static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) +{ + int status; + u16 Result[2] = {0,0}; + + status = scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM|SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, Result); + if (status<0) + { + printk("%s status = %08x\n",__FUNCTION__,status); + } + if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) + { + /* 0x0000 NOT LOCKED */ + *pLockStatus = NOT_LOCKED; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) + { + /* 0x4000 DEMOD LOCKED */ + *pLockStatus = DEMOD_LOCK; + } + else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) + { + /* 0x8000 DEMOD + FEC LOCKED (system lock) */ + *pLockStatus = MPEG_LOCK; + } + else + { + /* 0xC000 NEVER LOCKED */ + /* (system will never be able to lock to the signal) */ + /* TODO: check this, intermediate & standard specific lock states are not + taken into account here */ + *pLockStatus = NEVER_LOCK; + } + return status; +} + +#define QAM_MIRROR__M 0x03 +#define QAM_MIRROR_NORMAL 0x00 +#define QAM_MIRRORED 0x01 +#define QAM_MIRROR_AUTO_ON 0x02 +#define QAM_LOCKRANGE__M 0x10 +#define QAM_LOCKRANGE_NORMAL 0x10 + +static int SetQAM(struct drxk_state *state,u16 IntermediateFreqkHz, s32 tunerFreqOffset) +{ + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + int status = 0; + u8 parameterLen; + u16 setEnvParameters[5]; + u16 setParamParameters[4]={0,0,0,0}; + u16 cmdResult; + + //printk("%s\n", __FUNCTION__); + + do { + /* + STEP 1: reset demodulator + resets FEC DI and FEC RS + resets QAM block + resets SCU variables + */ + CHK_ERROR(Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP)); + CHK_ERROR(QAMResetQAM(state)); + + /* + STEP 2: configure demodulator + -set env + -set params; resets IQM,QAM,FEC HW; initializes some SCU variables + */ + CHK_ERROR(QAMSetSymbolrate(state)); + + /* Env parameters */ + setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ + if (state->m_OperationMode == OM_QAM_ITU_C) + { + setEnvParameters[2] = QAM_TOP_ANNEX_C; /* Annex */ + } + setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); +// check for LOCKRANGE Extented + // setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; + parameterLen = 4; + + /* Set params */ + switch(state->param.u.qam.modulation) + { + case QAM_256: + state->m_Constellation = DRX_CONSTELLATION_QAM256; + break; + case QAM_AUTO: + case QAM_64: + state->m_Constellation = DRX_CONSTELLATION_QAM64; + break; + case QAM_16: + state->m_Constellation = DRX_CONSTELLATION_QAM16; + break; + case QAM_32: + state->m_Constellation = DRX_CONSTELLATION_QAM32; + break; + case QAM_128: + state->m_Constellation = DRX_CONSTELLATION_QAM128; + break; + default: + status = -EINVAL; + break; + } + CHK_ERROR(status); + setParamParameters[0] = state->m_Constellation; /* constellation */ + setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ + + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,4,setParamParameters,1,&cmdResult)); + + + /* STEP 3: enable the system in a mode where the ADC provides valid signal + setup constellation independent registers */ +// CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); + CHK_ERROR (SetFrequencyShifter (state, IntermediateFreqkHz, tunerFreqOffset, true)); + + /* Setup BER measurement */ + CHK_ERROR(SetQAMMeasurement (state, + state->m_Constellation, + state->param.u.qam.symbol_rate)); + + /* Reset default values */ + CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE)); + CHK_ERROR(Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); + + /* Reset default LC values */ + CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); + + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); + CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); + + /* Mirroring, QAM-block starting point not inverted */ + CHK_ERROR(Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* STEP 4: constellation specific setup */ + switch (state->param.u.qam.modulation) + { + case QAM_16: + CHK_ERROR(SetQAM16(state)); + break; + case QAM_32: + CHK_ERROR(SetQAM32(state)); + break; + case QAM_AUTO: + case QAM_64: + CHK_ERROR(SetQAM64(state)); + break; + case QAM_128: + CHK_ERROR(SetQAM128(state)); + break; + case QAM_256: + //printk("SETQAM256\n"); + CHK_ERROR(SetQAM256(state)); + break; + default: + return -1; + break; + } /* switch */ + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + + + /* Re-configure MPEG output, requires knowledge of channel bitrate */ +// extAttr->currentChannel.constellation = channel->constellation; +// extAttr->currentChannel.symbolrate = channel->symbolrate; + CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); + + /* Start processes */ + CHK_ERROR(MPEGTSStart(state)); + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE)); + + /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ + CHK_ERROR(scu_command(state,SCU_RAM_COMMAND_STANDARD_QAM | + SCU_RAM_COMMAND_CMD_DEMOD_START,0, + NULL,1,&cmdResult)); + + /* update global DRXK data container */ +//? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; + + /* All done, all OK */ + } while(0); + + if (status<0) { + printk("%s %d\n", __FUNCTION__, status); + } + return status; +} + +static int SetQAMStandard(struct drxk_state *state, enum OperationMode oMode) +{ +#ifdef DRXK_QAM_TAPS +#define DRXK_QAMA_TAPS_SELECT +#include "drxk_filters.h" +#undef DRXK_QAMA_TAPS_SELECT +#else + int status; +#endif + + //printk("%s\n", __FUNCTION__); + do + { + /* added antenna switch */ + SwitchAntennaToQAM(state); + + /* Ensure correct power-up mode */ + CHK_ERROR(PowerUpQAM(state)); + /* Reset QAM block */ + CHK_ERROR(QAMResetQAM(state)); + + /* Setup IQM */ + + CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); + CHK_ERROR(Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); + + /* Upload IQM Channel Filter settings by + boot loader from ROM table */ + switch (oMode) + { + case OM_QAM_ITU_A: + CHK_ERROR(BLChainCmd(state, + DRXK_BL_ROM_OFFSET_TAPS_ITU_A, + DRXK_BLCC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + case OM_QAM_ITU_C: + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, + DRXK_BL_ROM_OFFSET_TAPS_ITU_C, + DRXK_BLDC_NR_ELEMENTS_TAPS, + DRXK_BLC_TIMEOUT)); + break; + default: + status=-EINVAL; + } + CHK_ERROR (status); + + CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, + (1 << IQM_CF_OUT_ENA_QAM__B))); + CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, + ((1 << IQM_CF_MIDTAP_RE__B) | + (1 << IQM_CF_MIDTAP_IM__B)))); + + CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); + CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); + + CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); + + /* IQM Impulse Noise Processing Unit */ + CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); + CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); + CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); + CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); + CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); + CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); + + /* turn on IQMAF. Must be done before setAgc**() */ + CHK_ERROR(SetIqmAf(state, true)); + CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); + + /* IQM will not be reset from here, sync ADC and update/init AGC */ + CHK_ERROR(ADCSynchronization (state)); + + /* Set the FSM step period */ + CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); + + /* Halt SCU to enable safe non-atomic accesses */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); + + /* No more resets of the IQM, current standard correctly set => + now AGCs can be configured. */ + + CHK_ERROR(InitAGC(state,true)); + CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); + + /* Configure AGC's */ + CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); + CHK_ERROR(SetAgcIf (state, &(state->m_qamIfAgcCfg), true)); + + /* Activate SCU to enable SCU commands */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + } while (0); + return status; +} + +static int WriteGPIO(struct drxk_state *state) +{ + int status; + u16 value = 0; + + do { + /* stop lock indicator process */ + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, + SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + + /* Write magic word to enable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, + SIO_TOP_COMM_KEY_KEY)); + + if (state->m_hasSAWSW) { + /* write to io pad configuration register - output mode */ + CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, + state->m_GPIOCfg)); + + /* use corresponding bit in io data output registar */ + CHK_ERROR(Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value)); + if (state->m_GPIO == 0) { + value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ + } else { + value |= 0x8000; /* write one to 15th bit - 1st UIO */ + } + /* write back to io data output register */ + CHK_ERROR(Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value)); + + } + /* Write magic word to disable pdr reg write */ + CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); + } while (0); + return status; +} + +static int SwitchAntennaToQAM(struct drxk_state *state) +{ + int status = -1; + + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBC) { + state->m_GPIO = state->m_AntennaDVBC; + status = WriteGPIO(state); + } + } + return status; +} + +static int SwitchAntennaToDVBT(struct drxk_state *state) +{ + int status = -1; + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n")); + if (state->m_AntennaSwitchDVBTDVBC != 0) { + if (state->m_GPIO != state->m_AntennaDVBT) { + state->m_GPIO = state->m_AntennaDVBT; + status = WriteGPIO(state); + } + } + return status; +} + + +static int PowerDownDevice(struct drxk_state *state) +{ + /* Power down to requested mode */ + /* Backup some register settings */ + /* Set pins with possible pull-ups connected to them in input mode */ + /* Analog power down */ + /* ADC power down */ + /* Power down device */ + int status; + do { + if (state->m_bPDownOpenBridge) { + // Open I2C bridge before power down of DRXK + CHK_ERROR(ConfigureI2CBridge(state, true)); + } + // driver 0.9.0 + CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); + + CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A , SIO_CC_UPDATE_KEY)); + state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; + CHK_ERROR(HI_CfgCommand(state)); + } + while(0); + + if (status<0) { + //KdPrintEx((MSG_ERROR " - " __FUNCTION__ " status - %08x\n",status)); + return -1; + } + return 0; +} + +static int load_microcode(struct drxk_state *state, char *mc_name) +{ + const struct firmware *fw = NULL; + int err=0; + + err = request_firmware(&fw, mc_name, state->i2c->dev.parent); + if (err < 0) { + printk(KERN_ERR + ": Could not load firmware file %s.\n", mc_name); + printk(KERN_INFO + ": Copy %s to your hotplug directory!\n", mc_name); + return err; + } + err=DownloadMicrocode(state, fw->data, fw->size); + release_firmware(fw); + return err; +} + +static int init_drxk(struct drxk_state *state) +{ + int status; + DRXPowerMode_t powerMode = DRXK_POWER_DOWN_OFDM; + u16 driverVersion; + + //printk("init_drxk\n"); + if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { + do { + CHK_ERROR(PowerUpDevice(state)); + CHK_ERROR (DRXX_Open(state)); + /* Soft reset of OFDM-, sys- and osc-clockdomain */ + CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, + SIO_CC_SOFT_RST_OFDM__M | + SIO_CC_SOFT_RST_SYS__M | + SIO_CC_SOFT_RST_OSC__M)); + CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); + /* TODO is this needed, if yes how much delay in worst case scenario */ + msleep(1); + state->m_DRXK_A3_PATCH_CODE = true; + CHK_ERROR(GetDeviceCapabilities(state)); + + /* Bridge delay, uses oscilator clock */ + /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ + /* SDA brdige delay */ + state->m_HICfgBridgeDelay = (u16)((state->m_oscClockFreq/1000)* HI_I2C_BRIDGE_DELAY)/1000; + /* Clipping */ + if (state->m_HICfgBridgeDelay > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) + { + state->m_HICfgBridgeDelay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; + } + /* SCL bridge delay, same as SDA for now */ + state->m_HICfgBridgeDelay += state->m_HICfgBridgeDelay << SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; + + CHK_ERROR(InitHI(state)); + /* disable various processes */ +#if NOA1ROM + if (!(state->m_DRXK_A1_ROM_CODE) && !(state->m_DRXK_A2_ROM_CODE) ) +#endif + { + CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); + } + + /* disable MPEG port */ + CHK_ERROR(MPEGTSDisable(state)); + + /* Stop AUD and SCU */ + CHK_ERROR(Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP)); + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP)); + + /* enable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); + + /* include boot loader section */ + CHK_ERROR(Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE)); + CHK_ERROR(BLChainCmd(state, 0, 6, 100)); + +#if 0 + if (state->m_DRXK_A3_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A3_microcode, + DRXK_A3_microcode_length)); +#else + load_microcode(state, "drxk_a3.mc"); +#endif +#if NOA1ROM + if (state->m_DRXK_A2_PATCH_CODE) + CHK_ERROR(DownloadMicrocode(state, + DRXK_A2_microcode, + DRXK_A2_microcode_length)); +#endif + /* disable token-ring bus through OFDM block for possible ucode upload */ + CHK_ERROR(Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); + + /* Run SCU for a little while to initialize microcode version numbers */ + CHK_ERROR(Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); + CHK_ERROR (DRXX_Open(state)); + // added for test + msleep(30); + + powerMode = DRXK_POWER_DOWN_OFDM; + CHK_ERROR(CtrlPowerMode(state, &powerMode)); + + /* Stamp driver version number in SCU data RAM in BCD code + Done to enable field application engineers to retreive drxdriver version + via I2C from SCU RAM. + Not using SCU command interface for SCU register access since no + microcode may be present. + */ + driverVersion = (((DRXK_VERSION_MAJOR/100) % 10) << 12) + + (((DRXK_VERSION_MAJOR/10) % 10) << 8) + + ((DRXK_VERSION_MAJOR%10) << 4) + + (DRXK_VERSION_MINOR%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion )); + driverVersion = (((DRXK_VERSION_PATCH/1000) % 10) << 12) + + (((DRXK_VERSION_PATCH/100) % 10) << 8) + + (((DRXK_VERSION_PATCH/10) % 10) << 4) + + (DRXK_VERSION_PATCH%10); + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion )); + + printk("DRXK driver version:%d.%d.%d\n", + DRXK_VERSION_MAJOR,DRXK_VERSION_MINOR,DRXK_VERSION_PATCH); + + /* Dirty fix of default values for ROM/PATCH microcode + Dirty because this fix makes it impossible to setup suitable values + before calling DRX_Open. This solution requires changes to RF AGC speed + to be done via the CTRL function after calling DRX_Open */ + + // m_dvbtRfAgcCfg.speed=3; + + /* Reset driver debug flags to 0 */ + CHK_ERROR(Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0)); + /* driver 0.9.0 */ + /* Setup FEC OC: + NOTE: No more full FEC resets allowed afterwards!! */ + CHK_ERROR(Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP)); + // MPEGTS functions are still the same + CHK_ERROR(MPEGTSDtoInit(state)); + CHK_ERROR(MPEGTSStop(state)); + CHK_ERROR(MPEGTSConfigurePolarity(state)); + CHK_ERROR(MPEGTSConfigurePins(state, state->m_enableMPEGOutput)); + // added: configure GPIO + CHK_ERROR(WriteGPIO(state)); + + state->m_DrxkState = DRXK_STOPPED; + + if (state->m_bPowerDown) { + CHK_ERROR(PowerDownDevice(state)); + state->m_DrxkState = DRXK_POWERED_DOWN; + } + else + state->m_DrxkState = DRXK_STOPPED; + } while(0); + //printk("%s=%d\n", __FUNCTION__, status); + } + else + { + //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " - Init already done\n")); + } + + return 0; +} + +static void drxk_c_release(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + printk("%s\n", __FUNCTION__); + kfree(state); +} + +static int drxk_c_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + SetOperationMode(state, OM_QAM_ITU_A); + return 0; +} + +static int drxk_c_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + + ShutDown(state); + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + struct drxk_state *state = fe->demodulator_priv; + + //printk("drxk_gate %d\n", enable); + return ConfigureI2CBridge(state, enable ? true : false); +} + +static int drxk_set_parameters (struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 IF; + + //printk("%s\n", __FUNCTION__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, p); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + state->param=*p; + fe->ops.tuner_ops.get_frequency(fe, &IF); + Start(state, 0, IF); + + //printk("%s IF=%d done\n", __FUNCTION__, IF); + return 0; +} + +static int drxk_c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 stat; + + *status=0; + GetLockStatus(state, &stat, 0); + if (stat==MPEG_LOCK) + *status|=0x1f; + if (stat==FEC_LOCK) + *status|=0x0f; + if (stat==DEMOD_LOCK) + *status|=0x07; + return 0; +} + +static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + //struct drxk_state *state = fe->demodulator_priv; + *ber=0; + return 0; +} + +static int drxk_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct drxk_state *state = fe->demodulator_priv; + u32 val; + + ReadIFAgc(state, &val); + *strength = val & 0xffff;; + return 0; +} + +static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct drxk_state *state = fe->demodulator_priv; + s32 snr2; + + GetSignalToNoise(state, &snr2); + *snr = snr2&0xffff; + return 0; +} + +static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct drxk_state *state = fe->demodulator_priv; + u16 err; + + DVBTQAMGetAccPktErr(state, &err); + *ucblocks = (u32) err; + return 0; +} + +static int drxk_c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=3000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +static void drxk_t_release(struct dvb_frontend* fe) +{ + //struct drxk_state *state=fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + //kfree(state); +} + +static int drxk_t_init (struct dvb_frontend *fe) +{ + struct drxk_state *state=fe->demodulator_priv; + if (mutex_trylock(&state->ctlock)==0) + return -EBUSY; + //printk("%s\n", __FUNCTION__); + SetOperationMode(state, OM_DVBT); + //printk("%s done\n", __FUNCTION__); + return 0; +} + +static int drxk_t_sleep(struct dvb_frontend* fe) +{ + struct drxk_state *state=fe->demodulator_priv; + mutex_unlock(&state->ctlock); + return 0; +} + +static int drxk_t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) +{ + //struct drxk_state *state = fe->demodulator_priv; + //printk("%s\n", __FUNCTION__); + return 0; +} + +static struct dvb_frontend_ops drxk_c_ops = { + .info = { + .name = "DRXK DVB-C", + .type = FE_QAM, + .frequency_stepsize = 62500, + .frequency_min = 47000000, + .frequency_max = 862000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, + .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO + }, + .release = drxk_c_release, + .init = drxk_c_init, + .sleep = drxk_c_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_c_get_frontend, + .get_tune_settings = drxk_c_get_tune_settings, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +static struct dvb_frontend_ops drxk_t_ops = { + .info = { + .name = "DRXK DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 865000000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + .release = drxk_t_release, + .init = drxk_t_init, + .sleep = drxk_t_sleep, + .i2c_gate_ctrl = drxk_gate_ctrl, + + .set_frontend = drxk_set_parameters, + .get_frontend = drxk_t_get_frontend, + + .read_status = drxk_read_status, + .read_ber = drxk_read_ber, + .read_signal_strength = drxk_read_signal_strength, + .read_snr = drxk_read_snr, + .read_ucblocks = drxk_read_ucblocks, +}; + +struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, + struct dvb_frontend **fe_t) +{ + struct drxk_state *state = NULL; + + state=kzalloc(sizeof(struct drxk_state), GFP_KERNEL); + if (!state) + return NULL; + + state->i2c=i2c; + state->demod_address=adr; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + + memcpy(&state->c_frontend.ops, &drxk_c_ops, sizeof(struct dvb_frontend_ops)); + memcpy(&state->t_frontend.ops, &drxk_t_ops, sizeof(struct dvb_frontend_ops)); + state->c_frontend.demodulator_priv=state; + state->t_frontend.demodulator_priv=state; + + init_state(state); + if (init_drxk(state)<0) + goto error; + *fe_t = &state->t_frontend; + return &state->c_frontend; + +error: + printk("drxk: not found\n"); + kfree(state); + return NULL; +} + +MODULE_DESCRIPTION("DRX-K driver"); +MODULE_AUTHOR("Ralph Metzler"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drxk_attach); diff --git a/drivers/media/dvb/frontends/drxk_hard.h b/drivers/media/dvb/frontends/drxk_hard.h new file mode 100644 index 000000000000..550df3434a98 --- /dev/null +++ b/drivers/media/dvb/frontends/drxk_hard.h @@ -0,0 +1,339 @@ +#include "drxk_map.h" + +#define DRXK_VERSION_MAJOR 0 +#define DRXK_VERSION_MINOR 9 +#define DRXK_VERSION_PATCH 4300 + +#define HI_I2C_DELAY 42 +#define HI_I2C_BRIDGE_DELAY 350 +#define DRXK_MAX_RETRIES 100 + +#define DRIVER_4400 1 + +#define DRXX_JTAGID 0x039210D9 +#define DRXX_J_JTAGID 0x239310D9 +#define DRXX_K_JTAGID 0x039210D9 + +#define DRX_UNKNOWN 254 +#define DRX_AUTO 255 + +#define DRX_SCU_READY 0 +#define DRXK_MAX_WAITTIME (200) +#define SCU_RESULT_OK 0 +#define SCU_RESULT_UNKSTD -2 +#define SCU_RESULT_UNKCMD -1 + +#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT +#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200) +#endif + +#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/ +#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/ +#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/ +#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/ +#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/ +#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/ +#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/ +#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/ + +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +enum OperationMode { + OM_NONE, + OM_QAM_ITU_A, + OM_QAM_ITU_B, + OM_QAM_ITU_C, + OM_DVBT +}; + +typedef enum { + DRX_POWER_UP = 0, + DRX_POWER_MODE_1, + DRX_POWER_MODE_2, + DRX_POWER_MODE_3, + DRX_POWER_MODE_4, + DRX_POWER_MODE_5, + DRX_POWER_MODE_6, + DRX_POWER_MODE_7, + DRX_POWER_MODE_8, + + DRX_POWER_MODE_9, + DRX_POWER_MODE_10, + DRX_POWER_MODE_11, + DRX_POWER_MODE_12, + DRX_POWER_MODE_13, + DRX_POWER_MODE_14, + DRX_POWER_MODE_15, + DRX_POWER_MODE_16, + DRX_POWER_DOWN = 255 +}DRXPowerMode_t, *pDRXPowerMode_t; + + +/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ +#ifndef DRXK_POWER_DOWN_OFDM +#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 +#endif + +/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ +#ifndef DRXK_POWER_DOWN_CORE +#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 +#endif + +/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ +#ifndef DRXK_POWER_DOWN_PLL +#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 +#endif + + +enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; +enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; +enum EDrxkCoefArrayIndex { + DRXK_COEF_IDX_MN = 0, + DRXK_COEF_IDX_FM , + DRXK_COEF_IDX_L , + DRXK_COEF_IDX_LP , + DRXK_COEF_IDX_BG , + DRXK_COEF_IDX_DK , + DRXK_COEF_IDX_I , + DRXK_COEF_IDX_MAX +}; +enum EDrxkSifAttenuation { + DRXK_SIF_ATTENUATION_0DB, + DRXK_SIF_ATTENUATION_3DB, + DRXK_SIF_ATTENUATION_6DB, + DRXK_SIF_ATTENUATION_9DB +}; +enum EDrxkConstellation { + DRX_CONSTELLATION_BPSK = 0, + DRX_CONSTELLATION_QPSK, + DRX_CONSTELLATION_PSK8, + DRX_CONSTELLATION_QAM16, + DRX_CONSTELLATION_QAM32, + DRX_CONSTELLATION_QAM64, + DRX_CONSTELLATION_QAM128, + DRX_CONSTELLATION_QAM256, + DRX_CONSTELLATION_QAM512, + DRX_CONSTELLATION_QAM1024, + DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, + DRX_CONSTELLATION_AUTO = DRX_AUTO +}; +enum EDrxkInterleaveMode { + DRXK_QAM_I12_J17 = 16, + DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN +}; +enum { + DRXK_SPIN_A1 = 0, + DRXK_SPIN_A2, + DRXK_SPIN_A3, + DRXK_SPIN_UNKNOWN +}; + +enum DRXKCfgDvbtSqiSpeed { + DRXK_DVBT_SQI_SPEED_FAST = 0, + DRXK_DVBT_SQI_SPEED_MEDIUM, + DRXK_DVBT_SQI_SPEED_SLOW, + DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN +} ; + +enum DRXFftmode_t { + DRX_FFTMODE_2K = 0, + DRX_FFTMODE_4K, + DRX_FFTMODE_8K, + DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, + DRX_FFTMODE_AUTO = DRX_AUTO +}; + +enum DRXMPEGStrWidth_t { + DRX_MPEG_STR_WIDTH_1, + DRX_MPEG_STR_WIDTH_8 +}; + +enum DRXQamLockRange_t { + DRX_QAM_LOCKRANGE_NORMAL, + DRX_QAM_LOCKRANGE_EXTENDED +}; + +struct DRXKCfgDvbtEchoThres_t { + u16 threshold; + enum DRXFftmode_t fftMode; +} ; + +struct SCfgAgc +{ + enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ + u16 outputLevel; /* range dependent on AGC */ + u16 minOutputLevel; /* range dependent on AGC */ + u16 maxOutputLevel; /* range dependent on AGC */ + u16 speed; /* range dependent on AGC */ + u16 top; /* rf-agc take over point */ + u16 cutOffCurrent; /* rf-agc is accelerated if output current + is below cut-off current */ + u16 IngainTgtMax; + u16 FastClipCtrlDelay; +}; + +struct SCfgPreSaw +{ + u16 reference; /* pre SAW reference value, range 0 .. 31 */ + bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ +}; + +struct DRXKOfdmScCmd_t +{ + u16 cmd; /**< Command number */ + u16 subcmd; /**< Sub-command parameter*/ + u16 param0; /**< General purpous param */ + u16 param1; /**< General purpous param */ + u16 param2; /**< General purpous param */ + u16 param3; /**< General purpous param */ + u16 param4; /**< General purpous param */ +}; + +struct drxk_state { + struct dvb_frontend c_frontend; + struct dvb_frontend t_frontend; + struct dvb_frontend_parameters param; + struct device *dev; + + struct i2c_adapter *i2c; + u8 demod_address; + void *priv; + + struct mutex mutex; + struct mutex ctlock; + + u32 m_Instance; ///< Channel 1,2,3 or 4 + + int m_ChunkSize; + u8 Chunk[256]; + + bool m_hasLNA; + bool m_hasDVBT; + bool m_hasDVBC; + bool m_hasAudio; + bool m_hasATV; + bool m_hasOOB; + bool m_hasSAWSW; /**< TRUE if mat_tx is available */ + bool m_hasGPIO1; /**< TRUE if mat_rx is available */ + bool m_hasGPIO2; /**< TRUE if GPIO is available */ + bool m_hasIRQN; /**< TRUE if IRQN is available */ + u16 m_oscClockFreq; + u16 m_HICfgTimingDiv; + u16 m_HICfgBridgeDelay; + u16 m_HICfgWakeUpKey; + u16 m_HICfgTimeout; + u16 m_HICfgCtrl; + s32 m_sysClockFreq ; ///< system clock frequency in kHz + + enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started) + enum OperationMode m_OperationMode; ///< digital standards + struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC + struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC + u16 m_vsbPgaCfg; ///< settings for VSB PGA + struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense + s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication + s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication + bool m_smartAntInverted; + bool m_bDebugEnableBridge; + bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed + bool m_bPowerDown; ///< Power down when not used + + u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint) + + bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ + bool m_insertRSByte; /**< If TRUE, insert RS byte */ + bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ + bool m_invertDATA; /**< If TRUE, invert DATA signals */ + bool m_invertERR; /**< If TRUE, invert ERR signal */ + bool m_invertSTR; /**< If TRUE, invert STR signals */ + bool m_invertVAL; /**< If TRUE, invert VAL signals */ + bool m_invertCLK; /**< If TRUE, invert CLK signals */ + bool m_DVBCStaticCLK; + bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will + be used, otherwise clockrate will + adapt to the bitrate of the TS */ + u32 m_DVBTBitrate; + u32 m_DVBCBitrate; + + u8 m_TSDataStrength; + u8 m_TSClockkStrength; + + enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/ + u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case + static clockrate is selected */ + + //LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start + s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time) + + bool m_disableTEIhandling; + + bool m_RfAgcPol; + bool m_IfAgcPol; + + struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC + struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC + struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense + bool m_phaseCorrectionBypass; + s16 m_atvTopVidPeak; + u16 m_atvTopNoiseTh; + enum EDrxkSifAttenuation m_sifAttenuation; + bool m_enableCVBSOutput; + bool m_enableSIFOutput; + bool m_bMirrorFreqSpect; + enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel + u32 m_CurrSymbolRate; ///< Current QAM symbol rate + struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC + u16 m_qamPgaCfg; ///< settings for QAM PGA + struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense + enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode + u16 m_fecRsPlen; + u16 m_fecRsPrescale; + + enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; + + u16 m_GPIO; + u16 m_GPIOCfg; + + struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC + struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC + struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense + + u16 m_agcFastClipCtrlDelay; + bool m_adcCompPassed; + u16 m_adcCompCoef[64]; + u16 m_adcState; + + u8 *m_microcode; + int m_microcode_length; + bool m_DRXK_A1_PATCH_CODE; + bool m_DRXK_A1_ROM_CODE; + bool m_DRXK_A2_ROM_CODE; + bool m_DRXK_A3_ROM_CODE; + bool m_DRXK_A2_PATCH_CODE; + bool m_DRXK_A3_PATCH_CODE; + + bool m_rfmirror; + u8 m_deviceSpin; + u32 m_iqmRcRate; + + u16 m_AntennaDVBC; + u16 m_AntennaDVBT; + u16 m_AntennaSwitchDVBTDVBC; + + DRXPowerMode_t m_currentPowerMode; +}; + +#define NEVER_LOCK 0 +#define NOT_LOCKED 1 +#define DEMOD_LOCK 2 +#define FEC_LOCK 3 +#define MPEG_LOCK 4 + diff --git a/drivers/media/dvb/frontends/drxk_map.h b/drivers/media/dvb/frontends/drxk_map.h new file mode 100644 index 000000000000..c3f4f4387e16 --- /dev/null +++ b/drivers/media/dvb/frontends/drxk_map.h @@ -0,0 +1,16438 @@ +#ifndef __DRXK_MAP__H__ +#define __DRXK_MAP__H__ 1 + +#define AUD_COMM_EXEC__A 0x1000000 +#define AUD_COMM_EXEC__W 2 +#define AUD_COMM_EXEC__M 0x3 +#define AUD_COMM_EXEC__PRE 0x0 +#define AUD_COMM_EXEC_STOP 0x0 + +#define FEC_COMM_EXEC__A 0x1C00000 +#define FEC_COMM_EXEC__W 2 +#define FEC_COMM_EXEC__M 0x3 +#define FEC_COMM_EXEC__PRE 0x0 +#define FEC_COMM_EXEC_STOP 0x0 +#define FEC_COMM_EXEC_ACTIVE 0x1 +#define FEC_COMM_EXEC_HOLD 0x2 + +#define FEC_COMM_MB__A 0x1C00002 +#define FEC_COMM_MB__W 16 +#define FEC_COMM_MB__M 0xFFFF +#define FEC_COMM_MB__PRE 0x0 +#define FEC_COMM_INT_REQ__A 0x1C00003 +#define FEC_COMM_INT_REQ__W 16 +#define FEC_COMM_INT_REQ__M 0xFFFF +#define FEC_COMM_INT_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_OC_REQ__B 0 +#define FEC_COMM_INT_REQ_OC_REQ__W 1 +#define FEC_COMM_INT_REQ_OC_REQ__M 0x1 +#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_RS_REQ__B 1 +#define FEC_COMM_INT_REQ_RS_REQ__W 1 +#define FEC_COMM_INT_REQ_RS_REQ__M 0x2 +#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0 +#define FEC_COMM_INT_REQ_DI_REQ__B 2 +#define FEC_COMM_INT_REQ_DI_REQ__W 1 +#define FEC_COMM_INT_REQ_DI_REQ__M 0x4 +#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0 + +#define FEC_COMM_INT_STA__A 0x1C00005 +#define FEC_COMM_INT_STA__W 16 +#define FEC_COMM_INT_STA__M 0xFFFF +#define FEC_COMM_INT_STA__PRE 0x0 +#define FEC_COMM_INT_MSK__A 0x1C00006 +#define FEC_COMM_INT_MSK__W 16 +#define FEC_COMM_INT_MSK__M 0xFFFF +#define FEC_COMM_INT_MSK__PRE 0x0 +#define FEC_COMM_INT_STM__A 0x1C00007 +#define FEC_COMM_INT_STM__W 16 +#define FEC_COMM_INT_STM__M 0xFFFF +#define FEC_COMM_INT_STM__PRE 0x0 + + + +#define FEC_TOP_COMM_EXEC__A 0x1C10000 +#define FEC_TOP_COMM_EXEC__W 2 +#define FEC_TOP_COMM_EXEC__M 0x3 +#define FEC_TOP_COMM_EXEC__PRE 0x0 +#define FEC_TOP_COMM_EXEC_STOP 0x0 +#define FEC_TOP_COMM_EXEC_ACTIVE 0x1 +#define FEC_TOP_COMM_EXEC_HOLD 0x2 + +#define FEC_TOP_ANNEX__A 0x1C10010 +#define FEC_TOP_ANNEX__W 2 +#define FEC_TOP_ANNEX__M 0x3 +#define FEC_TOP_ANNEX__PRE 0x0 +#define FEC_TOP_ANNEX_A 0x0 +#define FEC_TOP_ANNEX_B 0x1 +#define FEC_TOP_ANNEX_C 0x2 +#define FEC_TOP_ANNEX_D 0x3 + + + +#define FEC_DI_COMM_EXEC__A 0x1C20000 +#define FEC_DI_COMM_EXEC__W 2 +#define FEC_DI_COMM_EXEC__M 0x3 +#define FEC_DI_COMM_EXEC__PRE 0x0 +#define FEC_DI_COMM_EXEC_STOP 0x0 +#define FEC_DI_COMM_EXEC_ACTIVE 0x1 +#define FEC_DI_COMM_EXEC_HOLD 0x2 + +#define FEC_DI_COMM_MB__A 0x1C20002 +#define FEC_DI_COMM_MB__W 2 +#define FEC_DI_COMM_MB__M 0x3 +#define FEC_DI_COMM_MB__PRE 0x0 +#define FEC_DI_COMM_MB_CTL__B 0 +#define FEC_DI_COMM_MB_CTL__W 1 +#define FEC_DI_COMM_MB_CTL__M 0x1 +#define FEC_DI_COMM_MB_CTL__PRE 0x0 +#define FEC_DI_COMM_MB_CTL_OFF 0x0 +#define FEC_DI_COMM_MB_CTL_ON 0x1 +#define FEC_DI_COMM_MB_OBS__B 1 +#define FEC_DI_COMM_MB_OBS__W 1 +#define FEC_DI_COMM_MB_OBS__M 0x2 +#define FEC_DI_COMM_MB_OBS__PRE 0x0 +#define FEC_DI_COMM_MB_OBS_OFF 0x0 +#define FEC_DI_COMM_MB_OBS_ON 0x2 + +#define FEC_DI_COMM_INT_REQ__A 0x1C20003 +#define FEC_DI_COMM_INT_REQ__W 1 +#define FEC_DI_COMM_INT_REQ__M 0x1 +#define FEC_DI_COMM_INT_REQ__PRE 0x0 +#define FEC_DI_COMM_INT_STA__A 0x1C20005 +#define FEC_DI_COMM_INT_STA__W 2 +#define FEC_DI_COMM_INT_STA__M 0x3 +#define FEC_DI_COMM_INT_STA__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STA_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_MSK__A 0x1C20006 +#define FEC_DI_COMM_INT_MSK__W 2 +#define FEC_DI_COMM_INT_MSK__M 0x3 +#define FEC_DI_COMM_INT_MSK__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 +#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0 + +#define FEC_DI_COMM_INT_STM__A 0x1C20007 +#define FEC_DI_COMM_INT_STM__W 2 +#define FEC_DI_COMM_INT_STM__M 0x3 +#define FEC_DI_COMM_INT_STM__PRE 0x0 +#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 +#define FEC_DI_COMM_INT_STM_STAT_INT__W 1 +#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1 +#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2 +#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0 + + +#define FEC_DI_STATUS__A 0x1C20010 +#define FEC_DI_STATUS__W 1 +#define FEC_DI_STATUS__M 0x1 +#define FEC_DI_STATUS__PRE 0x0 +#define FEC_DI_MODE__A 0x1C20011 +#define FEC_DI_MODE__W 3 +#define FEC_DI_MODE__M 0x7 +#define FEC_DI_MODE__PRE 0x0 + +#define FEC_DI_MODE_NO_SYNC__B 0 +#define FEC_DI_MODE_NO_SYNC__W 1 +#define FEC_DI_MODE_NO_SYNC__M 0x1 +#define FEC_DI_MODE_NO_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2 +#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0 + +#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 +#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 +#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4 +#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0 + + +#define FEC_DI_CONTROL_WORD__A 0x1C20012 +#define FEC_DI_CONTROL_WORD__W 4 +#define FEC_DI_CONTROL_WORD__M 0xF +#define FEC_DI_CONTROL_WORD__PRE 0x0 + +#define FEC_DI_RESTART__A 0x1C20013 +#define FEC_DI_RESTART__W 1 +#define FEC_DI_RESTART__M 0x1 +#define FEC_DI_RESTART__PRE 0x0 + +#define FEC_DI_TIMEOUT_LO__A 0x1C20014 +#define FEC_DI_TIMEOUT_LO__W 16 +#define FEC_DI_TIMEOUT_LO__M 0xFFFF +#define FEC_DI_TIMEOUT_LO__PRE 0x0 + +#define FEC_DI_TIMEOUT_HI__A 0x1C20015 +#define FEC_DI_TIMEOUT_HI__W 8 +#define FEC_DI_TIMEOUT_HI__M 0xFF +#define FEC_DI_TIMEOUT_HI__PRE 0xA + +#define FEC_DI_INPUT_CTL__A 0x1C20016 +#define FEC_DI_INPUT_CTL__W 1 +#define FEC_DI_INPUT_CTL__M 0x1 +#define FEC_DI_INPUT_CTL__PRE 0x0 + + + +#define FEC_RS_COMM_EXEC__A 0x1C30000 +#define FEC_RS_COMM_EXEC__W 2 +#define FEC_RS_COMM_EXEC__M 0x3 +#define FEC_RS_COMM_EXEC__PRE 0x0 +#define FEC_RS_COMM_EXEC_STOP 0x0 +#define FEC_RS_COMM_EXEC_ACTIVE 0x1 +#define FEC_RS_COMM_EXEC_HOLD 0x2 + +#define FEC_RS_COMM_MB__A 0x1C30002 +#define FEC_RS_COMM_MB__W 2 +#define FEC_RS_COMM_MB__M 0x3 +#define FEC_RS_COMM_MB__PRE 0x0 +#define FEC_RS_COMM_MB_CTL__B 0 +#define FEC_RS_COMM_MB_CTL__W 1 +#define FEC_RS_COMM_MB_CTL__M 0x1 +#define FEC_RS_COMM_MB_CTL__PRE 0x0 +#define FEC_RS_COMM_MB_CTL_OFF 0x0 +#define FEC_RS_COMM_MB_CTL_ON 0x1 +#define FEC_RS_COMM_MB_OBS__B 1 +#define FEC_RS_COMM_MB_OBS__W 1 +#define FEC_RS_COMM_MB_OBS__M 0x2 +#define FEC_RS_COMM_MB_OBS__PRE 0x0 +#define FEC_RS_COMM_MB_OBS_OFF 0x0 +#define FEC_RS_COMM_MB_OBS_ON 0x2 + +#define FEC_RS_COMM_INT_REQ__A 0x1C30003 +#define FEC_RS_COMM_INT_REQ__W 1 +#define FEC_RS_COMM_INT_REQ__M 0x1 +#define FEC_RS_COMM_INT_REQ__PRE 0x0 +#define FEC_RS_COMM_INT_STA__A 0x1C30005 +#define FEC_RS_COMM_INT_STA__W 2 +#define FEC_RS_COMM_INT_STA__M 0x3 +#define FEC_RS_COMM_INT_STA__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1 +#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2 +#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0 + +#define FEC_RS_COMM_INT_MSK__A 0x1C30006 +#define FEC_RS_COMM_INT_MSK__W 2 +#define FEC_RS_COMM_INT_MSK__M 0x3 +#define FEC_RS_COMM_INT_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_COMM_INT_STM__A 0x1C30007 +#define FEC_RS_COMM_INT_STM__W 2 +#define FEC_RS_COMM_INT_STM__M 0x3 +#define FEC_RS_COMM_INT_STM__PRE 0x0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1 +#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2 +#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0 + +#define FEC_RS_STATUS__A 0x1C30010 +#define FEC_RS_STATUS__W 1 +#define FEC_RS_STATUS__M 0x1 +#define FEC_RS_STATUS__PRE 0x0 +#define FEC_RS_MODE__A 0x1C30011 +#define FEC_RS_MODE__W 1 +#define FEC_RS_MODE__M 0x1 +#define FEC_RS_MODE__PRE 0x0 + +#define FEC_RS_MODE_BYPASS__B 0 +#define FEC_RS_MODE_BYPASS__W 1 +#define FEC_RS_MODE_BYPASS__M 0x1 +#define FEC_RS_MODE_BYPASS__PRE 0x0 + +#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 +#define FEC_RS_MEASUREMENT_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF +#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993 + +#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 +#define FEC_RS_MEASUREMENT_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1 + +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF +#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1 + +#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 +#define FEC_RS_NR_BIT_ERRORS__W 16 +#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF +#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 +#define FEC_RS_NR_BIT_ERRORS_EXP__W 4 +#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015 +#define FEC_RS_NR_SYMBOL_ERRORS__W 16 +#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF +#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016 +#define FEC_RS_NR_PACKET_ERRORS__W 16 +#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF +#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF + +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF + +#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 +#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 +#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000 +#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000 + +#define FEC_RS_NR_FAILURES__A 0x1C30017 +#define FEC_RS_NR_FAILURES__W 16 +#define FEC_RS_NR_FAILURES__M 0xFFFF +#define FEC_RS_NR_FAILURES__PRE 0x0 + +#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 +#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 +#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF +#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0 + +#define FEC_RS_NR_FAILURES_EXP__B 12 +#define FEC_RS_NR_FAILURES_EXP__W 4 +#define FEC_RS_NR_FAILURES_EXP__M 0xF000 +#define FEC_RS_NR_FAILURES_EXP__PRE 0x0 + + + +#define FEC_OC_COMM_EXEC__A 0x1C40000 +#define FEC_OC_COMM_EXEC__W 2 +#define FEC_OC_COMM_EXEC__M 0x3 +#define FEC_OC_COMM_EXEC__PRE 0x0 +#define FEC_OC_COMM_EXEC_STOP 0x0 +#define FEC_OC_COMM_EXEC_ACTIVE 0x1 +#define FEC_OC_COMM_EXEC_HOLD 0x2 + +#define FEC_OC_COMM_MB__A 0x1C40002 +#define FEC_OC_COMM_MB__W 2 +#define FEC_OC_COMM_MB__M 0x3 +#define FEC_OC_COMM_MB__PRE 0x0 +#define FEC_OC_COMM_MB_CTL__B 0 +#define FEC_OC_COMM_MB_CTL__W 1 +#define FEC_OC_COMM_MB_CTL__M 0x1 +#define FEC_OC_COMM_MB_CTL__PRE 0x0 +#define FEC_OC_COMM_MB_CTL_OFF 0x0 +#define FEC_OC_COMM_MB_CTL_ON 0x1 +#define FEC_OC_COMM_MB_OBS__B 1 +#define FEC_OC_COMM_MB_OBS__W 1 +#define FEC_OC_COMM_MB_OBS__M 0x2 +#define FEC_OC_COMM_MB_OBS__PRE 0x0 +#define FEC_OC_COMM_MB_OBS_OFF 0x0 +#define FEC_OC_COMM_MB_OBS_ON 0x2 + +#define FEC_OC_COMM_INT_REQ__A 0x1C40003 +#define FEC_OC_COMM_INT_REQ__W 1 +#define FEC_OC_COMM_INT_REQ__M 0x1 +#define FEC_OC_COMM_INT_REQ__PRE 0x0 +#define FEC_OC_COMM_INT_STA__A 0x1C40005 +#define FEC_OC_COMM_INT_STA__W 8 +#define FEC_OC_COMM_INT_STA__M 0xFF +#define FEC_OC_COMM_INT_STA__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1 +#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2 +#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4 +#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8 +#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10 +#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20 +#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40 +#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80 +#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0 + +#define FEC_OC_COMM_INT_MSK__A 0x1C40006 +#define FEC_OC_COMM_INT_MSK__W 8 +#define FEC_OC_COMM_INT_MSK__M 0xFF +#define FEC_OC_COMM_INT_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_COMM_INT_STM__A 0x1C40007 +#define FEC_OC_COMM_INT_STM__W 8 +#define FEC_OC_COMM_INT_STM__M 0xFF +#define FEC_OC_COMM_INT_STM__PRE 0x0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1 +#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2 +#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4 +#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8 +#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10 +#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20 +#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40 +#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80 +#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0 + +#define FEC_OC_STATUS__A 0x1C40010 +#define FEC_OC_STATUS__W 5 +#define FEC_OC_STATUS__M 0x1F +#define FEC_OC_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_DPR_STATUS__B 0 +#define FEC_OC_STATUS_DPR_STATUS__W 1 +#define FEC_OC_STATUS_DPR_STATUS__M 0x1 +#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0 + +#define FEC_OC_STATUS_SNC_STATUS__B 1 +#define FEC_OC_STATUS_SNC_STATUS__W 2 +#define FEC_OC_STATUS_SNC_STATUS__M 0x6 +#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0 +#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0 +#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2 +#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4 + +#define FEC_OC_STATUS_FIFO_FULL__B 3 +#define FEC_OC_STATUS_FIFO_FULL__W 1 +#define FEC_OC_STATUS_FIFO_FULL__M 0x8 +#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0 + +#define FEC_OC_STATUS_FIFO_EMPTY__B 4 +#define FEC_OC_STATUS_FIFO_EMPTY__W 1 +#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10 +#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0 + +#define FEC_OC_MODE__A 0x1C40011 +#define FEC_OC_MODE__W 4 +#define FEC_OC_MODE__M 0xF +#define FEC_OC_MODE__PRE 0x0 + +#define FEC_OC_MODE_PARITY__B 0 +#define FEC_OC_MODE_PARITY__W 1 +#define FEC_OC_MODE_PARITY__M 0x1 +#define FEC_OC_MODE_PARITY__PRE 0x0 + +#define FEC_OC_MODE_TRANSPARENT__B 1 +#define FEC_OC_MODE_TRANSPARENT__W 1 +#define FEC_OC_MODE_TRANSPARENT__M 0x2 +#define FEC_OC_MODE_TRANSPARENT__PRE 0x0 + +#define FEC_OC_MODE_CLEAR__B 2 +#define FEC_OC_MODE_CLEAR__W 1 +#define FEC_OC_MODE_CLEAR__M 0x4 +#define FEC_OC_MODE_CLEAR__PRE 0x0 + +#define FEC_OC_MODE_RETAIN_FRAMING__B 3 +#define FEC_OC_MODE_RETAIN_FRAMING__W 1 +#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8 +#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0 + +#define FEC_OC_DPR_MODE__A 0x1C40012 +#define FEC_OC_DPR_MODE__W 2 +#define FEC_OC_DPR_MODE__M 0x3 +#define FEC_OC_DPR_MODE__PRE 0x0 + +#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 +#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1 +#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0 + +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2 +#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0 + + +#define FEC_OC_DPR_UNLOCK__A 0x1C40013 +#define FEC_OC_DPR_UNLOCK__W 1 +#define FEC_OC_DPR_UNLOCK__M 0x1 +#define FEC_OC_DPR_UNLOCK__PRE 0x0 +#define FEC_OC_DTO_MODE__A 0x1C40014 +#define FEC_OC_DTO_MODE__W 3 +#define FEC_OC_DTO_MODE__M 0x7 +#define FEC_OC_DTO_MODE__PRE 0x0 + +#define FEC_OC_DTO_MODE_DYNAMIC__B 0 +#define FEC_OC_DTO_MODE_DYNAMIC__W 1 +#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 +#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0 + +#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2 +#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0 + +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 +#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0 + + +#define FEC_OC_DTO_PERIOD__A 0x1C40015 +#define FEC_OC_DTO_PERIOD__W 8 +#define FEC_OC_DTO_PERIOD__M 0xFF +#define FEC_OC_DTO_PERIOD__PRE 0x0 +#define FEC_OC_DTO_RATE_LO__A 0x1C40016 +#define FEC_OC_DTO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 +#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 +#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_DTO_RATE_HI__A 0x1C40017 +#define FEC_OC_DTO_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 +#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 +#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF +#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0 + +#define FEC_OC_DTO_BURST_LEN__A 0x1C40018 +#define FEC_OC_DTO_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN__PRE 0xBC + +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF +#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC + +#define FEC_OC_FCT_MODE__A 0x1C4001A +#define FEC_OC_FCT_MODE__W 2 +#define FEC_OC_FCT_MODE__M 0x3 +#define FEC_OC_FCT_MODE__PRE 0x0 + +#define FEC_OC_FCT_MODE_RAT_ENA__B 0 +#define FEC_OC_FCT_MODE_RAT_ENA__W 1 +#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 +#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0 + +#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__W 1 +#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 +#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0 + +#define FEC_OC_FCT_USAGE__A 0x1C4001B +#define FEC_OC_FCT_USAGE__W 3 +#define FEC_OC_FCT_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE__PRE 0x7 + +#define FEC_OC_FCT_USAGE_USAGE__B 0 +#define FEC_OC_FCT_USAGE_USAGE__W 3 +#define FEC_OC_FCT_USAGE_USAGE__M 0x7 +#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7 + +#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C +#define FEC_OC_FCT_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION__PRE 0x0 + +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF +#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0 + +#define FEC_OC_TMD_MODE__A 0x1C4001E +#define FEC_OC_TMD_MODE__W 3 +#define FEC_OC_TMD_MODE__M 0x7 +#define FEC_OC_TMD_MODE__PRE 0x4 + +#define FEC_OC_TMD_MODE_MODE__B 0 +#define FEC_OC_TMD_MODE_MODE__W 3 +#define FEC_OC_TMD_MODE_MODE__M 0x7 +#define FEC_OC_TMD_MODE_MODE__PRE 0x4 + +#define FEC_OC_TMD_COUNT__A 0x1C4001F +#define FEC_OC_TMD_COUNT__W 10 +#define FEC_OC_TMD_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_COUNT_COUNT__B 0 +#define FEC_OC_TMD_COUNT_COUNT__W 10 +#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF +#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4 + +#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 +#define FEC_OC_TMD_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF +#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500 + +#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 +#define FEC_OC_TMD_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF +#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300 + +#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022 +#define FEC_OC_TMD_CTL_UPD_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1 + +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1 + +#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 +#define FEC_OC_TMD_INT_UPD_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4 + +#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 +#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF +#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4 + +#define FEC_OC_AVR_PARM_A__A 0x1C40026 +#define FEC_OC_AVR_PARM_A__W 4 +#define FEC_OC_AVR_PARM_A__M 0xF +#define FEC_OC_AVR_PARM_A__PRE 0x6 + +#define FEC_OC_AVR_PARM_A_PARM__B 0 +#define FEC_OC_AVR_PARM_A_PARM__W 4 +#define FEC_OC_AVR_PARM_A_PARM__M 0xF +#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6 + +#define FEC_OC_AVR_PARM_B__A 0x1C40027 +#define FEC_OC_AVR_PARM_B__W 4 +#define FEC_OC_AVR_PARM_B__M 0xF +#define FEC_OC_AVR_PARM_B__PRE 0x4 + +#define FEC_OC_AVR_PARM_B_PARM__B 0 +#define FEC_OC_AVR_PARM_B_PARM__W 4 +#define FEC_OC_AVR_PARM_B_PARM__M 0xF +#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4 + +#define FEC_OC_AVR_AVG_LO__A 0x1C40028 +#define FEC_OC_AVR_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 +#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 +#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF +#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI__A 0x1C40029 +#define FEC_OC_AVR_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI__PRE 0x0 + +#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 +#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 +#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F +#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0 + +#define FEC_OC_RCN_MODE__A 0x1C4002C +#define FEC_OC_RCN_MODE__W 5 +#define FEC_OC_RCN_MODE__M 0x1F +#define FEC_OC_RCN_MODE__PRE 0x1F + +#define FEC_OC_RCN_MODE_MODE__B 0 +#define FEC_OC_RCN_MODE_MODE__W 5 +#define FEC_OC_RCN_MODE_MODE__M 0x1F +#define FEC_OC_RCN_MODE_MODE__PRE 0x1F + +#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D +#define FEC_OC_RCN_OCC_SETTLE__W 11 +#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400 + +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF +#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400 + +#define FEC_OC_RCN_GAIN__A 0x1C4002E +#define FEC_OC_RCN_GAIN__W 4 +#define FEC_OC_RCN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN__PRE 0xC + +#define FEC_OC_RCN_GAIN_GAIN__B 0 +#define FEC_OC_RCN_GAIN_GAIN__W 4 +#define FEC_OC_RCN_GAIN_GAIN__M 0xF +#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC + +#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 +#define FEC_OC_RCN_CTL_RATE_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031 +#define FEC_OC_RCN_CTL_RATE_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0 + +#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 +#define FEC_OC_RCN_CTL_STEP_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF +#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0 + +#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 +#define FEC_OC_RCN_CTL_STEP_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8 + +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF +#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8 + +#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034 +#define FEC_OC_RCN_DTO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035 +#define FEC_OC_RCN_DTO_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036 +#define FEC_OC_RCN_DTO_RATE_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF +#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037 +#define FEC_OC_RCN_DTO_RATE_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF +#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038 +#define FEC_OC_RCN_RATE_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF +#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0 + +#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039 +#define FEC_OC_RCN_RATE_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF +#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0 + +#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A +#define FEC_OC_RCN_DYN_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF +#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B +#define FEC_OC_RCN_DYN_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0 + +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF +#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0 + +#define FEC_OC_SNC_MODE__A 0x1C40040 +#define FEC_OC_SNC_MODE__W 5 +#define FEC_OC_SNC_MODE__M 0x1F +#define FEC_OC_SNC_MODE__PRE 0x0 + +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1 +#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 +#define FEC_OC_SNC_MODE_ERROR_CTL__W 2 +#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6 +#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0 + +#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 +#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 +#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8 +#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0 + +#define FEC_OC_SNC_MODE_SHUTDOWN__B 4 +#define FEC_OC_SNC_MODE_SHUTDOWN__W 1 +#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 +#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0 + +#define FEC_OC_SNC_LWM__A 0x1C40041 +#define FEC_OC_SNC_LWM__W 4 +#define FEC_OC_SNC_LWM__M 0xF +#define FEC_OC_SNC_LWM__PRE 0x3 + +#define FEC_OC_SNC_LWM_MARK__B 0 +#define FEC_OC_SNC_LWM_MARK__W 4 +#define FEC_OC_SNC_LWM_MARK__M 0xF +#define FEC_OC_SNC_LWM_MARK__PRE 0x3 + +#define FEC_OC_SNC_HWM__A 0x1C40042 +#define FEC_OC_SNC_HWM__W 4 +#define FEC_OC_SNC_HWM__M 0xF +#define FEC_OC_SNC_HWM__PRE 0x5 + +#define FEC_OC_SNC_HWM_MARK__B 0 +#define FEC_OC_SNC_HWM_MARK__W 4 +#define FEC_OC_SNC_HWM_MARK__M 0xF +#define FEC_OC_SNC_HWM_MARK__PRE 0x5 + +#define FEC_OC_SNC_UNLOCK__A 0x1C40043 +#define FEC_OC_SNC_UNLOCK__W 1 +#define FEC_OC_SNC_UNLOCK__M 0x1 +#define FEC_OC_SNC_UNLOCK__PRE 0x0 + +#define FEC_OC_SNC_UNLOCK_RESTART__B 0 +#define FEC_OC_SNC_UNLOCK_RESTART__W 1 +#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1 +#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044 +#define FEC_OC_SNC_LOCK_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0 + +#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 +#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045 +#define FEC_OC_SNC_FAIL_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 +#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF +#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 +#define FEC_OC_SNC_FAIL_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171 + +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF +#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171 + +#define FEC_OC_EMS_MODE__A 0x1C40047 +#define FEC_OC_EMS_MODE__W 2 +#define FEC_OC_EMS_MODE__M 0x3 +#define FEC_OC_EMS_MODE__PRE 0x0 + +#define FEC_OC_EMS_MODE_MODE__B 0 +#define FEC_OC_EMS_MODE_MODE__W 2 +#define FEC_OC_EMS_MODE_MODE__M 0x3 +#define FEC_OC_EMS_MODE_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE__A 0x1C40048 +#define FEC_OC_IPR_MODE__W 12 +#define FEC_OC_IPR_MODE__M 0xFFF +#define FEC_OC_IPR_MODE__PRE 0x0 + +#define FEC_OC_IPR_MODE_SERIAL__B 0 +#define FEC_OC_IPR_MODE_SERIAL__W 1 +#define FEC_OC_IPR_MODE_SERIAL__M 0x1 +#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0 + +#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2 +#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 +#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8 +#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 +#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20 +#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40 +#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80 +#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100 +#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200 +#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400 +#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800 +#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT__A 0x1C40049 +#define FEC_OC_IPR_INVERT__W 12 +#define FEC_OC_IPR_INVERT__M 0xFFF +#define FEC_OC_IPR_INVERT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD0__B 0 +#define FEC_OC_IPR_INVERT_MD0__W 1 +#define FEC_OC_IPR_INVERT_MD0__M 0x1 +#define FEC_OC_IPR_INVERT_MD0__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD1__B 1 +#define FEC_OC_IPR_INVERT_MD1__W 1 +#define FEC_OC_IPR_INVERT_MD1__M 0x2 +#define FEC_OC_IPR_INVERT_MD1__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD2__B 2 +#define FEC_OC_IPR_INVERT_MD2__W 1 +#define FEC_OC_IPR_INVERT_MD2__M 0x4 +#define FEC_OC_IPR_INVERT_MD2__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD3__B 3 +#define FEC_OC_IPR_INVERT_MD3__W 1 +#define FEC_OC_IPR_INVERT_MD3__M 0x8 +#define FEC_OC_IPR_INVERT_MD3__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD4__B 4 +#define FEC_OC_IPR_INVERT_MD4__W 1 +#define FEC_OC_IPR_INVERT_MD4__M 0x10 +#define FEC_OC_IPR_INVERT_MD4__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD5__B 5 +#define FEC_OC_IPR_INVERT_MD5__W 1 +#define FEC_OC_IPR_INVERT_MD5__M 0x20 +#define FEC_OC_IPR_INVERT_MD5__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD6__B 6 +#define FEC_OC_IPR_INVERT_MD6__W 1 +#define FEC_OC_IPR_INVERT_MD6__M 0x40 +#define FEC_OC_IPR_INVERT_MD6__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MD7__B 7 +#define FEC_OC_IPR_INVERT_MD7__W 1 +#define FEC_OC_IPR_INVERT_MD7__M 0x80 +#define FEC_OC_IPR_INVERT_MD7__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MERR__B 8 +#define FEC_OC_IPR_INVERT_MERR__W 1 +#define FEC_OC_IPR_INVERT_MERR__M 0x100 +#define FEC_OC_IPR_INVERT_MERR__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MSTRT__B 9 +#define FEC_OC_IPR_INVERT_MSTRT__W 1 +#define FEC_OC_IPR_INVERT_MSTRT__M 0x200 +#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MVAL__B 10 +#define FEC_OC_IPR_INVERT_MVAL__W 1 +#define FEC_OC_IPR_INVERT_MVAL__M 0x400 +#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0 + +#define FEC_OC_IPR_INVERT_MCLK__B 11 +#define FEC_OC_IPR_INVERT_MCLK__W 1 +#define FEC_OC_IPR_INVERT_MCLK__M 0x800 +#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0 + +#define FEC_OC_OCR_MODE__A 0x1C40050 +#define FEC_OC_OCR_MODE__W 4 +#define FEC_OC_OCR_MODE__M 0xF +#define FEC_OC_OCR_MODE__PRE 0x0 + +#define FEC_OC_OCR_MODE_MB_SELECT__B 0 +#define FEC_OC_OCR_MODE_MB_SELECT__W 1 +#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1 +#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2 +#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 +#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 +#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4 +#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0 + +#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8 +#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0 + +#define FEC_OC_OCR_RATE__A 0x1C40051 +#define FEC_OC_OCR_RATE__W 4 +#define FEC_OC_OCR_RATE__M 0xF +#define FEC_OC_OCR_RATE__PRE 0x0 + +#define FEC_OC_OCR_RATE_RATE__B 0 +#define FEC_OC_OCR_RATE_RATE__W 4 +#define FEC_OC_OCR_RATE_RATE__M 0xF +#define FEC_OC_OCR_RATE_RATE__PRE 0x0 + +#define FEC_OC_OCR_INVERT__A 0x1C40052 +#define FEC_OC_OCR_INVERT__W 12 +#define FEC_OC_OCR_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT__PRE 0x800 + +#define FEC_OC_OCR_INVERT_INVERT__B 0 +#define FEC_OC_OCR_INVERT_INVERT__W 12 +#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF +#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800 + +#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053 +#define FEC_OC_OCR_GRAB_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 +#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF +#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054 +#define FEC_OC_OCR_GRAB_SYNC__W 8 +#define FEC_OC_OCR_GRAB_SYNC__M 0xFF +#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7 +#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78 +#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80 +#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055 +#define FEC_OC_OCR_GRAB_RD0__W 10 +#define FEC_OC_OCR_GRAB_RD0__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD0_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056 +#define FEC_OC_OCR_GRAB_RD1__W 10 +#define FEC_OC_OCR_GRAB_RD1__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD1_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057 +#define FEC_OC_OCR_GRAB_RD2__W 10 +#define FEC_OC_OCR_GRAB_RD2__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD2_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058 +#define FEC_OC_OCR_GRAB_RD3__W 10 +#define FEC_OC_OCR_GRAB_RD3__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD3_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059 +#define FEC_OC_OCR_GRAB_RD4__W 10 +#define FEC_OC_OCR_GRAB_RD4__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD4_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A +#define FEC_OC_OCR_GRAB_RD5__W 10 +#define FEC_OC_OCR_GRAB_RD5__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5__PRE 0x0 + +#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 +#define FEC_OC_OCR_GRAB_RD5_DATA__W 10 +#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF +#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0 + + + +#define FEC_DI_RAM__A 0x1C50000 + + + +#define FEC_RS_RAM__A 0x1C60000 + + + +#define FEC_OC_RAM__A 0x1C70000 + + + + + +#define IQM_COMM_EXEC__A 0x1800000 +#define IQM_COMM_EXEC__W 2 +#define IQM_COMM_EXEC__M 0x3 +#define IQM_COMM_EXEC__PRE 0x0 +#define IQM_COMM_EXEC_B__B 0 +#define IQM_COMM_EXEC_B__W 2 +#define IQM_COMM_EXEC_B__M 0x3 +#define IQM_COMM_EXEC_B__PRE 0x0 +#define IQM_COMM_EXEC_B_STOP 0x0 +#define IQM_COMM_EXEC_B_ACTIVE 0x1 +#define IQM_COMM_EXEC_B_HOLD 0x2 + +#define IQM_COMM_MB__A 0x1800002 +#define IQM_COMM_MB__W 16 +#define IQM_COMM_MB__M 0xFFFF +#define IQM_COMM_MB__PRE 0x0 +#define IQM_COMM_MB_B__B 0 +#define IQM_COMM_MB_B__W 16 +#define IQM_COMM_MB_B__M 0xFFFF +#define IQM_COMM_MB_B__PRE 0x0 + +#define IQM_COMM_INT_REQ__A 0x1800003 +#define IQM_COMM_INT_REQ__W 3 +#define IQM_COMM_INT_REQ__M 0x7 +#define IQM_COMM_INT_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_AF_REQ__B 0 +#define IQM_COMM_INT_REQ_AF_REQ__W 1 +#define IQM_COMM_INT_REQ_AF_REQ__M 0x1 +#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CF_REQ__B 1 +#define IQM_COMM_INT_REQ_CF_REQ__W 1 +#define IQM_COMM_INT_REQ_CF_REQ__M 0x2 +#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0 + +#define IQM_COMM_INT_REQ_CW_REQ__B 2 +#define IQM_COMM_INT_REQ_CW_REQ__W 1 +#define IQM_COMM_INT_REQ_CW_REQ__M 0x4 +#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0 + +#define IQM_COMM_INT_STA__A 0x1800005 +#define IQM_COMM_INT_STA__W 16 +#define IQM_COMM_INT_STA__M 0xFFFF +#define IQM_COMM_INT_STA__PRE 0x0 +#define IQM_COMM_INT_STA_B__B 0 +#define IQM_COMM_INT_STA_B__W 16 +#define IQM_COMM_INT_STA_B__M 0xFFFF +#define IQM_COMM_INT_STA_B__PRE 0x0 + +#define IQM_COMM_INT_MSK__A 0x1800006 +#define IQM_COMM_INT_MSK__W 16 +#define IQM_COMM_INT_MSK__M 0xFFFF +#define IQM_COMM_INT_MSK__PRE 0x0 +#define IQM_COMM_INT_MSK_B__B 0 +#define IQM_COMM_INT_MSK_B__W 16 +#define IQM_COMM_INT_MSK_B__M 0xFFFF +#define IQM_COMM_INT_MSK_B__PRE 0x0 + +#define IQM_COMM_INT_STM__A 0x1800007 +#define IQM_COMM_INT_STM__W 16 +#define IQM_COMM_INT_STM__M 0xFFFF +#define IQM_COMM_INT_STM__PRE 0x0 +#define IQM_COMM_INT_STM_B__B 0 +#define IQM_COMM_INT_STM_B__W 16 +#define IQM_COMM_INT_STM_B__M 0xFFFF +#define IQM_COMM_INT_STM_B__PRE 0x0 + + + +#define IQM_FS_COMM_EXEC__A 0x1820000 +#define IQM_FS_COMM_EXEC__W 2 +#define IQM_FS_COMM_EXEC__M 0x3 +#define IQM_FS_COMM_EXEC__PRE 0x0 +#define IQM_FS_COMM_EXEC_STOP 0x0 +#define IQM_FS_COMM_EXEC_ACTIVE 0x1 +#define IQM_FS_COMM_EXEC_HOLD 0x2 + +#define IQM_FS_COMM_MB__A 0x1820002 +#define IQM_FS_COMM_MB__W 4 +#define IQM_FS_COMM_MB__M 0xF +#define IQM_FS_COMM_MB__PRE 0x0 +#define IQM_FS_COMM_MB_CTL__B 0 +#define IQM_FS_COMM_MB_CTL__W 1 +#define IQM_FS_COMM_MB_CTL__M 0x1 +#define IQM_FS_COMM_MB_CTL__PRE 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FS_COMM_MB_OBS__B 1 +#define IQM_FS_COMM_MB_OBS__W 1 +#define IQM_FS_COMM_MB_OBS__M 0x2 +#define IQM_FS_COMM_MB_OBS__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_FS_COMM_MB_CTL_MUX__B 2 +#define IQM_FS_COMM_MB_CTL_MUX__W 1 +#define IQM_FS_COMM_MB_CTL_MUX__M 0x4 +#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0 +#define IQM_FS_COMM_MB_OBS_MUX__B 3 +#define IQM_FS_COMM_MB_OBS_MUX__W 1 +#define IQM_FS_COMM_MB_OBS_MUX__M 0x8 +#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0 + +#define IQM_FS_RATE_OFS_LO__A 0x1820010 +#define IQM_FS_RATE_OFS_LO__W 16 +#define IQM_FS_RATE_OFS_LO__M 0xFFFF +#define IQM_FS_RATE_OFS_LO__PRE 0x0 +#define IQM_FS_RATE_OFS_LO_B__B 0 +#define IQM_FS_RATE_OFS_LO_B__W 16 +#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF +#define IQM_FS_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_FS_RATE_OFS_HI__A 0x1820011 +#define IQM_FS_RATE_OFS_HI__W 12 +#define IQM_FS_RATE_OFS_HI__M 0xFFF +#define IQM_FS_RATE_OFS_HI__PRE 0x0 +#define IQM_FS_RATE_OFS_HI_B__B 0 +#define IQM_FS_RATE_OFS_HI_B__W 12 +#define IQM_FS_RATE_OFS_HI_B__M 0xFFF +#define IQM_FS_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_FS_RATE_LO__A 0x1820012 +#define IQM_FS_RATE_LO__W 16 +#define IQM_FS_RATE_LO__M 0xFFFF +#define IQM_FS_RATE_LO__PRE 0x0 +#define IQM_FS_RATE_LO_B__B 0 +#define IQM_FS_RATE_LO_B__W 16 +#define IQM_FS_RATE_LO_B__M 0xFFFF +#define IQM_FS_RATE_LO_B__PRE 0x0 + +#define IQM_FS_RATE_HI__A 0x1820013 +#define IQM_FS_RATE_HI__W 12 +#define IQM_FS_RATE_HI__M 0xFFF +#define IQM_FS_RATE_HI__PRE 0x0 +#define IQM_FS_RATE_HI_B__B 0 +#define IQM_FS_RATE_HI_B__W 12 +#define IQM_FS_RATE_HI_B__M 0xFFF +#define IQM_FS_RATE_HI_B__PRE 0x0 + +#define IQM_FS_ADJ_SEL__A 0x1820014 +#define IQM_FS_ADJ_SEL__W 2 +#define IQM_FS_ADJ_SEL__M 0x3 +#define IQM_FS_ADJ_SEL__PRE 0x0 + +#define IQM_FS_ADJ_SEL_B__B 0 +#define IQM_FS_ADJ_SEL_B__W 2 +#define IQM_FS_ADJ_SEL_B__M 0x3 +#define IQM_FS_ADJ_SEL_B__PRE 0x0 +#define IQM_FS_ADJ_SEL_B_OFF 0x0 +#define IQM_FS_ADJ_SEL_B_QAM 0x1 +#define IQM_FS_ADJ_SEL_B_VSB 0x2 + + + +#define IQM_FD_COMM_EXEC__A 0x1830000 +#define IQM_FD_COMM_EXEC__W 2 +#define IQM_FD_COMM_EXEC__M 0x3 +#define IQM_FD_COMM_EXEC__PRE 0x0 +#define IQM_FD_COMM_EXEC_STOP 0x0 +#define IQM_FD_COMM_EXEC_ACTIVE 0x1 +#define IQM_FD_COMM_EXEC_HOLD 0x2 + +#define IQM_FD_COMM_MB__A 0x1830002 +#define IQM_FD_COMM_MB__W 2 +#define IQM_FD_COMM_MB__M 0x3 +#define IQM_FD_COMM_MB__PRE 0x0 +#define IQM_FD_COMM_MB_CTL__B 0 +#define IQM_FD_COMM_MB_CTL__W 1 +#define IQM_FD_COMM_MB_CTL__M 0x1 +#define IQM_FD_COMM_MB_CTL__PRE 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_FD_COMM_MB_OBS__B 1 +#define IQM_FD_COMM_MB_OBS__W 1 +#define IQM_FD_COMM_MB_OBS__M 0x2 +#define IQM_FD_COMM_MB_OBS__PRE 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_FD_RATESEL__A 0x1830010 +#define IQM_FD_RATESEL__W 2 +#define IQM_FD_RATESEL__M 0x3 +#define IQM_FD_RATESEL__PRE 0x0 +#define IQM_FD_RATESEL_B__B 0 +#define IQM_FD_RATESEL_B__W 2 +#define IQM_FD_RATESEL_B__M 0x3 +#define IQM_FD_RATESEL_B__PRE 0x0 +#define IQM_FD_RATESEL_B_DS0 0x0 +#define IQM_FD_RATESEL_B_DS1 0x1 +#define IQM_FD_RATESEL_B_DS2 0x2 +#define IQM_FD_RATESEL_B_DS3 0x3 + + + +#define IQM_RC_COMM_EXEC__A 0x1840000 +#define IQM_RC_COMM_EXEC__W 2 +#define IQM_RC_COMM_EXEC__M 0x3 +#define IQM_RC_COMM_EXEC__PRE 0x0 +#define IQM_RC_COMM_EXEC_STOP 0x0 +#define IQM_RC_COMM_EXEC_ACTIVE 0x1 +#define IQM_RC_COMM_EXEC_HOLD 0x2 + +#define IQM_RC_COMM_MB__A 0x1840002 +#define IQM_RC_COMM_MB__W 2 +#define IQM_RC_COMM_MB__M 0x3 +#define IQM_RC_COMM_MB__PRE 0x0 +#define IQM_RC_COMM_MB_CTL__B 0 +#define IQM_RC_COMM_MB_CTL__W 1 +#define IQM_RC_COMM_MB_CTL__M 0x1 +#define IQM_RC_COMM_MB_CTL__PRE 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RC_COMM_MB_OBS__B 1 +#define IQM_RC_COMM_MB_OBS__W 1 +#define IQM_RC_COMM_MB_OBS__M 0x2 +#define IQM_RC_COMM_MB_OBS__PRE 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RC_RATE_OFS_LO__A 0x1840010 +#define IQM_RC_RATE_OFS_LO__W 16 +#define IQM_RC_RATE_OFS_LO__M 0xFFFF +#define IQM_RC_RATE_OFS_LO__PRE 0x0 +#define IQM_RC_RATE_OFS_LO_B__B 0 +#define IQM_RC_RATE_OFS_LO_B__W 16 +#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF +#define IQM_RC_RATE_OFS_LO_B__PRE 0x0 + +#define IQM_RC_RATE_OFS_HI__A 0x1840011 +#define IQM_RC_RATE_OFS_HI__W 8 +#define IQM_RC_RATE_OFS_HI__M 0xFF +#define IQM_RC_RATE_OFS_HI__PRE 0x0 +#define IQM_RC_RATE_OFS_HI_B__B 0 +#define IQM_RC_RATE_OFS_HI_B__W 8 +#define IQM_RC_RATE_OFS_HI_B__M 0xFF +#define IQM_RC_RATE_OFS_HI_B__PRE 0x0 + +#define IQM_RC_RATE_LO__A 0x1840012 +#define IQM_RC_RATE_LO__W 16 +#define IQM_RC_RATE_LO__M 0xFFFF +#define IQM_RC_RATE_LO__PRE 0x0 +#define IQM_RC_RATE_LO_B__B 0 +#define IQM_RC_RATE_LO_B__W 16 +#define IQM_RC_RATE_LO_B__M 0xFFFF +#define IQM_RC_RATE_LO_B__PRE 0x0 + +#define IQM_RC_RATE_HI__A 0x1840013 +#define IQM_RC_RATE_HI__W 8 +#define IQM_RC_RATE_HI__M 0xFF +#define IQM_RC_RATE_HI__PRE 0x0 +#define IQM_RC_RATE_HI_B__B 0 +#define IQM_RC_RATE_HI_B__W 8 +#define IQM_RC_RATE_HI_B__M 0xFF +#define IQM_RC_RATE_HI_B__PRE 0x0 + +#define IQM_RC_ADJ_SEL__A 0x1840014 +#define IQM_RC_ADJ_SEL__W 2 +#define IQM_RC_ADJ_SEL__M 0x3 +#define IQM_RC_ADJ_SEL__PRE 0x0 + +#define IQM_RC_ADJ_SEL_B__B 0 +#define IQM_RC_ADJ_SEL_B__W 2 +#define IQM_RC_ADJ_SEL_B__M 0x3 +#define IQM_RC_ADJ_SEL_B__PRE 0x0 +#define IQM_RC_ADJ_SEL_B_OFF 0x0 +#define IQM_RC_ADJ_SEL_B_QAM 0x1 +#define IQM_RC_ADJ_SEL_B_VSB 0x2 + +#define IQM_RC_CROUT_ENA__A 0x1840015 +#define IQM_RC_CROUT_ENA__W 1 +#define IQM_RC_CROUT_ENA__M 0x1 +#define IQM_RC_CROUT_ENA__PRE 0x0 + +#define IQM_RC_CROUT_ENA_ENA__B 0 +#define IQM_RC_CROUT_ENA_ENA__W 1 +#define IQM_RC_CROUT_ENA_ENA__M 0x1 +#define IQM_RC_CROUT_ENA_ENA__PRE 0x0 + +#define IQM_RC_STRETCH__A 0x1840016 +#define IQM_RC_STRETCH__W 5 +#define IQM_RC_STRETCH__M 0x1F +#define IQM_RC_STRETCH__PRE 0x0 + +#define IQM_RC_STRETCH_B__B 0 +#define IQM_RC_STRETCH_B__W 5 +#define IQM_RC_STRETCH_B__M 0x1F +#define IQM_RC_STRETCH_B__PRE 0x0 + + + +#define IQM_RT_COMM_EXEC__A 0x1850000 +#define IQM_RT_COMM_EXEC__W 2 +#define IQM_RT_COMM_EXEC__M 0x3 +#define IQM_RT_COMM_EXEC__PRE 0x0 +#define IQM_RT_COMM_EXEC_STOP 0x0 +#define IQM_RT_COMM_EXEC_ACTIVE 0x1 +#define IQM_RT_COMM_EXEC_HOLD 0x2 + +#define IQM_RT_COMM_MB__A 0x1850002 +#define IQM_RT_COMM_MB__W 2 +#define IQM_RT_COMM_MB__M 0x3 +#define IQM_RT_COMM_MB__PRE 0x0 +#define IQM_RT_COMM_MB_CTL__B 0 +#define IQM_RT_COMM_MB_CTL__W 1 +#define IQM_RT_COMM_MB_CTL__M 0x1 +#define IQM_RT_COMM_MB_CTL__PRE 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_RT_COMM_MB_OBS__B 1 +#define IQM_RT_COMM_MB_OBS__W 1 +#define IQM_RT_COMM_MB_OBS__M 0x2 +#define IQM_RT_COMM_MB_OBS__PRE 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_RT_ACTIVE__A 0x1850010 +#define IQM_RT_ACTIVE__W 2 +#define IQM_RT_ACTIVE__M 0x3 +#define IQM_RT_ACTIVE__PRE 0x0 + +#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 +#define IQM_RT_ACTIVE_ACTIVE_RT__W 1 +#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1 +#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1 + +#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__W 1 +#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2 +#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0 +#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2 + + +#define IQM_RT_LO_INCR__A 0x1850011 +#define IQM_RT_LO_INCR__W 12 +#define IQM_RT_LO_INCR__M 0xFFF +#define IQM_RT_LO_INCR__PRE 0x588 +#define IQM_RT_LO_INCR_FM 0x0 +#define IQM_RT_LO_INCR_MN 0x588 + +#define IQM_RT_ROT_BP__A 0x1850012 +#define IQM_RT_ROT_BP__W 3 +#define IQM_RT_ROT_BP__M 0x7 +#define IQM_RT_ROT_BP__PRE 0x0 + +#define IQM_RT_ROT_BP_ROT_OFF__B 0 +#define IQM_RT_ROT_BP_ROT_OFF__W 1 +#define IQM_RT_ROT_BP_ROT_OFF__M 0x1 +#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0 +#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1 + +#define IQM_RT_ROT_BP_ROT_BPF__B 1 +#define IQM_RT_ROT_BP_ROT_BPF__W 1 +#define IQM_RT_ROT_BP_ROT_BPF__M 0x2 +#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0 + +#define IQM_RT_ROT_BP_MIX_BP__B 2 +#define IQM_RT_ROT_BP_MIX_BP__W 1 +#define IQM_RT_ROT_BP_MIX_BP__M 0x4 +#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0 + + +#define IQM_RT_LP_BP__A 0x1850013 +#define IQM_RT_LP_BP__W 1 +#define IQM_RT_LP_BP__M 0x1 +#define IQM_RT_LP_BP__PRE 0x0 + +#define IQM_RT_DELAY__A 0x1850014 +#define IQM_RT_DELAY__W 7 +#define IQM_RT_DELAY__M 0x7F +#define IQM_RT_DELAY__PRE 0x45 + + + +#define IQM_CF_COMM_EXEC__A 0x1860000 +#define IQM_CF_COMM_EXEC__W 2 +#define IQM_CF_COMM_EXEC__M 0x3 +#define IQM_CF_COMM_EXEC__PRE 0x0 +#define IQM_CF_COMM_EXEC_STOP 0x0 +#define IQM_CF_COMM_EXEC_ACTIVE 0x1 +#define IQM_CF_COMM_EXEC_HOLD 0x2 + +#define IQM_CF_COMM_MB__A 0x1860002 +#define IQM_CF_COMM_MB__W 2 +#define IQM_CF_COMM_MB__M 0x3 +#define IQM_CF_COMM_MB__PRE 0x0 +#define IQM_CF_COMM_MB_CTL__B 0 +#define IQM_CF_COMM_MB_CTL__W 1 +#define IQM_CF_COMM_MB_CTL__M 0x1 +#define IQM_CF_COMM_MB_CTL__PRE 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_CF_COMM_MB_OBS__B 1 +#define IQM_CF_COMM_MB_OBS__W 1 +#define IQM_CF_COMM_MB_OBS__M 0x2 +#define IQM_CF_COMM_MB_OBS__PRE 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2 + +#define IQM_CF_COMM_INT_REQ__A 0x1860003 +#define IQM_CF_COMM_INT_REQ__W 1 +#define IQM_CF_COMM_INT_REQ__M 0x1 +#define IQM_CF_COMM_INT_REQ__PRE 0x0 +#define IQM_CF_COMM_INT_STA__A 0x1860005 +#define IQM_CF_COMM_INT_STA__W 2 +#define IQM_CF_COMM_INT_STA__M 0x3 +#define IQM_CF_COMM_INT_STA__PRE 0x0 +#define IQM_CF_COMM_INT_STA_PM__B 0 +#define IQM_CF_COMM_INT_STA_PM__W 1 +#define IQM_CF_COMM_INT_STA_PM__M 0x1 +#define IQM_CF_COMM_INT_STA_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STA_INC__B 1 +#define IQM_CF_COMM_INT_STA_INC__W 1 +#define IQM_CF_COMM_INT_STA_INC__M 0x2 +#define IQM_CF_COMM_INT_STA_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_MSK__A 0x1860006 +#define IQM_CF_COMM_INT_MSK__W 2 +#define IQM_CF_COMM_INT_MSK__M 0x3 +#define IQM_CF_COMM_INT_MSK__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_PM__B 0 +#define IQM_CF_COMM_INT_MSK_PM__W 1 +#define IQM_CF_COMM_INT_MSK_PM__M 0x1 +#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0 +#define IQM_CF_COMM_INT_MSK_INC__B 1 +#define IQM_CF_COMM_INT_MSK_INC__W 1 +#define IQM_CF_COMM_INT_MSK_INC__M 0x2 +#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0 + +#define IQM_CF_COMM_INT_STM__A 0x1860007 +#define IQM_CF_COMM_INT_STM__W 2 +#define IQM_CF_COMM_INT_STM__M 0x3 +#define IQM_CF_COMM_INT_STM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_PM__B 0 +#define IQM_CF_COMM_INT_STM_PM__W 1 +#define IQM_CF_COMM_INT_STM_PM__M 0x1 +#define IQM_CF_COMM_INT_STM_PM__PRE 0x0 +#define IQM_CF_COMM_INT_STM_INC__B 1 +#define IQM_CF_COMM_INT_STM_INC__W 1 +#define IQM_CF_COMM_INT_STM_INC__M 0x2 +#define IQM_CF_COMM_INT_STM_INC__PRE 0x0 + +#define IQM_CF_SYMMETRIC__A 0x1860010 +#define IQM_CF_SYMMETRIC__W 2 +#define IQM_CF_SYMMETRIC__M 0x3 +#define IQM_CF_SYMMETRIC__PRE 0x0 + +#define IQM_CF_SYMMETRIC_RE__B 0 +#define IQM_CF_SYMMETRIC_RE__W 1 +#define IQM_CF_SYMMETRIC_RE__M 0x1 +#define IQM_CF_SYMMETRIC_RE__PRE 0x0 + +#define IQM_CF_SYMMETRIC_IM__B 1 +#define IQM_CF_SYMMETRIC_IM__W 1 +#define IQM_CF_SYMMETRIC_IM__M 0x2 +#define IQM_CF_SYMMETRIC_IM__PRE 0x0 + +#define IQM_CF_MIDTAP__A 0x1860011 +#define IQM_CF_MIDTAP__W 3 +#define IQM_CF_MIDTAP__M 0x7 +#define IQM_CF_MIDTAP__PRE 0x3 + +#define IQM_CF_MIDTAP_RE__B 0 +#define IQM_CF_MIDTAP_RE__W 1 +#define IQM_CF_MIDTAP_RE__M 0x1 +#define IQM_CF_MIDTAP_RE__PRE 0x1 + +#define IQM_CF_MIDTAP_IM__B 1 +#define IQM_CF_MIDTAP_IM__W 1 +#define IQM_CF_MIDTAP_IM__M 0x2 +#define IQM_CF_MIDTAP_IM__PRE 0x2 + +#define IQM_CF_MIDTAP_SCALE__B 2 +#define IQM_CF_MIDTAP_SCALE__W 1 +#define IQM_CF_MIDTAP_SCALE__M 0x4 +#define IQM_CF_MIDTAP_SCALE__PRE 0x0 + +#define IQM_CF_OUT_ENA__A 0x1860012 +#define IQM_CF_OUT_ENA__W 3 +#define IQM_CF_OUT_ENA__M 0x7 +#define IQM_CF_OUT_ENA__PRE 0x0 + +#define IQM_CF_OUT_ENA_ATV__B 0 +#define IQM_CF_OUT_ENA_ATV__W 1 +#define IQM_CF_OUT_ENA_ATV__M 0x1 +#define IQM_CF_OUT_ENA_ATV__PRE 0x0 + +#define IQM_CF_OUT_ENA_QAM__B 1 +#define IQM_CF_OUT_ENA_QAM__W 1 +#define IQM_CF_OUT_ENA_QAM__M 0x2 +#define IQM_CF_OUT_ENA_QAM__PRE 0x0 + +#define IQM_CF_OUT_ENA_OFDM__B 2 +#define IQM_CF_OUT_ENA_OFDM__W 1 +#define IQM_CF_OUT_ENA_OFDM__M 0x4 +#define IQM_CF_OUT_ENA_OFDM__PRE 0x0 + +#define IQM_CF_ADJ_SEL__A 0x1860013 +#define IQM_CF_ADJ_SEL__W 2 +#define IQM_CF_ADJ_SEL__M 0x3 +#define IQM_CF_ADJ_SEL__PRE 0x0 + +#define IQM_CF_ADJ_SEL_B__B 0 +#define IQM_CF_ADJ_SEL_B__W 2 +#define IQM_CF_ADJ_SEL_B__M 0x3 +#define IQM_CF_ADJ_SEL_B__PRE 0x0 + +#define IQM_CF_SCALE__A 0x1860014 +#define IQM_CF_SCALE__W 14 +#define IQM_CF_SCALE__M 0x3FFF +#define IQM_CF_SCALE__PRE 0x400 +#define IQM_CF_SCALE_B__B 0 +#define IQM_CF_SCALE_B__W 14 +#define IQM_CF_SCALE_B__M 0x3FFF +#define IQM_CF_SCALE_B__PRE 0x400 + +#define IQM_CF_SCALE_SH__A 0x1860015 +#define IQM_CF_SCALE_SH__W 2 +#define IQM_CF_SCALE_SH__M 0x3 +#define IQM_CF_SCALE_SH__PRE 0x0 + +#define IQM_CF_SCALE_SH_B__B 0 +#define IQM_CF_SCALE_SH_B__W 2 +#define IQM_CF_SCALE_SH_B__M 0x3 +#define IQM_CF_SCALE_SH_B__PRE 0x0 + +#define IQM_CF_AMP__A 0x1860016 +#define IQM_CF_AMP__W 14 +#define IQM_CF_AMP__M 0x3FFF +#define IQM_CF_AMP__PRE 0x0 + +#define IQM_CF_AMP_B__B 0 +#define IQM_CF_AMP_B__W 14 +#define IQM_CF_AMP_B__M 0x3FFF +#define IQM_CF_AMP_B__PRE 0x0 + +#define IQM_CF_POW_MEAS_LEN__A 0x1860017 +#define IQM_CF_POW_MEAS_LEN__W 3 +#define IQM_CF_POW_MEAS_LEN__M 0x7 +#define IQM_CF_POW_MEAS_LEN__PRE 0x2 + +#define IQM_CF_POW_MEAS_LEN_B__B 0 +#define IQM_CF_POW_MEAS_LEN_B__W 3 +#define IQM_CF_POW_MEAS_LEN_B__M 0x7 +#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2 + +#define IQM_CF_POW__A 0x1860018 +#define IQM_CF_POW__W 16 +#define IQM_CF_POW__M 0xFFFF +#define IQM_CF_POW__PRE 0x2 +#define IQM_CF_POW_B__B 0 +#define IQM_CF_POW_B__W 16 +#define IQM_CF_POW_B__M 0xFFFF +#define IQM_CF_POW_B__PRE 0x2 + +#define IQM_CF_DS_ENA__A 0x1860019 +#define IQM_CF_DS_ENA__W 3 +#define IQM_CF_DS_ENA__M 0x7 +#define IQM_CF_DS_ENA__PRE 0x4 + +#define IQM_CF_DS_ENA_ATV__B 0 +#define IQM_CF_DS_ENA_ATV__W 1 +#define IQM_CF_DS_ENA_ATV__M 0x1 +#define IQM_CF_DS_ENA_ATV__PRE 0x0 + +#define IQM_CF_DS_ENA_QAM__B 1 +#define IQM_CF_DS_ENA_QAM__W 1 +#define IQM_CF_DS_ENA_QAM__M 0x2 +#define IQM_CF_DS_ENA_QAM__PRE 0x0 + +#define IQM_CF_DS_ENA_VSB__B 2 +#define IQM_CF_DS_ENA_VSB__W 1 +#define IQM_CF_DS_ENA_VSB__M 0x4 +#define IQM_CF_DS_ENA_VSB__PRE 0x4 + + +#define IQM_CF_POW_UPD__A 0x186001A +#define IQM_CF_POW_UPD__W 1 +#define IQM_CF_POW_UPD__M 0x1 +#define IQM_CF_POW_UPD__PRE 0x0 +#define IQM_CF_TAP_RE0__A 0x1860020 +#define IQM_CF_TAP_RE0__W 7 +#define IQM_CF_TAP_RE0__M 0x7F +#define IQM_CF_TAP_RE0__PRE 0x2 +#define IQM_CF_TAP_RE0_B__B 0 +#define IQM_CF_TAP_RE0_B__W 7 +#define IQM_CF_TAP_RE0_B__M 0x7F +#define IQM_CF_TAP_RE0_B__PRE 0x2 + +#define IQM_CF_TAP_RE1__A 0x1860021 +#define IQM_CF_TAP_RE1__W 7 +#define IQM_CF_TAP_RE1__M 0x7F +#define IQM_CF_TAP_RE1__PRE 0x2 +#define IQM_CF_TAP_RE1_B__B 0 +#define IQM_CF_TAP_RE1_B__W 7 +#define IQM_CF_TAP_RE1_B__M 0x7F +#define IQM_CF_TAP_RE1_B__PRE 0x2 + +#define IQM_CF_TAP_RE2__A 0x1860022 +#define IQM_CF_TAP_RE2__W 7 +#define IQM_CF_TAP_RE2__M 0x7F +#define IQM_CF_TAP_RE2__PRE 0x2 +#define IQM_CF_TAP_RE2_B__B 0 +#define IQM_CF_TAP_RE2_B__W 7 +#define IQM_CF_TAP_RE2_B__M 0x7F +#define IQM_CF_TAP_RE2_B__PRE 0x2 + +#define IQM_CF_TAP_RE3__A 0x1860023 +#define IQM_CF_TAP_RE3__W 7 +#define IQM_CF_TAP_RE3__M 0x7F +#define IQM_CF_TAP_RE3__PRE 0x2 +#define IQM_CF_TAP_RE3_B__B 0 +#define IQM_CF_TAP_RE3_B__W 7 +#define IQM_CF_TAP_RE3_B__M 0x7F +#define IQM_CF_TAP_RE3_B__PRE 0x2 + +#define IQM_CF_TAP_RE4__A 0x1860024 +#define IQM_CF_TAP_RE4__W 7 +#define IQM_CF_TAP_RE4__M 0x7F +#define IQM_CF_TAP_RE4__PRE 0x2 +#define IQM_CF_TAP_RE4_B__B 0 +#define IQM_CF_TAP_RE4_B__W 7 +#define IQM_CF_TAP_RE4_B__M 0x7F +#define IQM_CF_TAP_RE4_B__PRE 0x2 + +#define IQM_CF_TAP_RE5__A 0x1860025 +#define IQM_CF_TAP_RE5__W 7 +#define IQM_CF_TAP_RE5__M 0x7F +#define IQM_CF_TAP_RE5__PRE 0x2 +#define IQM_CF_TAP_RE5_B__B 0 +#define IQM_CF_TAP_RE5_B__W 7 +#define IQM_CF_TAP_RE5_B__M 0x7F +#define IQM_CF_TAP_RE5_B__PRE 0x2 + +#define IQM_CF_TAP_RE6__A 0x1860026 +#define IQM_CF_TAP_RE6__W 7 +#define IQM_CF_TAP_RE6__M 0x7F +#define IQM_CF_TAP_RE6__PRE 0x2 +#define IQM_CF_TAP_RE6_B__B 0 +#define IQM_CF_TAP_RE6_B__W 7 +#define IQM_CF_TAP_RE6_B__M 0x7F +#define IQM_CF_TAP_RE6_B__PRE 0x2 + +#define IQM_CF_TAP_RE7__A 0x1860027 +#define IQM_CF_TAP_RE7__W 9 +#define IQM_CF_TAP_RE7__M 0x1FF +#define IQM_CF_TAP_RE7__PRE 0x2 +#define IQM_CF_TAP_RE7_B__B 0 +#define IQM_CF_TAP_RE7_B__W 9 +#define IQM_CF_TAP_RE7_B__M 0x1FF +#define IQM_CF_TAP_RE7_B__PRE 0x2 + +#define IQM_CF_TAP_RE8__A 0x1860028 +#define IQM_CF_TAP_RE8__W 9 +#define IQM_CF_TAP_RE8__M 0x1FF +#define IQM_CF_TAP_RE8__PRE 0x2 +#define IQM_CF_TAP_RE8_B__B 0 +#define IQM_CF_TAP_RE8_B__W 9 +#define IQM_CF_TAP_RE8_B__M 0x1FF +#define IQM_CF_TAP_RE8_B__PRE 0x2 + +#define IQM_CF_TAP_RE9__A 0x1860029 +#define IQM_CF_TAP_RE9__W 9 +#define IQM_CF_TAP_RE9__M 0x1FF +#define IQM_CF_TAP_RE9__PRE 0x2 +#define IQM_CF_TAP_RE9_B__B 0 +#define IQM_CF_TAP_RE9_B__W 9 +#define IQM_CF_TAP_RE9_B__M 0x1FF +#define IQM_CF_TAP_RE9_B__PRE 0x2 + +#define IQM_CF_TAP_RE10__A 0x186002A +#define IQM_CF_TAP_RE10__W 9 +#define IQM_CF_TAP_RE10__M 0x1FF +#define IQM_CF_TAP_RE10__PRE 0x2 +#define IQM_CF_TAP_RE10_B__B 0 +#define IQM_CF_TAP_RE10_B__W 9 +#define IQM_CF_TAP_RE10_B__M 0x1FF +#define IQM_CF_TAP_RE10_B__PRE 0x2 + +#define IQM_CF_TAP_RE11__A 0x186002B +#define IQM_CF_TAP_RE11__W 9 +#define IQM_CF_TAP_RE11__M 0x1FF +#define IQM_CF_TAP_RE11__PRE 0x2 +#define IQM_CF_TAP_RE11_B__B 0 +#define IQM_CF_TAP_RE11_B__W 9 +#define IQM_CF_TAP_RE11_B__M 0x1FF +#define IQM_CF_TAP_RE11_B__PRE 0x2 + +#define IQM_CF_TAP_RE12__A 0x186002C +#define IQM_CF_TAP_RE12__W 9 +#define IQM_CF_TAP_RE12__M 0x1FF +#define IQM_CF_TAP_RE12__PRE 0x2 +#define IQM_CF_TAP_RE12_B__B 0 +#define IQM_CF_TAP_RE12_B__W 9 +#define IQM_CF_TAP_RE12_B__M 0x1FF +#define IQM_CF_TAP_RE12_B__PRE 0x2 + +#define IQM_CF_TAP_RE13__A 0x186002D +#define IQM_CF_TAP_RE13__W 9 +#define IQM_CF_TAP_RE13__M 0x1FF +#define IQM_CF_TAP_RE13__PRE 0x2 +#define IQM_CF_TAP_RE13_B__B 0 +#define IQM_CF_TAP_RE13_B__W 9 +#define IQM_CF_TAP_RE13_B__M 0x1FF +#define IQM_CF_TAP_RE13_B__PRE 0x2 + +#define IQM_CF_TAP_RE14__A 0x186002E +#define IQM_CF_TAP_RE14__W 9 +#define IQM_CF_TAP_RE14__M 0x1FF +#define IQM_CF_TAP_RE14__PRE 0x2 +#define IQM_CF_TAP_RE14_B__B 0 +#define IQM_CF_TAP_RE14_B__W 9 +#define IQM_CF_TAP_RE14_B__M 0x1FF +#define IQM_CF_TAP_RE14_B__PRE 0x2 + +#define IQM_CF_TAP_RE15__A 0x186002F +#define IQM_CF_TAP_RE15__W 9 +#define IQM_CF_TAP_RE15__M 0x1FF +#define IQM_CF_TAP_RE15__PRE 0x2 +#define IQM_CF_TAP_RE15_B__B 0 +#define IQM_CF_TAP_RE15_B__W 9 +#define IQM_CF_TAP_RE15_B__M 0x1FF +#define IQM_CF_TAP_RE15_B__PRE 0x2 + +#define IQM_CF_TAP_RE16__A 0x1860030 +#define IQM_CF_TAP_RE16__W 9 +#define IQM_CF_TAP_RE16__M 0x1FF +#define IQM_CF_TAP_RE16__PRE 0x2 +#define IQM_CF_TAP_RE16_B__B 0 +#define IQM_CF_TAP_RE16_B__W 9 +#define IQM_CF_TAP_RE16_B__M 0x1FF +#define IQM_CF_TAP_RE16_B__PRE 0x2 + +#define IQM_CF_TAP_RE17__A 0x1860031 +#define IQM_CF_TAP_RE17__W 9 +#define IQM_CF_TAP_RE17__M 0x1FF +#define IQM_CF_TAP_RE17__PRE 0x2 +#define IQM_CF_TAP_RE17_B__B 0 +#define IQM_CF_TAP_RE17_B__W 9 +#define IQM_CF_TAP_RE17_B__M 0x1FF +#define IQM_CF_TAP_RE17_B__PRE 0x2 + +#define IQM_CF_TAP_RE18__A 0x1860032 +#define IQM_CF_TAP_RE18__W 9 +#define IQM_CF_TAP_RE18__M 0x1FF +#define IQM_CF_TAP_RE18__PRE 0x2 +#define IQM_CF_TAP_RE18_B__B 0 +#define IQM_CF_TAP_RE18_B__W 9 +#define IQM_CF_TAP_RE18_B__M 0x1FF +#define IQM_CF_TAP_RE18_B__PRE 0x2 + +#define IQM_CF_TAP_RE19__A 0x1860033 +#define IQM_CF_TAP_RE19__W 9 +#define IQM_CF_TAP_RE19__M 0x1FF +#define IQM_CF_TAP_RE19__PRE 0x2 +#define IQM_CF_TAP_RE19_B__B 0 +#define IQM_CF_TAP_RE19_B__W 9 +#define IQM_CF_TAP_RE19_B__M 0x1FF +#define IQM_CF_TAP_RE19_B__PRE 0x2 + +#define IQM_CF_TAP_RE20__A 0x1860034 +#define IQM_CF_TAP_RE20__W 9 +#define IQM_CF_TAP_RE20__M 0x1FF +#define IQM_CF_TAP_RE20__PRE 0x2 +#define IQM_CF_TAP_RE20_B__B 0 +#define IQM_CF_TAP_RE20_B__W 9 +#define IQM_CF_TAP_RE20_B__M 0x1FF +#define IQM_CF_TAP_RE20_B__PRE 0x2 + +#define IQM_CF_TAP_RE21__A 0x1860035 +#define IQM_CF_TAP_RE21__W 11 +#define IQM_CF_TAP_RE21__M 0x7FF +#define IQM_CF_TAP_RE21__PRE 0x2 +#define IQM_CF_TAP_RE21_B__B 0 +#define IQM_CF_TAP_RE21_B__W 11 +#define IQM_CF_TAP_RE21_B__M 0x7FF +#define IQM_CF_TAP_RE21_B__PRE 0x2 + +#define IQM_CF_TAP_RE22__A 0x1860036 +#define IQM_CF_TAP_RE22__W 11 +#define IQM_CF_TAP_RE22__M 0x7FF +#define IQM_CF_TAP_RE22__PRE 0x2 +#define IQM_CF_TAP_RE22_B__B 0 +#define IQM_CF_TAP_RE22_B__W 11 +#define IQM_CF_TAP_RE22_B__M 0x7FF +#define IQM_CF_TAP_RE22_B__PRE 0x2 + +#define IQM_CF_TAP_RE23__A 0x1860037 +#define IQM_CF_TAP_RE23__W 11 +#define IQM_CF_TAP_RE23__M 0x7FF +#define IQM_CF_TAP_RE23__PRE 0x2 +#define IQM_CF_TAP_RE23_B__B 0 +#define IQM_CF_TAP_RE23_B__W 11 +#define IQM_CF_TAP_RE23_B__M 0x7FF +#define IQM_CF_TAP_RE23_B__PRE 0x2 + +#define IQM_CF_TAP_RE24__A 0x1860038 +#define IQM_CF_TAP_RE24__W 11 +#define IQM_CF_TAP_RE24__M 0x7FF +#define IQM_CF_TAP_RE24__PRE 0x2 +#define IQM_CF_TAP_RE24_B__B 0 +#define IQM_CF_TAP_RE24_B__W 11 +#define IQM_CF_TAP_RE24_B__M 0x7FF +#define IQM_CF_TAP_RE24_B__PRE 0x2 + +#define IQM_CF_TAP_RE25__A 0x1860039 +#define IQM_CF_TAP_RE25__W 11 +#define IQM_CF_TAP_RE25__M 0x7FF +#define IQM_CF_TAP_RE25__PRE 0x2 +#define IQM_CF_TAP_RE25_B__B 0 +#define IQM_CF_TAP_RE25_B__W 11 +#define IQM_CF_TAP_RE25_B__M 0x7FF +#define IQM_CF_TAP_RE25_B__PRE 0x2 + +#define IQM_CF_TAP_RE26__A 0x186003A +#define IQM_CF_TAP_RE26__W 11 +#define IQM_CF_TAP_RE26__M 0x7FF +#define IQM_CF_TAP_RE26__PRE 0x2 +#define IQM_CF_TAP_RE26_B__B 0 +#define IQM_CF_TAP_RE26_B__W 11 +#define IQM_CF_TAP_RE26_B__M 0x7FF +#define IQM_CF_TAP_RE26_B__PRE 0x2 + +#define IQM_CF_TAP_RE27__A 0x186003B +#define IQM_CF_TAP_RE27__W 11 +#define IQM_CF_TAP_RE27__M 0x7FF +#define IQM_CF_TAP_RE27__PRE 0x2 +#define IQM_CF_TAP_RE27_B__B 0 +#define IQM_CF_TAP_RE27_B__W 11 +#define IQM_CF_TAP_RE27_B__M 0x7FF +#define IQM_CF_TAP_RE27_B__PRE 0x2 + +#define IQM_CF_TAP_IM0__A 0x1860040 +#define IQM_CF_TAP_IM0__W 7 +#define IQM_CF_TAP_IM0__M 0x7F +#define IQM_CF_TAP_IM0__PRE 0x2 +#define IQM_CF_TAP_IM0_B__B 0 +#define IQM_CF_TAP_IM0_B__W 7 +#define IQM_CF_TAP_IM0_B__M 0x7F +#define IQM_CF_TAP_IM0_B__PRE 0x2 + +#define IQM_CF_TAP_IM1__A 0x1860041 +#define IQM_CF_TAP_IM1__W 7 +#define IQM_CF_TAP_IM1__M 0x7F +#define IQM_CF_TAP_IM1__PRE 0x2 +#define IQM_CF_TAP_IM1_B__B 0 +#define IQM_CF_TAP_IM1_B__W 7 +#define IQM_CF_TAP_IM1_B__M 0x7F +#define IQM_CF_TAP_IM1_B__PRE 0x2 + +#define IQM_CF_TAP_IM2__A 0x1860042 +#define IQM_CF_TAP_IM2__W 7 +#define IQM_CF_TAP_IM2__M 0x7F +#define IQM_CF_TAP_IM2__PRE 0x2 +#define IQM_CF_TAP_IM2_B__B 0 +#define IQM_CF_TAP_IM2_B__W 7 +#define IQM_CF_TAP_IM2_B__M 0x7F +#define IQM_CF_TAP_IM2_B__PRE 0x2 + +#define IQM_CF_TAP_IM3__A 0x1860043 +#define IQM_CF_TAP_IM3__W 7 +#define IQM_CF_TAP_IM3__M 0x7F +#define IQM_CF_TAP_IM3__PRE 0x2 +#define IQM_CF_TAP_IM3_B__B 0 +#define IQM_CF_TAP_IM3_B__W 7 +#define IQM_CF_TAP_IM3_B__M 0x7F +#define IQM_CF_TAP_IM3_B__PRE 0x2 + +#define IQM_CF_TAP_IM4__A 0x1860044 +#define IQM_CF_TAP_IM4__W 7 +#define IQM_CF_TAP_IM4__M 0x7F +#define IQM_CF_TAP_IM4__PRE 0x2 +#define IQM_CF_TAP_IM4_B__B 0 +#define IQM_CF_TAP_IM4_B__W 7 +#define IQM_CF_TAP_IM4_B__M 0x7F +#define IQM_CF_TAP_IM4_B__PRE 0x2 + +#define IQM_CF_TAP_IM5__A 0x1860045 +#define IQM_CF_TAP_IM5__W 7 +#define IQM_CF_TAP_IM5__M 0x7F +#define IQM_CF_TAP_IM5__PRE 0x2 +#define IQM_CF_TAP_IM5_B__B 0 +#define IQM_CF_TAP_IM5_B__W 7 +#define IQM_CF_TAP_IM5_B__M 0x7F +#define IQM_CF_TAP_IM5_B__PRE 0x2 + +#define IQM_CF_TAP_IM6__A 0x1860046 +#define IQM_CF_TAP_IM6__W 7 +#define IQM_CF_TAP_IM6__M 0x7F +#define IQM_CF_TAP_IM6__PRE 0x2 +#define IQM_CF_TAP_IM6_B__B 0 +#define IQM_CF_TAP_IM6_B__W 7 +#define IQM_CF_TAP_IM6_B__M 0x7F +#define IQM_CF_TAP_IM6_B__PRE 0x2 + +#define IQM_CF_TAP_IM7__A 0x1860047 +#define IQM_CF_TAP_IM7__W 9 +#define IQM_CF_TAP_IM7__M 0x1FF +#define IQM_CF_TAP_IM7__PRE 0x2 +#define IQM_CF_TAP_IM7_B__B 0 +#define IQM_CF_TAP_IM7_B__W 9 +#define IQM_CF_TAP_IM7_B__M 0x1FF +#define IQM_CF_TAP_IM7_B__PRE 0x2 + +#define IQM_CF_TAP_IM8__A 0x1860048 +#define IQM_CF_TAP_IM8__W 9 +#define IQM_CF_TAP_IM8__M 0x1FF +#define IQM_CF_TAP_IM8__PRE 0x2 +#define IQM_CF_TAP_IM8_B__B 0 +#define IQM_CF_TAP_IM8_B__W 9 +#define IQM_CF_TAP_IM8_B__M 0x1FF +#define IQM_CF_TAP_IM8_B__PRE 0x2 + +#define IQM_CF_TAP_IM9__A 0x1860049 +#define IQM_CF_TAP_IM9__W 9 +#define IQM_CF_TAP_IM9__M 0x1FF +#define IQM_CF_TAP_IM9__PRE 0x2 +#define IQM_CF_TAP_IM9_B__B 0 +#define IQM_CF_TAP_IM9_B__W 9 +#define IQM_CF_TAP_IM9_B__M 0x1FF +#define IQM_CF_TAP_IM9_B__PRE 0x2 + +#define IQM_CF_TAP_IM10__A 0x186004A +#define IQM_CF_TAP_IM10__W 9 +#define IQM_CF_TAP_IM10__M 0x1FF +#define IQM_CF_TAP_IM10__PRE 0x2 +#define IQM_CF_TAP_IM10_B__B 0 +#define IQM_CF_TAP_IM10_B__W 9 +#define IQM_CF_TAP_IM10_B__M 0x1FF +#define IQM_CF_TAP_IM10_B__PRE 0x2 + +#define IQM_CF_TAP_IM11__A 0x186004B +#define IQM_CF_TAP_IM11__W 9 +#define IQM_CF_TAP_IM11__M 0x1FF +#define IQM_CF_TAP_IM11__PRE 0x2 +#define IQM_CF_TAP_IM11_B__B 0 +#define IQM_CF_TAP_IM11_B__W 9 +#define IQM_CF_TAP_IM11_B__M 0x1FF +#define IQM_CF_TAP_IM11_B__PRE 0x2 + +#define IQM_CF_TAP_IM12__A 0x186004C +#define IQM_CF_TAP_IM12__W 9 +#define IQM_CF_TAP_IM12__M 0x1FF +#define IQM_CF_TAP_IM12__PRE 0x2 +#define IQM_CF_TAP_IM12_B__B 0 +#define IQM_CF_TAP_IM12_B__W 9 +#define IQM_CF_TAP_IM12_B__M 0x1FF +#define IQM_CF_TAP_IM12_B__PRE 0x2 + +#define IQM_CF_TAP_IM13__A 0x186004D +#define IQM_CF_TAP_IM13__W 9 +#define IQM_CF_TAP_IM13__M 0x1FF +#define IQM_CF_TAP_IM13__PRE 0x2 +#define IQM_CF_TAP_IM13_B__B 0 +#define IQM_CF_TAP_IM13_B__W 9 +#define IQM_CF_TAP_IM13_B__M 0x1FF +#define IQM_CF_TAP_IM13_B__PRE 0x2 + +#define IQM_CF_TAP_IM14__A 0x186004E +#define IQM_CF_TAP_IM14__W 9 +#define IQM_CF_TAP_IM14__M 0x1FF +#define IQM_CF_TAP_IM14__PRE 0x2 +#define IQM_CF_TAP_IM14_B__B 0 +#define IQM_CF_TAP_IM14_B__W 9 +#define IQM_CF_TAP_IM14_B__M 0x1FF +#define IQM_CF_TAP_IM14_B__PRE 0x2 + +#define IQM_CF_TAP_IM15__A 0x186004F +#define IQM_CF_TAP_IM15__W 9 +#define IQM_CF_TAP_IM15__M 0x1FF +#define IQM_CF_TAP_IM15__PRE 0x2 +#define IQM_CF_TAP_IM15_B__B 0 +#define IQM_CF_TAP_IM15_B__W 9 +#define IQM_CF_TAP_IM15_B__M 0x1FF +#define IQM_CF_TAP_IM15_B__PRE 0x2 + +#define IQM_CF_TAP_IM16__A 0x1860050 +#define IQM_CF_TAP_IM16__W 9 +#define IQM_CF_TAP_IM16__M 0x1FF +#define IQM_CF_TAP_IM16__PRE 0x2 +#define IQM_CF_TAP_IM16_B__B 0 +#define IQM_CF_TAP_IM16_B__W 9 +#define IQM_CF_TAP_IM16_B__M 0x1FF +#define IQM_CF_TAP_IM16_B__PRE 0x2 + +#define IQM_CF_TAP_IM17__A 0x1860051 +#define IQM_CF_TAP_IM17__W 9 +#define IQM_CF_TAP_IM17__M 0x1FF +#define IQM_CF_TAP_IM17__PRE 0x2 +#define IQM_CF_TAP_IM17_B__B 0 +#define IQM_CF_TAP_IM17_B__W 9 +#define IQM_CF_TAP_IM17_B__M 0x1FF +#define IQM_CF_TAP_IM17_B__PRE 0x2 + +#define IQM_CF_TAP_IM18__A 0x1860052 +#define IQM_CF_TAP_IM18__W 9 +#define IQM_CF_TAP_IM18__M 0x1FF +#define IQM_CF_TAP_IM18__PRE 0x2 +#define IQM_CF_TAP_IM18_B__B 0 +#define IQM_CF_TAP_IM18_B__W 9 +#define IQM_CF_TAP_IM18_B__M 0x1FF +#define IQM_CF_TAP_IM18_B__PRE 0x2 + +#define IQM_CF_TAP_IM19__A 0x1860053 +#define IQM_CF_TAP_IM19__W 9 +#define IQM_CF_TAP_IM19__M 0x1FF +#define IQM_CF_TAP_IM19__PRE 0x2 +#define IQM_CF_TAP_IM19_B__B 0 +#define IQM_CF_TAP_IM19_B__W 9 +#define IQM_CF_TAP_IM19_B__M 0x1FF +#define IQM_CF_TAP_IM19_B__PRE 0x2 + +#define IQM_CF_TAP_IM20__A 0x1860054 +#define IQM_CF_TAP_IM20__W 9 +#define IQM_CF_TAP_IM20__M 0x1FF +#define IQM_CF_TAP_IM20__PRE 0x2 +#define IQM_CF_TAP_IM20_B__B 0 +#define IQM_CF_TAP_IM20_B__W 9 +#define IQM_CF_TAP_IM20_B__M 0x1FF +#define IQM_CF_TAP_IM20_B__PRE 0x2 + +#define IQM_CF_TAP_IM21__A 0x1860055 +#define IQM_CF_TAP_IM21__W 11 +#define IQM_CF_TAP_IM21__M 0x7FF +#define IQM_CF_TAP_IM21__PRE 0x2 +#define IQM_CF_TAP_IM21_B__B 0 +#define IQM_CF_TAP_IM21_B__W 11 +#define IQM_CF_TAP_IM21_B__M 0x7FF +#define IQM_CF_TAP_IM21_B__PRE 0x2 + +#define IQM_CF_TAP_IM22__A 0x1860056 +#define IQM_CF_TAP_IM22__W 11 +#define IQM_CF_TAP_IM22__M 0x7FF +#define IQM_CF_TAP_IM22__PRE 0x2 +#define IQM_CF_TAP_IM22_B__B 0 +#define IQM_CF_TAP_IM22_B__W 11 +#define IQM_CF_TAP_IM22_B__M 0x7FF +#define IQM_CF_TAP_IM22_B__PRE 0x2 + +#define IQM_CF_TAP_IM23__A 0x1860057 +#define IQM_CF_TAP_IM23__W 11 +#define IQM_CF_TAP_IM23__M 0x7FF +#define IQM_CF_TAP_IM23__PRE 0x2 +#define IQM_CF_TAP_IM23_B__B 0 +#define IQM_CF_TAP_IM23_B__W 11 +#define IQM_CF_TAP_IM23_B__M 0x7FF +#define IQM_CF_TAP_IM23_B__PRE 0x2 + +#define IQM_CF_TAP_IM24__A 0x1860058 +#define IQM_CF_TAP_IM24__W 11 +#define IQM_CF_TAP_IM24__M 0x7FF +#define IQM_CF_TAP_IM24__PRE 0x2 +#define IQM_CF_TAP_IM24_B__B 0 +#define IQM_CF_TAP_IM24_B__W 11 +#define IQM_CF_TAP_IM24_B__M 0x7FF +#define IQM_CF_TAP_IM24_B__PRE 0x2 + +#define IQM_CF_TAP_IM25__A 0x1860059 +#define IQM_CF_TAP_IM25__W 11 +#define IQM_CF_TAP_IM25__M 0x7FF +#define IQM_CF_TAP_IM25__PRE 0x2 +#define IQM_CF_TAP_IM25_B__B 0 +#define IQM_CF_TAP_IM25_B__W 11 +#define IQM_CF_TAP_IM25_B__M 0x7FF +#define IQM_CF_TAP_IM25_B__PRE 0x2 + +#define IQM_CF_TAP_IM26__A 0x186005A +#define IQM_CF_TAP_IM26__W 11 +#define IQM_CF_TAP_IM26__M 0x7FF +#define IQM_CF_TAP_IM26__PRE 0x2 +#define IQM_CF_TAP_IM26_B__B 0 +#define IQM_CF_TAP_IM26_B__W 11 +#define IQM_CF_TAP_IM26_B__M 0x7FF +#define IQM_CF_TAP_IM26_B__PRE 0x2 + +#define IQM_CF_TAP_IM27__A 0x186005B +#define IQM_CF_TAP_IM27__W 11 +#define IQM_CF_TAP_IM27__M 0x7FF +#define IQM_CF_TAP_IM27__PRE 0x2 +#define IQM_CF_TAP_IM27_B__B 0 +#define IQM_CF_TAP_IM27_B__W 11 +#define IQM_CF_TAP_IM27_B__M 0x7FF +#define IQM_CF_TAP_IM27_B__PRE 0x2 + + +#define IQM_CF_CLP_VAL__A 0x1860060 +#define IQM_CF_CLP_VAL__W 9 +#define IQM_CF_CLP_VAL__M 0x1FF +#define IQM_CF_CLP_VAL__PRE 0x3C + +#define IQM_CF_DATATH__A 0x1860061 +#define IQM_CF_DATATH__W 10 +#define IQM_CF_DATATH__M 0x3FF +#define IQM_CF_DATATH__PRE 0x180 + +#define IQM_CF_PKDTH__A 0x1860062 +#define IQM_CF_PKDTH__W 5 +#define IQM_CF_PKDTH__M 0x1F +#define IQM_CF_PKDTH__PRE 0x1 + +#define IQM_CF_WND_LEN__A 0x1860063 +#define IQM_CF_WND_LEN__W 4 +#define IQM_CF_WND_LEN__M 0xF +#define IQM_CF_WND_LEN__PRE 0x1 + +#define IQM_CF_DET_LCT__A 0x1860064 +#define IQM_CF_DET_LCT__W 1 +#define IQM_CF_DET_LCT__M 0x1 +#define IQM_CF_DET_LCT__PRE 0x1 + +#define IQM_CF_SNS_LEN__A 0x1860065 +#define IQM_CF_SNS_LEN__W 16 +#define IQM_CF_SNS_LEN__M 0xFFFF +#define IQM_CF_SNS_LEN__PRE 0x0 + +#define IQM_CF_SNS_SENSE__A 0x1860066 +#define IQM_CF_SNS_SENSE__W 16 +#define IQM_CF_SNS_SENSE__M 0xFFFF +#define IQM_CF_SNS_SENSE__PRE 0x0 + +#define IQM_CF_BYPASSDET__A 0x1860067 +#define IQM_CF_BYPASSDET__W 1 +#define IQM_CF_BYPASSDET__M 0x1 +#define IQM_CF_BYPASSDET__PRE 0x0 + +#define IQM_CF_UPD_ENA__A 0x1860068 +#define IQM_CF_UPD_ENA__W 1 +#define IQM_CF_UPD_ENA__M 0x1 +#define IQM_CF_UPD_ENA__PRE 0x0 +#define IQM_CF_UPD_ENA_DISABLE 0x0 +#define IQM_CF_UPD_ENA_ENABLE 0x1 + + + +#define IQM_AF_COMM_EXEC__A 0x1870000 +#define IQM_AF_COMM_EXEC__W 2 +#define IQM_AF_COMM_EXEC__M 0x3 +#define IQM_AF_COMM_EXEC__PRE 0x0 +#define IQM_AF_COMM_EXEC_STOP 0x0 +#define IQM_AF_COMM_EXEC_ACTIVE 0x1 +#define IQM_AF_COMM_EXEC_HOLD 0x2 + +#define IQM_AF_COMM_MB__A 0x1870002 +#define IQM_AF_COMM_MB__W 8 +#define IQM_AF_COMM_MB__M 0xFF +#define IQM_AF_COMM_MB__PRE 0x0 +#define IQM_AF_COMM_MB_CTL__B 0 +#define IQM_AF_COMM_MB_CTL__W 1 +#define IQM_AF_COMM_MB_CTL__M 0x1 +#define IQM_AF_COMM_MB_CTL__PRE 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0 +#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1 +#define IQM_AF_COMM_MB_OBS__B 1 +#define IQM_AF_COMM_MB_OBS__W 1 +#define IQM_AF_COMM_MB_OBS__M 0x2 +#define IQM_AF_COMM_MB_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0 +#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2 +#define IQM_AF_COMM_MB_MUX_CTRL__B 2 +#define IQM_AF_COMM_MB_MUX_CTRL__W 3 +#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C +#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4 +#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8 +#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC +#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10 +#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14 +#define IQM_AF_COMM_MB_MUX_OBS__B 5 +#define IQM_AF_COMM_MB_MUX_OBS__W 3 +#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0 +#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0 +#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20 +#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40 +#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60 +#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80 +#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0 + +#define IQM_AF_COMM_INT_REQ__A 0x1870003 +#define IQM_AF_COMM_INT_REQ__W 1 +#define IQM_AF_COMM_INT_REQ__M 0x1 +#define IQM_AF_COMM_INT_REQ__PRE 0x0 +#define IQM_AF_COMM_INT_STA__A 0x1870005 +#define IQM_AF_COMM_INT_STA__W 3 +#define IQM_AF_COMM_INT_STA__M 0x7 +#define IQM_AF_COMM_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0 + +#define IQM_AF_COMM_INT_MSK__A 0x1870006 +#define IQM_AF_COMM_INT_MSK__W 3 +#define IQM_AF_COMM_INT_MSK__M 0x7 +#define IQM_AF_COMM_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1 +#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2 +#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4 +#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0 + +#define IQM_AF_COMM_INT_STM__A 0x1870007 +#define IQM_AF_COMM_INT_STM__W 3 +#define IQM_AF_COMM_INT_STM__M 0x7 +#define IQM_AF_COMM_INT_STM__PRE 0x0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1 +#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2 +#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4 +#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0 + + +#define IQM_AF_FDB_SEL__A 0x1870010 +#define IQM_AF_FDB_SEL__W 2 +#define IQM_AF_FDB_SEL__M 0x3 +#define IQM_AF_FDB_SEL__PRE 0x0 +#define IQM_AF_CLKNEG__A 0x1870012 +#define IQM_AF_CLKNEG__W 2 +#define IQM_AF_CLKNEG__M 0x3 +#define IQM_AF_CLKNEG__PRE 0x0 + +#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 +#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1 +#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1 + +#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__W 1 +#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 +#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 +#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 + + +#define IQM_AF_MON_IN_MUX__A 0x1870013 +#define IQM_AF_MON_IN_MUX__W 2 +#define IQM_AF_MON_IN_MUX__M 0x3 +#define IQM_AF_MON_IN_MUX__PRE 0x0 + +#define IQM_AF_MON_IN5__A 0x1870014 +#define IQM_AF_MON_IN5__W 10 +#define IQM_AF_MON_IN5__M 0x3FF +#define IQM_AF_MON_IN5__PRE 0x0 + +#define IQM_AF_MON_IN4__A 0x1870015 +#define IQM_AF_MON_IN4__W 10 +#define IQM_AF_MON_IN4__M 0x3FF +#define IQM_AF_MON_IN4__PRE 0x0 + +#define IQM_AF_MON_IN3__A 0x1870016 +#define IQM_AF_MON_IN3__W 10 +#define IQM_AF_MON_IN3__M 0x3FF +#define IQM_AF_MON_IN3__PRE 0x0 + +#define IQM_AF_MON_IN2__A 0x1870017 +#define IQM_AF_MON_IN2__W 10 +#define IQM_AF_MON_IN2__M 0x3FF +#define IQM_AF_MON_IN2__PRE 0x0 + +#define IQM_AF_MON_IN1__A 0x1870018 +#define IQM_AF_MON_IN1__W 10 +#define IQM_AF_MON_IN1__M 0x3FF +#define IQM_AF_MON_IN1__PRE 0x0 + +#define IQM_AF_MON_IN0__A 0x1870019 +#define IQM_AF_MON_IN0__W 10 +#define IQM_AF_MON_IN0__M 0x3FF +#define IQM_AF_MON_IN0__PRE 0x0 + +#define IQM_AF_MON_IN_VAL__A 0x187001A +#define IQM_AF_MON_IN_VAL__W 1 +#define IQM_AF_MON_IN_VAL__M 0x1 +#define IQM_AF_MON_IN_VAL__PRE 0x0 + +#define IQM_AF_START_LOCK__A 0x187001B +#define IQM_AF_START_LOCK__W 1 +#define IQM_AF_START_LOCK__M 0x1 +#define IQM_AF_START_LOCK__PRE 0x0 + +#define IQM_AF_PHASE0__A 0x187001C +#define IQM_AF_PHASE0__W 7 +#define IQM_AF_PHASE0__M 0x7F +#define IQM_AF_PHASE0__PRE 0x0 + +#define IQM_AF_PHASE1__A 0x187001D +#define IQM_AF_PHASE1__W 7 +#define IQM_AF_PHASE1__M 0x7F +#define IQM_AF_PHASE1__PRE 0x0 + +#define IQM_AF_PHASE2__A 0x187001E +#define IQM_AF_PHASE2__W 7 +#define IQM_AF_PHASE2__M 0x7F +#define IQM_AF_PHASE2__PRE 0x0 + +#define IQM_AF_SCU_PHASE__A 0x187001F +#define IQM_AF_SCU_PHASE__W 2 +#define IQM_AF_SCU_PHASE__M 0x3 +#define IQM_AF_SCU_PHASE__PRE 0x0 + +#define IQM_AF_SYNC_SEL__A 0x1870020 +#define IQM_AF_SYNC_SEL__W 2 +#define IQM_AF_SYNC_SEL__M 0x3 +#define IQM_AF_SYNC_SEL__PRE 0x0 +#define IQM_AF_ADC_CONF__A 0x1870021 +#define IQM_AF_ADC_CONF__W 4 +#define IQM_AF_ADC_CONF__M 0xF +#define IQM_AF_ADC_CONF__PRE 0x0 + +#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 +#define IQM_AF_ADC_CONF_ADC_SIGN__W 1 +#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1 +#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0 +#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1 + +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4 + +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0 +#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8 + + +#define IQM_AF_CLP_CLIP__A 0x1870022 +#define IQM_AF_CLP_CLIP__W 16 +#define IQM_AF_CLP_CLIP__M 0xFFFF +#define IQM_AF_CLP_CLIP__PRE 0x0 + +#define IQM_AF_CLP_LEN__A 0x1870023 +#define IQM_AF_CLP_LEN__W 16 +#define IQM_AF_CLP_LEN__M 0xFFFF +#define IQM_AF_CLP_LEN__PRE 0x0 + +#define IQM_AF_CLP_TH__A 0x1870024 +#define IQM_AF_CLP_TH__W 9 +#define IQM_AF_CLP_TH__M 0x1FF +#define IQM_AF_CLP_TH__PRE 0x0 + +#define IQM_AF_DCF_BYPASS__A 0x1870025 +#define IQM_AF_DCF_BYPASS__W 1 +#define IQM_AF_DCF_BYPASS__M 0x1 +#define IQM_AF_DCF_BYPASS__PRE 0x0 +#define IQM_AF_DCF_BYPASS_ACTIVE 0x0 +#define IQM_AF_DCF_BYPASS_BYPASS 0x1 + + +#define IQM_AF_SNS_LEN__A 0x1870026 +#define IQM_AF_SNS_LEN__W 16 +#define IQM_AF_SNS_LEN__M 0xFFFF +#define IQM_AF_SNS_LEN__PRE 0x0 + +#define IQM_AF_SNS_SENSE__A 0x1870027 +#define IQM_AF_SNS_SENSE__W 16 +#define IQM_AF_SNS_SENSE__M 0xFFFF +#define IQM_AF_SNS_SENSE__PRE 0x0 + +#define IQM_AF_AGC_IF__A 0x1870028 +#define IQM_AF_AGC_IF__W 15 +#define IQM_AF_AGC_IF__M 0x7FFF +#define IQM_AF_AGC_IF__PRE 0x0 + +#define IQM_AF_AGC_RF__A 0x1870029 +#define IQM_AF_AGC_RF__W 15 +#define IQM_AF_AGC_RF__M 0x7FFF +#define IQM_AF_AGC_RF__PRE 0x0 + +#define IQM_AF_PDREF__A 0x187002B +#define IQM_AF_PDREF__W 5 +#define IQM_AF_PDREF__M 0x1F +#define IQM_AF_PDREF__PRE 0x0 +#define IQM_AF_STDBY__A 0x187002C +#define IQM_AF_STDBY__W 6 +#define IQM_AF_STDBY__M 0x3F +#define IQM_AF_STDBY__PRE 0x3E + +#define IQM_AF_STDBY_STDBY_BIAS__B 0 +#define IQM_AF_STDBY_STDBY_BIAS__W 1 +#define IQM_AF_STDBY_STDBY_BIAS__M 0x1 +#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1 + +#define IQM_AF_STDBY_STDBY_ADC__B 1 +#define IQM_AF_STDBY_STDBY_ADC__W 1 +#define IQM_AF_STDBY_STDBY_ADC__M 0x2 +#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2 +#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 + +#define IQM_AF_STDBY_STDBY_AMP__B 2 +#define IQM_AF_STDBY_STDBY_AMP__W 1 +#define IQM_AF_STDBY_STDBY_AMP__M 0x4 +#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4 +#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 + +#define IQM_AF_STDBY_STDBY_PD__B 3 +#define IQM_AF_STDBY_STDBY_PD__W 1 +#define IQM_AF_STDBY_STDBY_PD__M 0x8 +#define IQM_AF_STDBY_STDBY_PD__PRE 0x8 +#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 + +#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 +#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10 +#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 + +#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 +#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 +#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20 +#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0 +#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 + + +#define IQM_AF_AMUX__A 0x187002D +#define IQM_AF_AMUX__W 1 +#define IQM_AF_AMUX__M 0x1 +#define IQM_AF_AMUX__PRE 0x0 +#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0 +#define IQM_AF_AMUX_SIGNAL2ADC 0x1 + + +#define IQM_AF_TST_AFEMAIN__A 0x187002E +#define IQM_AF_TST_AFEMAIN__W 8 +#define IQM_AF_TST_AFEMAIN__M 0xFF +#define IQM_AF_TST_AFEMAIN__PRE 0x0 + +#define IQM_AF_UPD_SEL__A 0x187002F +#define IQM_AF_UPD_SEL__W 1 +#define IQM_AF_UPD_SEL__M 0x1 +#define IQM_AF_UPD_SEL__PRE 0x0 + +#define IQM_AF_INC_DATATH__A 0x1870030 +#define IQM_AF_INC_DATATH__W 9 +#define IQM_AF_INC_DATATH__M 0x1FF +#define IQM_AF_INC_DATATH__PRE 0x180 + +#define IQM_AF_INC_PKDTH__A 0x1870031 +#define IQM_AF_INC_PKDTH__W 5 +#define IQM_AF_INC_PKDTH__M 0x1F +#define IQM_AF_INC_PKDTH__PRE 0x3 + +#define IQM_AF_INC_WND_LEN__A 0x1870032 +#define IQM_AF_INC_WND_LEN__W 4 +#define IQM_AF_INC_WND_LEN__M 0xF +#define IQM_AF_INC_WND_LEN__PRE 0xA + +#define IQM_AF_INC_DLY__A 0x1870033 +#define IQM_AF_INC_DLY__W 7 +#define IQM_AF_INC_DLY__M 0x7F +#define IQM_AF_INC_DLY__PRE 0x14 + +#define IQM_AF_INC_LCT__A 0x1870034 +#define IQM_AF_INC_LCT__W 1 +#define IQM_AF_INC_LCT__M 0x1 +#define IQM_AF_INC_LCT__PRE 0x1 + +#define IQM_AF_INC_CLP_VAL__A 0x1870035 +#define IQM_AF_INC_CLP_VAL__W 9 +#define IQM_AF_INC_CLP_VAL__M 0x1FF +#define IQM_AF_INC_CLP_VAL__PRE 0x3C + +#define IQM_AF_INC_BYPASS__A 0x1870036 +#define IQM_AF_INC_BYPASS__W 1 +#define IQM_AF_INC_BYPASS__M 0x1 +#define IQM_AF_INC_BYPASS__PRE 0x1 + +#define IQM_AF_INC_MODE_SEL__A 0x1870037 +#define IQM_AF_INC_MODE_SEL__W 2 +#define IQM_AF_INC_MODE_SEL__M 0x3 +#define IQM_AF_INC_MODE_SEL__PRE 0x1 + +#define IQM_AF_INC_A_DLY__A 0x1870038 +#define IQM_AF_INC_A_DLY__W 6 +#define IQM_AF_INC_A_DLY__M 0x3F +#define IQM_AF_INC_A_DLY__PRE 0xF + +#define IQM_AF_ISNS_LEN__A 0x1870039 +#define IQM_AF_ISNS_LEN__W 16 +#define IQM_AF_ISNS_LEN__M 0xFFFF +#define IQM_AF_ISNS_LEN__PRE 0x0 + +#define IQM_AF_ISNS_SENSE__A 0x187003A +#define IQM_AF_ISNS_SENSE__W 16 +#define IQM_AF_ISNS_SENSE__M 0xFFFF +#define IQM_AF_ISNS_SENSE__PRE 0x0 +#define IQM_AF_CMP_STATE__A 0x187003B +#define IQM_AF_CMP_STATE__W 7 +#define IQM_AF_CMP_STATE__M 0x7F +#define IQM_AF_CMP_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_STATE__B 0 +#define IQM_AF_CMP_STATE_STATE__W 2 +#define IQM_AF_CMP_STATE_STATE__M 0x3 +#define IQM_AF_CMP_STATE_STATE__PRE 0x0 + +#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2 +#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1 +#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4 +#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0 + +#define IQM_AF_CMP_STATE_FILTERGAIN__B 3 +#define IQM_AF_CMP_STATE_FILTERGAIN__W 2 +#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18 +#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10 +#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18 + +#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5 +#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1 +#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20 +#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0 + +#define IQM_AF_CMP_STATE_SEG64__B 6 +#define IQM_AF_CMP_STATE_SEG64__W 1 +#define IQM_AF_CMP_STATE_SEG64__M 0x40 +#define IQM_AF_CMP_STATE_SEG64__PRE 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0 +#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40 + + +#define IQM_AF_CMP_DC_OUT__A 0x187003C +#define IQM_AF_CMP_DC_OUT__W 12 +#define IQM_AF_CMP_DC_OUT__M 0xFFF +#define IQM_AF_CMP_DC_OUT__PRE 0x0 +#define IQM_AF_CMP_DC_IN__A 0x187003D +#define IQM_AF_CMP_DC_IN__W 13 +#define IQM_AF_CMP_DC_IN__M 0x1FFF +#define IQM_AF_CMP_DC_IN__PRE 0x0 + +#define IQM_AF_CMP_DC_IN_DC__B 0 +#define IQM_AF_CMP_DC_IN_DC__W 12 +#define IQM_AF_CMP_DC_IN_DC__M 0xFFF +#define IQM_AF_CMP_DC_IN_DC__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN__B 12 +#define IQM_AF_CMP_DC_IN_DC_EN__W 1 +#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000 +#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0 +#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000 + + +#define IQM_AF_CMP_AMP__A 0x187003E +#define IQM_AF_CMP_AMP__W 10 +#define IQM_AF_CMP_AMP__M 0x3FF +#define IQM_AF_CMP_AMP__PRE 0x0 +#define IQM_AF_CMP_DN_AVG__A 0x187003F +#define IQM_AF_CMP_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG__PRE 0x0 + +#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0 +#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8 +#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF +#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0 + + +#define IQM_AF_CMP_ACTIVE__A 0x1870040 +#define IQM_AF_CMP_ACTIVE__W 1 +#define IQM_AF_CMP_ACTIVE__M 0x1 +#define IQM_AF_CMP_ACTIVE__PRE 0x0 +#define IQM_AF_CMP_MEM0__A 0x1870080 +#define IQM_AF_CMP_MEM0__W 13 +#define IQM_AF_CMP_MEM0__M 0x1FFF +#define IQM_AF_CMP_MEM0__PRE 0x0 + +#define IQM_AF_CMP_MEM0_COEF__B 0 +#define IQM_AF_CMP_MEM0_COEF__W 13 +#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM0_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM1__A 0x1870081 +#define IQM_AF_CMP_MEM1__W 13 +#define IQM_AF_CMP_MEM1__M 0x1FFF +#define IQM_AF_CMP_MEM1__PRE 0x0 + +#define IQM_AF_CMP_MEM1_COEF__B 0 +#define IQM_AF_CMP_MEM1_COEF__W 13 +#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM1_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM2__A 0x1870082 +#define IQM_AF_CMP_MEM2__W 13 +#define IQM_AF_CMP_MEM2__M 0x1FFF +#define IQM_AF_CMP_MEM2__PRE 0x0 + +#define IQM_AF_CMP_MEM2_COEF__B 0 +#define IQM_AF_CMP_MEM2_COEF__W 13 +#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM2_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM3__A 0x1870083 +#define IQM_AF_CMP_MEM3__W 13 +#define IQM_AF_CMP_MEM3__M 0x1FFF +#define IQM_AF_CMP_MEM3__PRE 0x0 + +#define IQM_AF_CMP_MEM3_COEF__B 0 +#define IQM_AF_CMP_MEM3_COEF__W 13 +#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM3_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM4__A 0x1870084 +#define IQM_AF_CMP_MEM4__W 13 +#define IQM_AF_CMP_MEM4__M 0x1FFF +#define IQM_AF_CMP_MEM4__PRE 0x0 + +#define IQM_AF_CMP_MEM4_COEF__B 0 +#define IQM_AF_CMP_MEM4_COEF__W 13 +#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM4_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM5__A 0x1870085 +#define IQM_AF_CMP_MEM5__W 13 +#define IQM_AF_CMP_MEM5__M 0x1FFF +#define IQM_AF_CMP_MEM5__PRE 0x0 + +#define IQM_AF_CMP_MEM5_COEF__B 0 +#define IQM_AF_CMP_MEM5_COEF__W 13 +#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM5_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM6__A 0x1870086 +#define IQM_AF_CMP_MEM6__W 13 +#define IQM_AF_CMP_MEM6__M 0x1FFF +#define IQM_AF_CMP_MEM6__PRE 0x0 + +#define IQM_AF_CMP_MEM6_COEF__B 0 +#define IQM_AF_CMP_MEM6_COEF__W 13 +#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM6_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM7__A 0x1870087 +#define IQM_AF_CMP_MEM7__W 13 +#define IQM_AF_CMP_MEM7__M 0x1FFF +#define IQM_AF_CMP_MEM7__PRE 0x0 + +#define IQM_AF_CMP_MEM7_COEF__B 0 +#define IQM_AF_CMP_MEM7_COEF__W 13 +#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM7_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM8__A 0x1870088 +#define IQM_AF_CMP_MEM8__W 13 +#define IQM_AF_CMP_MEM8__M 0x1FFF +#define IQM_AF_CMP_MEM8__PRE 0x0 + +#define IQM_AF_CMP_MEM8_COEF__B 0 +#define IQM_AF_CMP_MEM8_COEF__W 13 +#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM8_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM9__A 0x1870089 +#define IQM_AF_CMP_MEM9__W 13 +#define IQM_AF_CMP_MEM9__M 0x1FFF +#define IQM_AF_CMP_MEM9__PRE 0x0 + +#define IQM_AF_CMP_MEM9_COEF__B 0 +#define IQM_AF_CMP_MEM9_COEF__W 13 +#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM9_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM10__A 0x187008A +#define IQM_AF_CMP_MEM10__W 13 +#define IQM_AF_CMP_MEM10__M 0x1FFF +#define IQM_AF_CMP_MEM10__PRE 0x0 + +#define IQM_AF_CMP_MEM10_COEF__B 0 +#define IQM_AF_CMP_MEM10_COEF__W 13 +#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM10_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM11__A 0x187008B +#define IQM_AF_CMP_MEM11__W 13 +#define IQM_AF_CMP_MEM11__M 0x1FFF +#define IQM_AF_CMP_MEM11__PRE 0x0 + +#define IQM_AF_CMP_MEM11_COEF__B 0 +#define IQM_AF_CMP_MEM11_COEF__W 13 +#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM11_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM12__A 0x187008C +#define IQM_AF_CMP_MEM12__W 13 +#define IQM_AF_CMP_MEM12__M 0x1FFF +#define IQM_AF_CMP_MEM12__PRE 0x0 + +#define IQM_AF_CMP_MEM12_COEF__B 0 +#define IQM_AF_CMP_MEM12_COEF__W 13 +#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM12_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM13__A 0x187008D +#define IQM_AF_CMP_MEM13__W 13 +#define IQM_AF_CMP_MEM13__M 0x1FFF +#define IQM_AF_CMP_MEM13__PRE 0x0 + +#define IQM_AF_CMP_MEM13_COEF__B 0 +#define IQM_AF_CMP_MEM13_COEF__W 13 +#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM13_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM14__A 0x187008E +#define IQM_AF_CMP_MEM14__W 13 +#define IQM_AF_CMP_MEM14__M 0x1FFF +#define IQM_AF_CMP_MEM14__PRE 0x0 + +#define IQM_AF_CMP_MEM14_COEF__B 0 +#define IQM_AF_CMP_MEM14_COEF__W 13 +#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM14_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM15__A 0x187008F +#define IQM_AF_CMP_MEM15__W 13 +#define IQM_AF_CMP_MEM15__M 0x1FFF +#define IQM_AF_CMP_MEM15__PRE 0x0 + +#define IQM_AF_CMP_MEM15_COEF__B 0 +#define IQM_AF_CMP_MEM15_COEF__W 13 +#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM15_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM16__A 0x1870090 +#define IQM_AF_CMP_MEM16__W 13 +#define IQM_AF_CMP_MEM16__M 0x1FFF +#define IQM_AF_CMP_MEM16__PRE 0x0 + +#define IQM_AF_CMP_MEM16_COEF__B 0 +#define IQM_AF_CMP_MEM16_COEF__W 13 +#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM16_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM17__A 0x1870091 +#define IQM_AF_CMP_MEM17__W 13 +#define IQM_AF_CMP_MEM17__M 0x1FFF +#define IQM_AF_CMP_MEM17__PRE 0x0 + +#define IQM_AF_CMP_MEM17_COEF__B 0 +#define IQM_AF_CMP_MEM17_COEF__W 13 +#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM17_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM18__A 0x1870092 +#define IQM_AF_CMP_MEM18__W 13 +#define IQM_AF_CMP_MEM18__M 0x1FFF +#define IQM_AF_CMP_MEM18__PRE 0x0 + +#define IQM_AF_CMP_MEM18_COEF__B 0 +#define IQM_AF_CMP_MEM18_COEF__W 13 +#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM18_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM19__A 0x1870093 +#define IQM_AF_CMP_MEM19__W 13 +#define IQM_AF_CMP_MEM19__M 0x1FFF +#define IQM_AF_CMP_MEM19__PRE 0x0 + +#define IQM_AF_CMP_MEM19_COEF__B 0 +#define IQM_AF_CMP_MEM19_COEF__W 13 +#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM19_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM20__A 0x1870094 +#define IQM_AF_CMP_MEM20__W 13 +#define IQM_AF_CMP_MEM20__M 0x1FFF +#define IQM_AF_CMP_MEM20__PRE 0x0 + +#define IQM_AF_CMP_MEM20_COEF__B 0 +#define IQM_AF_CMP_MEM20_COEF__W 13 +#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM20_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM21__A 0x1870095 +#define IQM_AF_CMP_MEM21__W 13 +#define IQM_AF_CMP_MEM21__M 0x1FFF +#define IQM_AF_CMP_MEM21__PRE 0x0 + +#define IQM_AF_CMP_MEM21_COEF__B 0 +#define IQM_AF_CMP_MEM21_COEF__W 13 +#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM21_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM22__A 0x1870096 +#define IQM_AF_CMP_MEM22__W 13 +#define IQM_AF_CMP_MEM22__M 0x1FFF +#define IQM_AF_CMP_MEM22__PRE 0x0 + +#define IQM_AF_CMP_MEM22_COEF__B 0 +#define IQM_AF_CMP_MEM22_COEF__W 13 +#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM22_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM23__A 0x1870097 +#define IQM_AF_CMP_MEM23__W 13 +#define IQM_AF_CMP_MEM23__M 0x1FFF +#define IQM_AF_CMP_MEM23__PRE 0x0 + +#define IQM_AF_CMP_MEM23_COEF__B 0 +#define IQM_AF_CMP_MEM23_COEF__W 13 +#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM23_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM24__A 0x1870098 +#define IQM_AF_CMP_MEM24__W 13 +#define IQM_AF_CMP_MEM24__M 0x1FFF +#define IQM_AF_CMP_MEM24__PRE 0x0 + +#define IQM_AF_CMP_MEM24_COEF__B 0 +#define IQM_AF_CMP_MEM24_COEF__W 13 +#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM24_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM25__A 0x1870099 +#define IQM_AF_CMP_MEM25__W 13 +#define IQM_AF_CMP_MEM25__M 0x1FFF +#define IQM_AF_CMP_MEM25__PRE 0x0 + +#define IQM_AF_CMP_MEM25_COEF__B 0 +#define IQM_AF_CMP_MEM25_COEF__W 13 +#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM25_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM26__A 0x187009A +#define IQM_AF_CMP_MEM26__W 13 +#define IQM_AF_CMP_MEM26__M 0x1FFF +#define IQM_AF_CMP_MEM26__PRE 0x0 + +#define IQM_AF_CMP_MEM26_COEF__B 0 +#define IQM_AF_CMP_MEM26_COEF__W 13 +#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM26_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM27__A 0x187009B +#define IQM_AF_CMP_MEM27__W 13 +#define IQM_AF_CMP_MEM27__M 0x1FFF +#define IQM_AF_CMP_MEM27__PRE 0x0 + +#define IQM_AF_CMP_MEM27_COEF__B 0 +#define IQM_AF_CMP_MEM27_COEF__W 13 +#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM27_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM28__A 0x187009C +#define IQM_AF_CMP_MEM28__W 13 +#define IQM_AF_CMP_MEM28__M 0x1FFF +#define IQM_AF_CMP_MEM28__PRE 0x0 + +#define IQM_AF_CMP_MEM28_COEF__B 0 +#define IQM_AF_CMP_MEM28_COEF__W 13 +#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM28_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM29__A 0x187009D +#define IQM_AF_CMP_MEM29__W 13 +#define IQM_AF_CMP_MEM29__M 0x1FFF +#define IQM_AF_CMP_MEM29__PRE 0x0 + +#define IQM_AF_CMP_MEM29_COEF__B 0 +#define IQM_AF_CMP_MEM29_COEF__W 13 +#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM29_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM30__A 0x187009E +#define IQM_AF_CMP_MEM30__W 13 +#define IQM_AF_CMP_MEM30__M 0x1FFF +#define IQM_AF_CMP_MEM30__PRE 0x0 + +#define IQM_AF_CMP_MEM30_COEF__B 0 +#define IQM_AF_CMP_MEM30_COEF__W 13 +#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM30_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM31__A 0x187009F +#define IQM_AF_CMP_MEM31__W 13 +#define IQM_AF_CMP_MEM31__M 0x1FFF +#define IQM_AF_CMP_MEM31__PRE 0x0 + +#define IQM_AF_CMP_MEM31_COEF__B 0 +#define IQM_AF_CMP_MEM31_COEF__W 13 +#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM31_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM32__A 0x18700A0 +#define IQM_AF_CMP_MEM32__W 13 +#define IQM_AF_CMP_MEM32__M 0x1FFF +#define IQM_AF_CMP_MEM32__PRE 0x0 + +#define IQM_AF_CMP_MEM32_COEF__B 0 +#define IQM_AF_CMP_MEM32_COEF__W 13 +#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM32_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM33__A 0x18700A1 +#define IQM_AF_CMP_MEM33__W 13 +#define IQM_AF_CMP_MEM33__M 0x1FFF +#define IQM_AF_CMP_MEM33__PRE 0x0 + +#define IQM_AF_CMP_MEM33_COEF__B 0 +#define IQM_AF_CMP_MEM33_COEF__W 13 +#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM33_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM34__A 0x18700A2 +#define IQM_AF_CMP_MEM34__W 13 +#define IQM_AF_CMP_MEM34__M 0x1FFF +#define IQM_AF_CMP_MEM34__PRE 0x0 + +#define IQM_AF_CMP_MEM34_COEF__B 0 +#define IQM_AF_CMP_MEM34_COEF__W 13 +#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM34_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM35__A 0x18700A3 +#define IQM_AF_CMP_MEM35__W 13 +#define IQM_AF_CMP_MEM35__M 0x1FFF +#define IQM_AF_CMP_MEM35__PRE 0x0 + +#define IQM_AF_CMP_MEM35_COEF__B 0 +#define IQM_AF_CMP_MEM35_COEF__W 13 +#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM35_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM36__A 0x18700A4 +#define IQM_AF_CMP_MEM36__W 13 +#define IQM_AF_CMP_MEM36__M 0x1FFF +#define IQM_AF_CMP_MEM36__PRE 0x0 + +#define IQM_AF_CMP_MEM36_COEF__B 0 +#define IQM_AF_CMP_MEM36_COEF__W 13 +#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM36_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM37__A 0x18700A5 +#define IQM_AF_CMP_MEM37__W 13 +#define IQM_AF_CMP_MEM37__M 0x1FFF +#define IQM_AF_CMP_MEM37__PRE 0x0 + +#define IQM_AF_CMP_MEM37_COEF__B 0 +#define IQM_AF_CMP_MEM37_COEF__W 13 +#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM37_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM38__A 0x18700A6 +#define IQM_AF_CMP_MEM38__W 13 +#define IQM_AF_CMP_MEM38__M 0x1FFF +#define IQM_AF_CMP_MEM38__PRE 0x0 + +#define IQM_AF_CMP_MEM38_COEF__B 0 +#define IQM_AF_CMP_MEM38_COEF__W 13 +#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM38_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM39__A 0x18700A7 +#define IQM_AF_CMP_MEM39__W 13 +#define IQM_AF_CMP_MEM39__M 0x1FFF +#define IQM_AF_CMP_MEM39__PRE 0x0 + +#define IQM_AF_CMP_MEM39_COEF__B 0 +#define IQM_AF_CMP_MEM39_COEF__W 13 +#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM39_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM40__A 0x18700A8 +#define IQM_AF_CMP_MEM40__W 13 +#define IQM_AF_CMP_MEM40__M 0x1FFF +#define IQM_AF_CMP_MEM40__PRE 0x0 + +#define IQM_AF_CMP_MEM40_COEF__B 0 +#define IQM_AF_CMP_MEM40_COEF__W 13 +#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM40_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM41__A 0x18700A9 +#define IQM_AF_CMP_MEM41__W 13 +#define IQM_AF_CMP_MEM41__M 0x1FFF +#define IQM_AF_CMP_MEM41__PRE 0x0 + +#define IQM_AF_CMP_MEM41_COEF__B 0 +#define IQM_AF_CMP_MEM41_COEF__W 13 +#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM41_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM42__A 0x18700AA +#define IQM_AF_CMP_MEM42__W 13 +#define IQM_AF_CMP_MEM42__M 0x1FFF +#define IQM_AF_CMP_MEM42__PRE 0x0 + +#define IQM_AF_CMP_MEM42_COEF__B 0 +#define IQM_AF_CMP_MEM42_COEF__W 13 +#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM42_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM43__A 0x18700AB +#define IQM_AF_CMP_MEM43__W 13 +#define IQM_AF_CMP_MEM43__M 0x1FFF +#define IQM_AF_CMP_MEM43__PRE 0x0 + +#define IQM_AF_CMP_MEM43_COEF__B 0 +#define IQM_AF_CMP_MEM43_COEF__W 13 +#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM43_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM44__A 0x18700AC +#define IQM_AF_CMP_MEM44__W 13 +#define IQM_AF_CMP_MEM44__M 0x1FFF +#define IQM_AF_CMP_MEM44__PRE 0x0 + +#define IQM_AF_CMP_MEM44_COEF__B 0 +#define IQM_AF_CMP_MEM44_COEF__W 13 +#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM44_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM45__A 0x18700AD +#define IQM_AF_CMP_MEM45__W 13 +#define IQM_AF_CMP_MEM45__M 0x1FFF +#define IQM_AF_CMP_MEM45__PRE 0x0 + +#define IQM_AF_CMP_MEM45_COEF__B 0 +#define IQM_AF_CMP_MEM45_COEF__W 13 +#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM45_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM46__A 0x18700AE +#define IQM_AF_CMP_MEM46__W 13 +#define IQM_AF_CMP_MEM46__M 0x1FFF +#define IQM_AF_CMP_MEM46__PRE 0x0 + +#define IQM_AF_CMP_MEM46_COEF__B 0 +#define IQM_AF_CMP_MEM46_COEF__W 13 +#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM46_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM47__A 0x18700AF +#define IQM_AF_CMP_MEM47__W 13 +#define IQM_AF_CMP_MEM47__M 0x1FFF +#define IQM_AF_CMP_MEM47__PRE 0x0 + +#define IQM_AF_CMP_MEM47_COEF__B 0 +#define IQM_AF_CMP_MEM47_COEF__W 13 +#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM47_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM48__A 0x18700B0 +#define IQM_AF_CMP_MEM48__W 13 +#define IQM_AF_CMP_MEM48__M 0x1FFF +#define IQM_AF_CMP_MEM48__PRE 0x0 + +#define IQM_AF_CMP_MEM48_COEF__B 0 +#define IQM_AF_CMP_MEM48_COEF__W 13 +#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM48_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM49__A 0x18700B1 +#define IQM_AF_CMP_MEM49__W 13 +#define IQM_AF_CMP_MEM49__M 0x1FFF +#define IQM_AF_CMP_MEM49__PRE 0x0 + +#define IQM_AF_CMP_MEM49_COEF__B 0 +#define IQM_AF_CMP_MEM49_COEF__W 13 +#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM49_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM50__A 0x18700B2 +#define IQM_AF_CMP_MEM50__W 13 +#define IQM_AF_CMP_MEM50__M 0x1FFF +#define IQM_AF_CMP_MEM50__PRE 0x0 + +#define IQM_AF_CMP_MEM50_COEF__B 0 +#define IQM_AF_CMP_MEM50_COEF__W 13 +#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM50_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM51__A 0x18700B3 +#define IQM_AF_CMP_MEM51__W 13 +#define IQM_AF_CMP_MEM51__M 0x1FFF +#define IQM_AF_CMP_MEM51__PRE 0x0 + +#define IQM_AF_CMP_MEM51_COEF__B 0 +#define IQM_AF_CMP_MEM51_COEF__W 13 +#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM51_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM52__A 0x18700B4 +#define IQM_AF_CMP_MEM52__W 13 +#define IQM_AF_CMP_MEM52__M 0x1FFF +#define IQM_AF_CMP_MEM52__PRE 0x0 + +#define IQM_AF_CMP_MEM52_COEF__B 0 +#define IQM_AF_CMP_MEM52_COEF__W 13 +#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM52_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM53__A 0x18700B5 +#define IQM_AF_CMP_MEM53__W 13 +#define IQM_AF_CMP_MEM53__M 0x1FFF +#define IQM_AF_CMP_MEM53__PRE 0x0 + +#define IQM_AF_CMP_MEM53_COEF__B 0 +#define IQM_AF_CMP_MEM53_COEF__W 13 +#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM53_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM54__A 0x18700B6 +#define IQM_AF_CMP_MEM54__W 13 +#define IQM_AF_CMP_MEM54__M 0x1FFF +#define IQM_AF_CMP_MEM54__PRE 0x0 + +#define IQM_AF_CMP_MEM54_COEF__B 0 +#define IQM_AF_CMP_MEM54_COEF__W 13 +#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM54_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM55__A 0x18700B7 +#define IQM_AF_CMP_MEM55__W 13 +#define IQM_AF_CMP_MEM55__M 0x1FFF +#define IQM_AF_CMP_MEM55__PRE 0x0 + +#define IQM_AF_CMP_MEM55_COEF__B 0 +#define IQM_AF_CMP_MEM55_COEF__W 13 +#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM55_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM56__A 0x18700B8 +#define IQM_AF_CMP_MEM56__W 13 +#define IQM_AF_CMP_MEM56__M 0x1FFF +#define IQM_AF_CMP_MEM56__PRE 0x0 + +#define IQM_AF_CMP_MEM56_COEF__B 0 +#define IQM_AF_CMP_MEM56_COEF__W 13 +#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM56_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM57__A 0x18700B9 +#define IQM_AF_CMP_MEM57__W 13 +#define IQM_AF_CMP_MEM57__M 0x1FFF +#define IQM_AF_CMP_MEM57__PRE 0x0 + +#define IQM_AF_CMP_MEM57_COEF__B 0 +#define IQM_AF_CMP_MEM57_COEF__W 13 +#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM57_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM58__A 0x18700BA +#define IQM_AF_CMP_MEM58__W 13 +#define IQM_AF_CMP_MEM58__M 0x1FFF +#define IQM_AF_CMP_MEM58__PRE 0x0 + +#define IQM_AF_CMP_MEM58_COEF__B 0 +#define IQM_AF_CMP_MEM58_COEF__W 13 +#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM58_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM59__A 0x18700BB +#define IQM_AF_CMP_MEM59__W 13 +#define IQM_AF_CMP_MEM59__M 0x1FFF +#define IQM_AF_CMP_MEM59__PRE 0x0 + +#define IQM_AF_CMP_MEM59_COEF__B 0 +#define IQM_AF_CMP_MEM59_COEF__W 13 +#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM59_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM60__A 0x18700BC +#define IQM_AF_CMP_MEM60__W 13 +#define IQM_AF_CMP_MEM60__M 0x1FFF +#define IQM_AF_CMP_MEM60__PRE 0x0 + +#define IQM_AF_CMP_MEM60_COEF__B 0 +#define IQM_AF_CMP_MEM60_COEF__W 13 +#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM60_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM61__A 0x18700BD +#define IQM_AF_CMP_MEM61__W 13 +#define IQM_AF_CMP_MEM61__M 0x1FFF +#define IQM_AF_CMP_MEM61__PRE 0x0 + +#define IQM_AF_CMP_MEM61_COEF__B 0 +#define IQM_AF_CMP_MEM61_COEF__W 13 +#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM61_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM62__A 0x18700BE +#define IQM_AF_CMP_MEM62__W 13 +#define IQM_AF_CMP_MEM62__M 0x1FFF +#define IQM_AF_CMP_MEM62__PRE 0x0 + +#define IQM_AF_CMP_MEM62_COEF__B 0 +#define IQM_AF_CMP_MEM62_COEF__W 13 +#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM62_COEF__PRE 0x0 + +#define IQM_AF_CMP_MEM63__A 0x18700BF +#define IQM_AF_CMP_MEM63__W 13 +#define IQM_AF_CMP_MEM63__M 0x1FFF +#define IQM_AF_CMP_MEM63__PRE 0x0 + +#define IQM_AF_CMP_MEM63_COEF__B 0 +#define IQM_AF_CMP_MEM63_COEF__W 13 +#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF +#define IQM_AF_CMP_MEM63_COEF__PRE 0x0 + + + +#define IQM_RT_RAM__A 0x1880000 + +#define IQM_RT_RAM_DLY__B 0 +#define IQM_RT_RAM_DLY__W 13 +#define IQM_RT_RAM_DLY__M 0x1FFF +#define IQM_RT_RAM_DLY__PRE 0x0 + + + + + +#define OFDM_CE_COMM_EXEC__A 0x2C00000 +#define OFDM_CE_COMM_EXEC__W 3 +#define OFDM_CE_COMM_EXEC__M 0x7 +#define OFDM_CE_COMM_EXEC__PRE 0x0 +#define OFDM_CE_COMM_EXEC_STOP 0x0 +#define OFDM_CE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_COMM_EXEC_STEP 0x3 +#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CE_COMM_STATE__A 0x2C00001 +#define OFDM_CE_COMM_STATE__W 16 +#define OFDM_CE_COMM_STATE__M 0xFFFF +#define OFDM_CE_COMM_STATE__PRE 0x0 +#define OFDM_CE_COMM_MB__A 0x2C00002 +#define OFDM_CE_COMM_MB__W 16 +#define OFDM_CE_COMM_MB__M 0xFFFF +#define OFDM_CE_COMM_MB__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ__A 0x2C00004 +#define OFDM_CE_COMM_INT_REQ__W 16 +#define OFDM_CE_COMM_INT_REQ__M 0xFFFF +#define OFDM_CE_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4 +#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CE_COMM_INT_STA__A 0x2C00005 +#define OFDM_CE_COMM_INT_STA__W 16 +#define OFDM_CE_COMM_INT_STA__M 0xFFFF +#define OFDM_CE_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_COMM_INT_MSK__A 0x2C00006 +#define OFDM_CE_COMM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_COMM_INT_STM__A 0x2C00007 +#define OFDM_CE_COMM_INT_STM__W 16 +#define OFDM_CE_COMM_INT_STM__M 0xFFFF +#define OFDM_CE_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000 +#define OFDM_CE_TOP_COMM_EXEC__W 3 +#define OFDM_CE_TOP_COMM_EXEC__M 0x7 +#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CE_TOP_COMM_MB__A 0x2C10002 +#define OFDM_CE_TOP_COMM_MB__W 4 +#define OFDM_CE_TOP_COMM_MB__M 0xF +#define OFDM_CE_TOP_COMM_MB__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL__B 0 +#define OFDM_CE_TOP_COMM_MB_CTL__W 1 +#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CE_TOP_COMM_MB_OBS__B 1 +#define OFDM_CE_TOP_COMM_MB_OBS__W 1 +#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC +#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8 +#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC + +#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004 +#define OFDM_CE_TOP_COMM_INT_REQ__W 1 +#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005 +#define OFDM_CE_TOP_COMM_INT_STA__W 3 +#define OFDM_CE_TOP_COMM_INT_STA__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006 +#define OFDM_CE_TOP_COMM_INT_MSK__W 3 +#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7 +#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0 + +#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007 +#define OFDM_CE_TOP_COMM_INT_STM__W 3 +#define OFDM_CE_TOP_COMM_INT_STM__M 0x7 +#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4 +#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0 + + +#define OFDM_CE_TOP_MODE_2K__A 0x2C10010 +#define OFDM_CE_TOP_MODE_2K__W 1 +#define OFDM_CE_TOP_MODE_2K__M 0x1 +#define OFDM_CE_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CE_TOP_TAPSET__A 0x2C10011 +#define OFDM_CE_TOP_TAPSET__W 4 +#define OFDM_CE_TOP_TAPSET__M 0xF +#define OFDM_CE_TOP_TAPSET__PRE 0x1 +#define OFDM_CE_TOP_AVG_POW__A 0x2C10012 +#define OFDM_CE_TOP_AVG_POW__W 8 +#define OFDM_CE_TOP_AVG_POW__M 0xFF +#define OFDM_CE_TOP_AVG_POW__PRE 0x65 +#define OFDM_CE_TOP_MAX_POW__A 0x2C10013 +#define OFDM_CE_TOP_MAX_POW__W 8 +#define OFDM_CE_TOP_MAX_POW__M 0xFF +#define OFDM_CE_TOP_MAX_POW__PRE 0x80 +#define OFDM_CE_TOP_ATT__A 0x2C10014 +#define OFDM_CE_TOP_ATT__W 8 +#define OFDM_CE_TOP_ATT__M 0xFF +#define OFDM_CE_TOP_ATT__PRE 0x70 +#define OFDM_CE_TOP_NRED__A 0x2C10015 +#define OFDM_CE_TOP_NRED__W 6 +#define OFDM_CE_TOP_NRED__M 0x3F +#define OFDM_CE_TOP_NRED__PRE 0x9 + +#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020 +#define OFDM_CE_TOP_PU_SIGN__W 1 +#define OFDM_CE_TOP_PU_SIGN__M 0x1 +#define OFDM_CE_TOP_PU_SIGN__PRE 0x0 + +#define OFDM_CE_TOP_PU_MIX__A 0x2C10021 +#define OFDM_CE_TOP_PU_MIX__W 1 +#define OFDM_CE_TOP_PU_MIX__M 0x1 +#define OFDM_CE_TOP_PU_MIX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030 +#define OFDM_CE_TOP_PB_PILOT_REQ__W 15 +#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF +#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12 +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF +#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0 + + +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1 +#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0 + +#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032 +#define OFDM_CE_TOP_PB_FREEZE__W 1 +#define OFDM_CE_TOP_PB_FREEZE__M 0x1 +#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038 +#define OFDM_CE_TOP_PB_PILOT_EXP__W 4 +#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF +#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039 +#define OFDM_CE_TOP_PB_PILOT_REAL__W 10 +#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0 + +#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A +#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10 +#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF +#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B +#define OFDM_CE_TOP_PB_SMBNR__W 5 +#define OFDM_CE_TOP_PB_SMBNR__M 0x1F +#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0 + +#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040 +#define OFDM_CE_TOP_NE_PILOT_REQ__W 12 +#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF +#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 +#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0 + + +#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042 +#define OFDM_CE_TOP_NE_PILOT_DATA__W 10 +#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF +#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0 +#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043 +#define OFDM_CE_TOP_NE_ERR_SELECT__W 5 +#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F +#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10 +#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8 +#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0 + +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4 +#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4 + +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2 +#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2 + +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1 +#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1 + + +#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044 +#define OFDM_CE_TOP_NE_TD_CAL__W 9 +#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8 + +#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045 +#define OFDM_CE_TOP_NE_FD_CAL__W 9 +#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF +#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9 + +#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046 +#define OFDM_CE_TOP_NE_MIXAVG__W 3 +#define OFDM_CE_TOP_NE_MIXAVG__M 0x7 +#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6 + +#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047 +#define OFDM_CE_TOP_NE_NUPD_OFS__W 4 +#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF +#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4 +#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048 +#define OFDM_CE_TOP_NE_TD_POW__W 15 +#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049 +#define OFDM_CE_TOP_NE_FD_POW__W 15 +#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF +#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10 +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A +#define OFDM_CE_TOP_NE_NEXP_AVG__W 8 +#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF +#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0 + +#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B +#define OFDM_CE_TOP_NE_OFFSET__W 9 +#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF +#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0 + +#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C +#define OFDM_CE_TOP_NE_NUPD_TRH__W 5 +#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F +#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14 + +#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050 +#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8 +#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF +#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0 + +#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051 +#define OFDM_CE_TOP_PE_TIMESHIFT__W 14 +#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF +#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052 +#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054 +#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16 +#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056 +#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058 +#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16 +#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16 +#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF +#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A +#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0 + +#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B +#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5 +#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F +#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0 + +#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060 +#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1 +#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1 +#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100 + +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE + +#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1 +#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5 +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F +#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA + +#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B +#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C +#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0 + +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF +#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0 + + +#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072 +#define OFDM_CE_TOP_TI_SYM_CNT__W 6 +#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F +#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20 + +#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073 +#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1 +#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1 + +#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074 +#define OFDM_CE_TOP_TI_SHIFT__W 2 +#define OFDM_CE_TOP_TI_SHIFT__M 0x3 +#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0 + +#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075 +#define OFDM_CE_TOP_TI_SLOW__W 1 +#define OFDM_CE_TOP_TI_SLOW__M 0x1 +#define OFDM_CE_TOP_TI_SLOW__PRE 0x1 + +#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076 +#define OFDM_CE_TOP_TI_MGAIN__W 8 +#define OFDM_CE_TOP_TI_MGAIN__M 0xFF +#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0 + +#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077 +#define OFDM_CE_TOP_TI_ACCU1__W 8 +#define OFDM_CE_TOP_TI_ACCU1__M 0xFF +#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0 + +#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0 +#define OFDM_CE_TOP_NI_PER_LEFT__W 5 +#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F +#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE + +#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1 +#define OFDM_CE_TOP_NI_PER_RIGHT__W 5 +#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F +#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7 + +#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2 +#define OFDM_CE_TOP_NI_POS_LR__W 9 +#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF +#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0 + +#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090 +#define OFDM_CE_TOP_FI_SHT_INCR__W 9 +#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF +#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E + +#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091 +#define OFDM_CE_TOP_FI_EXP_NORM__W 4 +#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF +#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC + +#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092 +#define OFDM_CE_TOP_FI_SUPR_VAL__W 1 +#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1 +#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0 +#define OFDM_CE_TOP_IR_INPUTSEL__W 1 +#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1 +#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0 + +#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1 +#define OFDM_CE_TOP_IR_STARTPOS__W 8 +#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF +#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0 + +#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2 +#define OFDM_CE_TOP_IR_NEXP_THRES__W 8 +#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF +#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF + +#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3 +#define OFDM_CE_TOP_IR_LENGTH__W 4 +#define OFDM_CE_TOP_IR_LENGTH__M 0xF +#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9 + +#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4 +#define OFDM_CE_TOP_IR_FREQ__W 11 +#define OFDM_CE_TOP_IR_FREQ__M 0x7FF +#define OFDM_CE_TOP_IR_FREQ__PRE 0x0 + +#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5 +#define OFDM_CE_TOP_IR_FREQINC__W 11 +#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF +#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4 + +#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6 +#define OFDM_CE_TOP_IR_KAISINC__W 15 +#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF +#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100 + +#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7 +#define OFDM_CE_TOP_IR_CTL__W 3 +#define OFDM_CE_TOP_IR_CTL__M 0x7 +#define OFDM_CE_TOP_IR_CTL__PRE 0x0 + +#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8 +#define OFDM_CE_TOP_IR_REAL__W 16 +#define OFDM_CE_TOP_IR_REAL__M 0xFFFF +#define OFDM_CE_TOP_IR_REAL__PRE 0x0 + +#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9 +#define OFDM_CE_TOP_IR_IMAG__W 16 +#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF +#define OFDM_CE_TOP_IR_IMAG__PRE 0x0 + +#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA +#define OFDM_CE_TOP_IR_INDEX__W 12 +#define OFDM_CE_TOP_IR_INDEX__M 0xFFF +#define OFDM_CE_TOP_IR_INDEX__PRE 0x0 + + + +#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000 +#define OFDM_CE_FR_COMM_EXEC__W 3 +#define OFDM_CE_FR_COMM_EXEC__M 0x7 +#define OFDM_CE_FR_COMM_EXEC__PRE 0x0 +#define OFDM_CE_FR_COMM_EXEC_STOP 0x0 +#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2 +#define OFDM_CE_FR_COMM_EXEC_STEP 0x3 + + +#define OFDM_CE_FR_TREAL00__A 0x2C20010 +#define OFDM_CE_FR_TREAL00__W 11 +#define OFDM_CE_FR_TREAL00__M 0x7FF +#define OFDM_CE_FR_TREAL00__PRE 0x52 + +#define OFDM_CE_FR_TIMAG00__A 0x2C20011 +#define OFDM_CE_FR_TIMAG00__W 11 +#define OFDM_CE_FR_TIMAG00__M 0x7FF +#define OFDM_CE_FR_TIMAG00__PRE 0x0 + +#define OFDM_CE_FR_TREAL01__A 0x2C20012 +#define OFDM_CE_FR_TREAL01__W 11 +#define OFDM_CE_FR_TREAL01__M 0x7FF +#define OFDM_CE_FR_TREAL01__PRE 0x52 + +#define OFDM_CE_FR_TIMAG01__A 0x2C20013 +#define OFDM_CE_FR_TIMAG01__W 11 +#define OFDM_CE_FR_TIMAG01__M 0x7FF +#define OFDM_CE_FR_TIMAG01__PRE 0x0 + +#define OFDM_CE_FR_TREAL02__A 0x2C20014 +#define OFDM_CE_FR_TREAL02__W 11 +#define OFDM_CE_FR_TREAL02__M 0x7FF +#define OFDM_CE_FR_TREAL02__PRE 0x52 + +#define OFDM_CE_FR_TIMAG02__A 0x2C20015 +#define OFDM_CE_FR_TIMAG02__W 11 +#define OFDM_CE_FR_TIMAG02__M 0x7FF +#define OFDM_CE_FR_TIMAG02__PRE 0x0 + +#define OFDM_CE_FR_TREAL03__A 0x2C20016 +#define OFDM_CE_FR_TREAL03__W 11 +#define OFDM_CE_FR_TREAL03__M 0x7FF +#define OFDM_CE_FR_TREAL03__PRE 0x52 + +#define OFDM_CE_FR_TIMAG03__A 0x2C20017 +#define OFDM_CE_FR_TIMAG03__W 11 +#define OFDM_CE_FR_TIMAG03__M 0x7FF +#define OFDM_CE_FR_TIMAG03__PRE 0x0 + +#define OFDM_CE_FR_TREAL04__A 0x2C20018 +#define OFDM_CE_FR_TREAL04__W 11 +#define OFDM_CE_FR_TREAL04__M 0x7FF +#define OFDM_CE_FR_TREAL04__PRE 0x52 + +#define OFDM_CE_FR_TIMAG04__A 0x2C20019 +#define OFDM_CE_FR_TIMAG04__W 11 +#define OFDM_CE_FR_TIMAG04__M 0x7FF +#define OFDM_CE_FR_TIMAG04__PRE 0x0 + +#define OFDM_CE_FR_TREAL05__A 0x2C2001A +#define OFDM_CE_FR_TREAL05__W 11 +#define OFDM_CE_FR_TREAL05__M 0x7FF +#define OFDM_CE_FR_TREAL05__PRE 0x52 + +#define OFDM_CE_FR_TIMAG05__A 0x2C2001B +#define OFDM_CE_FR_TIMAG05__W 11 +#define OFDM_CE_FR_TIMAG05__M 0x7FF +#define OFDM_CE_FR_TIMAG05__PRE 0x0 + +#define OFDM_CE_FR_TREAL06__A 0x2C2001C +#define OFDM_CE_FR_TREAL06__W 11 +#define OFDM_CE_FR_TREAL06__M 0x7FF +#define OFDM_CE_FR_TREAL06__PRE 0x52 + +#define OFDM_CE_FR_TIMAG06__A 0x2C2001D +#define OFDM_CE_FR_TIMAG06__W 11 +#define OFDM_CE_FR_TIMAG06__M 0x7FF +#define OFDM_CE_FR_TIMAG06__PRE 0x0 + +#define OFDM_CE_FR_TREAL07__A 0x2C2001E +#define OFDM_CE_FR_TREAL07__W 11 +#define OFDM_CE_FR_TREAL07__M 0x7FF +#define OFDM_CE_FR_TREAL07__PRE 0x52 + +#define OFDM_CE_FR_TIMAG07__A 0x2C2001F +#define OFDM_CE_FR_TIMAG07__W 11 +#define OFDM_CE_FR_TIMAG07__M 0x7FF +#define OFDM_CE_FR_TIMAG07__PRE 0x0 + +#define OFDM_CE_FR_TREAL08__A 0x2C20020 +#define OFDM_CE_FR_TREAL08__W 11 +#define OFDM_CE_FR_TREAL08__M 0x7FF +#define OFDM_CE_FR_TREAL08__PRE 0x52 + +#define OFDM_CE_FR_TIMAG08__A 0x2C20021 +#define OFDM_CE_FR_TIMAG08__W 11 +#define OFDM_CE_FR_TIMAG08__M 0x7FF +#define OFDM_CE_FR_TIMAG08__PRE 0x0 + +#define OFDM_CE_FR_TREAL09__A 0x2C20022 +#define OFDM_CE_FR_TREAL09__W 11 +#define OFDM_CE_FR_TREAL09__M 0x7FF +#define OFDM_CE_FR_TREAL09__PRE 0x52 + +#define OFDM_CE_FR_TIMAG09__A 0x2C20023 +#define OFDM_CE_FR_TIMAG09__W 11 +#define OFDM_CE_FR_TIMAG09__M 0x7FF +#define OFDM_CE_FR_TIMAG09__PRE 0x0 + +#define OFDM_CE_FR_TREAL10__A 0x2C20024 +#define OFDM_CE_FR_TREAL10__W 11 +#define OFDM_CE_FR_TREAL10__M 0x7FF +#define OFDM_CE_FR_TREAL10__PRE 0x52 + +#define OFDM_CE_FR_TIMAG10__A 0x2C20025 +#define OFDM_CE_FR_TIMAG10__W 11 +#define OFDM_CE_FR_TIMAG10__M 0x7FF +#define OFDM_CE_FR_TIMAG10__PRE 0x0 + +#define OFDM_CE_FR_TREAL11__A 0x2C20026 +#define OFDM_CE_FR_TREAL11__W 11 +#define OFDM_CE_FR_TREAL11__M 0x7FF +#define OFDM_CE_FR_TREAL11__PRE 0x52 + +#define OFDM_CE_FR_TIMAG11__A 0x2C20027 +#define OFDM_CE_FR_TIMAG11__W 11 +#define OFDM_CE_FR_TIMAG11__M 0x7FF +#define OFDM_CE_FR_TIMAG11__PRE 0x0 + +#define OFDM_CE_FR_MID_TAP__A 0x2C20028 +#define OFDM_CE_FR_MID_TAP__W 11 +#define OFDM_CE_FR_MID_TAP__M 0x7FF +#define OFDM_CE_FR_MID_TAP__PRE 0x51 + +#define OFDM_CE_FR_SQS_G00__A 0x2C20029 +#define OFDM_CE_FR_SQS_G00__W 8 +#define OFDM_CE_FR_SQS_G00__M 0xFF +#define OFDM_CE_FR_SQS_G00__PRE 0xB + +#define OFDM_CE_FR_SQS_G01__A 0x2C2002A +#define OFDM_CE_FR_SQS_G01__W 8 +#define OFDM_CE_FR_SQS_G01__M 0xFF +#define OFDM_CE_FR_SQS_G01__PRE 0xB + +#define OFDM_CE_FR_SQS_G02__A 0x2C2002B +#define OFDM_CE_FR_SQS_G02__W 8 +#define OFDM_CE_FR_SQS_G02__M 0xFF +#define OFDM_CE_FR_SQS_G02__PRE 0xB + +#define OFDM_CE_FR_SQS_G03__A 0x2C2002C +#define OFDM_CE_FR_SQS_G03__W 8 +#define OFDM_CE_FR_SQS_G03__M 0xFF +#define OFDM_CE_FR_SQS_G03__PRE 0xB + +#define OFDM_CE_FR_SQS_G04__A 0x2C2002D +#define OFDM_CE_FR_SQS_G04__W 8 +#define OFDM_CE_FR_SQS_G04__M 0xFF +#define OFDM_CE_FR_SQS_G04__PRE 0xB + +#define OFDM_CE_FR_SQS_G05__A 0x2C2002E +#define OFDM_CE_FR_SQS_G05__W 8 +#define OFDM_CE_FR_SQS_G05__M 0xFF +#define OFDM_CE_FR_SQS_G05__PRE 0xB + +#define OFDM_CE_FR_SQS_G06__A 0x2C2002F +#define OFDM_CE_FR_SQS_G06__W 8 +#define OFDM_CE_FR_SQS_G06__M 0xFF +#define OFDM_CE_FR_SQS_G06__PRE 0xB + +#define OFDM_CE_FR_SQS_G07__A 0x2C20030 +#define OFDM_CE_FR_SQS_G07__W 8 +#define OFDM_CE_FR_SQS_G07__M 0xFF +#define OFDM_CE_FR_SQS_G07__PRE 0xB + +#define OFDM_CE_FR_SQS_G08__A 0x2C20031 +#define OFDM_CE_FR_SQS_G08__W 8 +#define OFDM_CE_FR_SQS_G08__M 0xFF +#define OFDM_CE_FR_SQS_G08__PRE 0xB + +#define OFDM_CE_FR_SQS_G09__A 0x2C20032 +#define OFDM_CE_FR_SQS_G09__W 8 +#define OFDM_CE_FR_SQS_G09__M 0xFF +#define OFDM_CE_FR_SQS_G09__PRE 0xB + +#define OFDM_CE_FR_SQS_G10__A 0x2C20033 +#define OFDM_CE_FR_SQS_G10__W 8 +#define OFDM_CE_FR_SQS_G10__M 0xFF +#define OFDM_CE_FR_SQS_G10__PRE 0xB + +#define OFDM_CE_FR_SQS_G11__A 0x2C20034 +#define OFDM_CE_FR_SQS_G11__W 8 +#define OFDM_CE_FR_SQS_G11__M 0xFF +#define OFDM_CE_FR_SQS_G11__PRE 0xB + +#define OFDM_CE_FR_SQS_G12__A 0x2C20035 +#define OFDM_CE_FR_SQS_G12__W 8 +#define OFDM_CE_FR_SQS_G12__M 0xFF +#define OFDM_CE_FR_SQS_G12__PRE 0x5 + +#define OFDM_CE_FR_RIO_G00__A 0x2C20036 +#define OFDM_CE_FR_RIO_G00__W 9 +#define OFDM_CE_FR_RIO_G00__M 0x1FF +#define OFDM_CE_FR_RIO_G00__PRE 0x1FF + +#define OFDM_CE_FR_RIO_G01__A 0x2C20037 +#define OFDM_CE_FR_RIO_G01__W 9 +#define OFDM_CE_FR_RIO_G01__M 0x1FF +#define OFDM_CE_FR_RIO_G01__PRE 0x190 + +#define OFDM_CE_FR_RIO_G02__A 0x2C20038 +#define OFDM_CE_FR_RIO_G02__W 9 +#define OFDM_CE_FR_RIO_G02__M 0x1FF +#define OFDM_CE_FR_RIO_G02__PRE 0x10B + +#define OFDM_CE_FR_RIO_G03__A 0x2C20039 +#define OFDM_CE_FR_RIO_G03__W 9 +#define OFDM_CE_FR_RIO_G03__M 0x1FF +#define OFDM_CE_FR_RIO_G03__PRE 0xC8 + +#define OFDM_CE_FR_RIO_G04__A 0x2C2003A +#define OFDM_CE_FR_RIO_G04__W 9 +#define OFDM_CE_FR_RIO_G04__M 0x1FF +#define OFDM_CE_FR_RIO_G04__PRE 0xA0 + +#define OFDM_CE_FR_RIO_G05__A 0x2C2003B +#define OFDM_CE_FR_RIO_G05__W 9 +#define OFDM_CE_FR_RIO_G05__M 0x1FF +#define OFDM_CE_FR_RIO_G05__PRE 0x85 + +#define OFDM_CE_FR_RIO_G06__A 0x2C2003C +#define OFDM_CE_FR_RIO_G06__W 9 +#define OFDM_CE_FR_RIO_G06__M 0x1FF +#define OFDM_CE_FR_RIO_G06__PRE 0x72 + +#define OFDM_CE_FR_RIO_G07__A 0x2C2003D +#define OFDM_CE_FR_RIO_G07__W 9 +#define OFDM_CE_FR_RIO_G07__M 0x1FF +#define OFDM_CE_FR_RIO_G07__PRE 0x64 + +#define OFDM_CE_FR_RIO_G08__A 0x2C2003E +#define OFDM_CE_FR_RIO_G08__W 9 +#define OFDM_CE_FR_RIO_G08__M 0x1FF +#define OFDM_CE_FR_RIO_G08__PRE 0x59 + +#define OFDM_CE_FR_RIO_G09__A 0x2C2003F +#define OFDM_CE_FR_RIO_G09__W 9 +#define OFDM_CE_FR_RIO_G09__M 0x1FF +#define OFDM_CE_FR_RIO_G09__PRE 0x50 + +#define OFDM_CE_FR_RIO_G10__A 0x2C20040 +#define OFDM_CE_FR_RIO_G10__W 9 +#define OFDM_CE_FR_RIO_G10__M 0x1FF +#define OFDM_CE_FR_RIO_G10__PRE 0x49 +#define OFDM_CE_FR_MODE__A 0x2C20041 +#define OFDM_CE_FR_MODE__W 9 +#define OFDM_CE_FR_MODE__M 0x1FF +#define OFDM_CE_FR_MODE__PRE 0xDE + +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1 +#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0 + +#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2 +#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2 + +#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4 +#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4 + +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8 +#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8 + +#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4 +#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1 +#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10 +#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10 + +#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5 +#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1 +#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20 +#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0 + +#define OFDM_CE_FR_MODE_MID_MODE__B 6 +#define OFDM_CE_FR_MODE_MID_MODE__W 1 +#define OFDM_CE_FR_MODE_MID_MODE__M 0x40 +#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40 + +#define OFDM_CE_FR_MODE_NOISE_MODE__B 7 +#define OFDM_CE_FR_MODE_NOISE_MODE__W 1 +#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80 +#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80 + +#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8 +#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1 +#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100 +#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0 + + +#define OFDM_CE_FR_SQS_TRH__A 0x2C20042 +#define OFDM_CE_FR_SQS_TRH__W 8 +#define OFDM_CE_FR_SQS_TRH__M 0xFF +#define OFDM_CE_FR_SQS_TRH__PRE 0x80 + +#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043 +#define OFDM_CE_FR_RIO_GAIN__W 3 +#define OFDM_CE_FR_RIO_GAIN__M 0x7 +#define OFDM_CE_FR_RIO_GAIN__PRE 0x7 +#define OFDM_CE_FR_BYPASS__A 0x2C20044 +#define OFDM_CE_FR_BYPASS__W 10 +#define OFDM_CE_FR_BYPASS__M 0x3FF +#define OFDM_CE_FR_BYPASS__PRE 0x13B + +#define OFDM_CE_FR_BYPASS_RUN_IN__B 0 +#define OFDM_CE_FR_BYPASS_RUN_IN__W 4 +#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF +#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB + +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 +#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130 + +#define OFDM_CE_FR_BYPASS_TOTAL__B 9 +#define OFDM_CE_FR_BYPASS_TOTAL__W 1 +#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200 +#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0 + + +#define OFDM_CE_FR_PM_SET__A 0x2C20045 +#define OFDM_CE_FR_PM_SET__W 4 +#define OFDM_CE_FR_PM_SET__M 0xF +#define OFDM_CE_FR_PM_SET__PRE 0xD + +#define OFDM_CE_FR_ERR_SH__A 0x2C20046 +#define OFDM_CE_FR_ERR_SH__W 4 +#define OFDM_CE_FR_ERR_SH__M 0xF +#define OFDM_CE_FR_ERR_SH__PRE 0x4 + +#define OFDM_CE_FR_MAN_SH__A 0x2C20047 +#define OFDM_CE_FR_MAN_SH__W 4 +#define OFDM_CE_FR_MAN_SH__M 0xF +#define OFDM_CE_FR_MAN_SH__PRE 0x7 + +#define OFDM_CE_FR_TAP_SH__A 0x2C20048 +#define OFDM_CE_FR_TAP_SH__W 3 +#define OFDM_CE_FR_TAP_SH__M 0x7 +#define OFDM_CE_FR_TAP_SH__PRE 0x3 + +#define OFDM_CE_FR_CLIP__A 0x2C20049 +#define OFDM_CE_FR_CLIP__W 9 +#define OFDM_CE_FR_CLIP__M 0x1FF +#define OFDM_CE_FR_CLIP__PRE 0x49 + +#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A +#define OFDM_CE_FR_LEAK_UPD__W 3 +#define OFDM_CE_FR_LEAK_UPD__M 0x7 +#define OFDM_CE_FR_LEAK_UPD__PRE 0x0 + +#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B +#define OFDM_CE_FR_LEAK_SH__W 3 +#define OFDM_CE_FR_LEAK_SH__M 0x7 +#define OFDM_CE_FR_LEAK_SH__PRE 0x1 + + + +#define OFDM_CE_NE_RAM__A 0x2C30000 + + + +#define OFDM_CE_PB_RAM__A 0x2C40000 + + + + + +#define OFDM_CP_COMM_EXEC__A 0x2800000 +#define OFDM_CP_COMM_EXEC__W 3 +#define OFDM_CP_COMM_EXEC__M 0x7 +#define OFDM_CP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_COMM_EXEC_STEP 0x3 +#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_CP_COMM_STATE__A 0x2800001 +#define OFDM_CP_COMM_STATE__W 16 +#define OFDM_CP_COMM_STATE__M 0xFFFF +#define OFDM_CP_COMM_STATE__PRE 0x0 +#define OFDM_CP_COMM_MB__A 0x2800002 +#define OFDM_CP_COMM_MB__W 16 +#define OFDM_CP_COMM_MB__M 0xFFFF +#define OFDM_CP_COMM_MB__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ__A 0x2800004 +#define OFDM_CP_COMM_INT_REQ__W 16 +#define OFDM_CP_COMM_INT_REQ__M 0xFFFF +#define OFDM_CP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2 +#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_CP_COMM_INT_STA__A 0x2800005 +#define OFDM_CP_COMM_INT_STA__W 16 +#define OFDM_CP_COMM_INT_STA__M 0xFFFF +#define OFDM_CP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_COMM_INT_MSK__A 0x2800006 +#define OFDM_CP_COMM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_COMM_INT_STM__A 0x2800007 +#define OFDM_CP_COMM_INT_STM__W 16 +#define OFDM_CP_COMM_INT_STM__M 0xFFFF +#define OFDM_CP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000 +#define OFDM_CP_TOP_COMM_EXEC__W 3 +#define OFDM_CP_TOP_COMM_EXEC__M 0x7 +#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_CP_TOP_COMM_MB__A 0x2810002 +#define OFDM_CP_TOP_COMM_MB__W 3 +#define OFDM_CP_TOP_COMM_MB__M 0x7 +#define OFDM_CP_TOP_COMM_MB__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL__B 0 +#define OFDM_CP_TOP_COMM_MB_CTL__W 1 +#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_CP_TOP_COMM_MB_OBS__B 1 +#define OFDM_CP_TOP_COMM_MB_OBS__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0 +#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4 + +#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004 +#define OFDM_CP_TOP_COMM_INT_REQ__W 1 +#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005 +#define OFDM_CP_TOP_COMM_INT_STA__W 1 +#define OFDM_CP_TOP_COMM_INT_STA__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006 +#define OFDM_CP_TOP_COMM_INT_MSK__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0 + +#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007 +#define OFDM_CP_TOP_COMM_INT_STM__W 1 +#define OFDM_CP_TOP_COMM_INT_STM__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1 +#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0 + + +#define OFDM_CP_TOP_MODE_2K__A 0x2810010 +#define OFDM_CP_TOP_MODE_2K__W 1 +#define OFDM_CP_TOP_MODE_2K__M 0x1 +#define OFDM_CP_TOP_MODE_2K__PRE 0x0 + +#define OFDM_CP_TOP_INTERVAL__A 0x2810011 +#define OFDM_CP_TOP_INTERVAL__W 4 +#define OFDM_CP_TOP_INTERVAL__M 0xF +#define OFDM_CP_TOP_INTERVAL__PRE 0x5 +#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012 +#define OFDM_CP_TOP_DETECT_ENA__W 2 +#define OFDM_CP_TOP_DETECT_ENA__M 0x3 +#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1 +#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0 + +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2 +#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0 + +#define OFDM_CP_TOP_FIX__A 0x2810013 +#define OFDM_CP_TOP_FIX__W 4 +#define OFDM_CP_TOP_FIX__M 0xF +#define OFDM_CP_TOP_FIX__PRE 0xF + +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1 + +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2 + +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4 + +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0 +#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8 + +#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021 +#define OFDM_CP_TOP_BR_SMB_NR__W 4 +#define OFDM_CP_TOP_BR_SMB_NR__M 0xF +#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3 +#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4 +#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8 +#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0 + + +#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022 +#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2 +#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3 +#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0 + +#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023 +#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4 +#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF +#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8 + +#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024 +#define OFDM_CP_TOP_BR_STR_DEL__W 10 +#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF +#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA + +#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025 +#define OFDM_CP_TOP_BR_EXP_ADJ__W 5 +#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F +#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10 + +#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030 +#define OFDM_CP_TOP_RT_ANG_INC0__W 16 +#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF +#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0 + +#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031 +#define OFDM_CP_TOP_RT_ANG_INC1__W 8 +#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF +#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5 + +#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033 +#define OFDM_CP_TOP_RT_DETECT_TRH__W 2 +#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3 +#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3 + +#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1 +#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036 +#define OFDM_CP_TOP_RT_SPD_MOD__W 2 +#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3 +#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0 + +#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037 +#define OFDM_CP_TOP_RT_SPD_SMB__W 2 +#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3 +#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0 +#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038 +#define OFDM_CP_TOP_RT_CPD_MODE__W 3 +#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3 +#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4 +#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0 + + +#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7 +#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A +#define OFDM_CP_TOP_RT_CPD_BIN__W 5 +#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F +#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B +#define OFDM_CP_TOP_RT_CPD_MAX__W 4 +#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF +#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0 +#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C +#define OFDM_CP_TOP_RT_SUPR_VAL__W 2 +#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3 +#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1 +#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0 + +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2 +#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0 + + +#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D +#define OFDM_CP_TOP_RT_EXP_AVE__W 5 +#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F +#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0 + +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5 +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F +#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3 + +#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040 +#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8 +#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF +#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041 +#define OFDM_CP_TOP_AC_AVER_POW__W 8 +#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF +#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F + +#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042 +#define OFDM_CP_TOP_AC_MAX_POW__W 8 +#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF +#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A + +#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6 +#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F +#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31 + +#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5 +#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F +#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10 + +#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045 +#define OFDM_CP_TOP_AC_GAIN_MAN__W 16 +#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF +#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046 +#define OFDM_CP_TOP_AC_GAIN_EXP__W 5 +#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F +#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047 +#define OFDM_CP_TOP_AC_AMP_MODE__W 2 +#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3 +#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2 +#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2 + +#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048 +#define OFDM_CP_TOP_AC_AMP_FIX__W 14 +#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049 +#define OFDM_CP_TOP_AC_AMP_READ__W 14 +#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF +#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10 +#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF +#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0 + +#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00 +#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0 + + +#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A +#define OFDM_CP_TOP_AC_ANG_MODE__W 2 +#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3 +#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0 +#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1 +#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2 +#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3 + + +#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B +#define OFDM_CP_TOP_AC_ANG_OFFS__W 16 +#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0 + +#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C +#define OFDM_CP_TOP_AC_ANG_READ__W 16 +#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF +#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060 +#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062 +#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8 +#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0 + +#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8 +#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF +#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051 +#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5 +#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F +#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0 + + +#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15 +#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF +#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0 +#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053 +#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11 +#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF +#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400 +#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3 +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C +#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2 +#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0 + +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1 +#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0 + + + +#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000 + + + +#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000 + + + +#define OFDM_CP_DL_0_RAM__A 0x2840000 + + + +#define OFDM_CP_DL_1_RAM__A 0x2850000 + + + +#define OFDM_CP_DL_2_RAM__A 0x2860000 + + + + + +#define OFDM_EC_COMM_EXEC__A 0x3400000 +#define OFDM_EC_COMM_EXEC__W 3 +#define OFDM_EC_COMM_EXEC__M 0x7 +#define OFDM_EC_COMM_EXEC__PRE 0x0 +#define OFDM_EC_COMM_EXEC_STOP 0x0 +#define OFDM_EC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_COMM_EXEC_STEP 0x3 +#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EC_COMM_STATE__A 0x3400001 +#define OFDM_EC_COMM_STATE__W 16 +#define OFDM_EC_COMM_STATE__M 0xFFFF +#define OFDM_EC_COMM_STATE__PRE 0x0 +#define OFDM_EC_COMM_MB__A 0x3400002 +#define OFDM_EC_COMM_MB__W 16 +#define OFDM_EC_COMM_MB__M 0xFFFF +#define OFDM_EC_COMM_MB__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ__A 0x3400004 +#define OFDM_EC_COMM_INT_REQ__W 16 +#define OFDM_EC_COMM_INT_REQ__M 0xFFFF +#define OFDM_EC_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10 +#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20 +#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define OFDM_EC_COMM_INT_STA__A 0x3400005 +#define OFDM_EC_COMM_INT_STA__W 16 +#define OFDM_EC_COMM_INT_STA__M 0xFFFF +#define OFDM_EC_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_COMM_INT_MSK__A 0x3400006 +#define OFDM_EC_COMM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_COMM_INT_STM__A 0x3400007 +#define OFDM_EC_COMM_INT_STM__W 16 +#define OFDM_EC_COMM_INT_STM__M 0xFFFF +#define OFDM_EC_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EC_SB_COMM_EXEC__A 0x3410000 +#define OFDM_EC_SB_COMM_EXEC__W 3 +#define OFDM_EC_SB_COMM_EXEC__M 0x7 +#define OFDM_EC_SB_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SB_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SB_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SB_COMM_STATE__A 0x3410001 +#define OFDM_EC_SB_COMM_STATE__W 4 +#define OFDM_EC_SB_COMM_STATE__M 0xF +#define OFDM_EC_SB_COMM_STATE__PRE 0x0 +#define OFDM_EC_SB_COMM_MB__A 0x3410002 +#define OFDM_EC_SB_COMM_MB__W 2 +#define OFDM_EC_SB_COMM_MB__M 0x3 +#define OFDM_EC_SB_COMM_MB__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL__B 0 +#define OFDM_EC_SB_COMM_MB_CTL__W 1 +#define OFDM_EC_SB_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SB_COMM_MB_OBS__B 1 +#define OFDM_EC_SB_COMM_MB_OBS__W 1 +#define OFDM_EC_SB_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2 + + +#define OFDM_EC_SB_TR_MODE__A 0x3410010 +#define OFDM_EC_SB_TR_MODE__W 1 +#define OFDM_EC_SB_TR_MODE__M 0x1 +#define OFDM_EC_SB_TR_MODE__PRE 0x0 +#define OFDM_EC_SB_TR_MODE_8K 0x0 +#define OFDM_EC_SB_TR_MODE_2K 0x1 + + +#define OFDM_EC_SB_CONST__A 0x3410011 +#define OFDM_EC_SB_CONST__W 2 +#define OFDM_EC_SB_CONST__M 0x3 +#define OFDM_EC_SB_CONST__PRE 0x2 +#define OFDM_EC_SB_CONST_QPSK 0x0 +#define OFDM_EC_SB_CONST_16QAM 0x1 +#define OFDM_EC_SB_CONST_64QAM 0x2 + + +#define OFDM_EC_SB_ALPHA__A 0x3410012 +#define OFDM_EC_SB_ALPHA__W 3 +#define OFDM_EC_SB_ALPHA__M 0x7 +#define OFDM_EC_SB_ALPHA__PRE 0x0 +#define OFDM_EC_SB_ALPHA_NH 0x0 +#define OFDM_EC_SB_ALPHA_H1 0x1 +#define OFDM_EC_SB_ALPHA_H2 0x2 +#define OFDM_EC_SB_ALPHA_H4 0x3 + + +#define OFDM_EC_SB_PRIOR__A 0x3410013 +#define OFDM_EC_SB_PRIOR__W 1 +#define OFDM_EC_SB_PRIOR__M 0x1 +#define OFDM_EC_SB_PRIOR__PRE 0x0 +#define OFDM_EC_SB_PRIOR_HI 0x0 +#define OFDM_EC_SB_PRIOR_LO 0x1 + + +#define OFDM_EC_SB_CSI_HI__A 0x3410014 +#define OFDM_EC_SB_CSI_HI__W 5 +#define OFDM_EC_SB_CSI_HI__M 0x1F +#define OFDM_EC_SB_CSI_HI__PRE 0x18 +#define OFDM_EC_SB_CSI_HI_MAX 0x1F +#define OFDM_EC_SB_CSI_HI_MIN 0x0 +#define OFDM_EC_SB_CSI_HI_TAG 0x0 + + +#define OFDM_EC_SB_CSI_LO__A 0x3410015 +#define OFDM_EC_SB_CSI_LO__W 5 +#define OFDM_EC_SB_CSI_LO__M 0x1F +#define OFDM_EC_SB_CSI_LO__PRE 0xC +#define OFDM_EC_SB_CSI_LO_MAX 0x1F +#define OFDM_EC_SB_CSI_LO_MIN 0x0 +#define OFDM_EC_SB_CSI_LO_TAG 0x0 + + +#define OFDM_EC_SB_SMB_TGL__A 0x3410016 +#define OFDM_EC_SB_SMB_TGL__W 1 +#define OFDM_EC_SB_SMB_TGL__M 0x1 +#define OFDM_EC_SB_SMB_TGL__PRE 0x1 +#define OFDM_EC_SB_SMB_TGL_OFF 0x0 +#define OFDM_EC_SB_SMB_TGL_ON 0x1 + + +#define OFDM_EC_SB_SNR_HI__A 0x3410017 +#define OFDM_EC_SB_SNR_HI__W 7 +#define OFDM_EC_SB_SNR_HI__M 0x7F +#define OFDM_EC_SB_SNR_HI__PRE 0x7F +#define OFDM_EC_SB_SNR_HI_MAX 0x7F +#define OFDM_EC_SB_SNR_HI_MIN 0x0 +#define OFDM_EC_SB_SNR_HI_TAG 0x0 + + +#define OFDM_EC_SB_SNR_MID__A 0x3410018 +#define OFDM_EC_SB_SNR_MID__W 7 +#define OFDM_EC_SB_SNR_MID__M 0x7F +#define OFDM_EC_SB_SNR_MID__PRE 0x7F +#define OFDM_EC_SB_SNR_MID_MAX 0x7F +#define OFDM_EC_SB_SNR_MID_MIN 0x0 +#define OFDM_EC_SB_SNR_MID_TAG 0x0 + + +#define OFDM_EC_SB_SNR_LO__A 0x3410019 +#define OFDM_EC_SB_SNR_LO__W 7 +#define OFDM_EC_SB_SNR_LO__M 0x7F +#define OFDM_EC_SB_SNR_LO__PRE 0x7F +#define OFDM_EC_SB_SNR_LO_MAX 0x7F +#define OFDM_EC_SB_SNR_LO_MIN 0x0 +#define OFDM_EC_SB_SNR_LO_TAG 0x0 + + +#define OFDM_EC_SB_SCALE_MSB__A 0x341001A +#define OFDM_EC_SB_SCALE_MSB__W 6 +#define OFDM_EC_SB_SCALE_MSB__M 0x3F +#define OFDM_EC_SB_SCALE_MSB__PRE 0x30 +#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B +#define OFDM_EC_SB_SCALE_BIT2__W 6 +#define OFDM_EC_SB_SCALE_BIT2__M 0x3F +#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC +#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F + + +#define OFDM_EC_SB_SCALE_LSB__A 0x341001C +#define OFDM_EC_SB_SCALE_LSB__W 6 +#define OFDM_EC_SB_SCALE_LSB__M 0x3F +#define OFDM_EC_SB_SCALE_LSB__PRE 0x3 +#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F + + +#define OFDM_EC_SB_CSI_OFS0__A 0x341001D +#define OFDM_EC_SB_CSI_OFS0__W 4 +#define OFDM_EC_SB_CSI_OFS0__M 0xF +#define OFDM_EC_SB_CSI_OFS0__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS1__A 0x341001E +#define OFDM_EC_SB_CSI_OFS1__W 4 +#define OFDM_EC_SB_CSI_OFS1__M 0xF +#define OFDM_EC_SB_CSI_OFS1__PRE 0x1 + +#define OFDM_EC_SB_CSI_OFS2__A 0x341001F +#define OFDM_EC_SB_CSI_OFS2__W 4 +#define OFDM_EC_SB_CSI_OFS2__M 0xF +#define OFDM_EC_SB_CSI_OFS2__PRE 0x1 + +#define OFDM_EC_SB_MAX0__A 0x3410020 +#define OFDM_EC_SB_MAX0__W 6 +#define OFDM_EC_SB_MAX0__M 0x3F +#define OFDM_EC_SB_MAX0__PRE 0x3F + +#define OFDM_EC_SB_MAX1__A 0x3410021 +#define OFDM_EC_SB_MAX1__W 6 +#define OFDM_EC_SB_MAX1__M 0x3F +#define OFDM_EC_SB_MAX1__PRE 0x3F +#define OFDM_EC_SB_MAX1_INIT 0x3F + + +#define OFDM_EC_SB_MAX2__A 0x3410022 +#define OFDM_EC_SB_MAX2__W 6 +#define OFDM_EC_SB_MAX2__M 0x3F +#define OFDM_EC_SB_MAX2__PRE 0x3F + +#define OFDM_EC_SB_CSI_DIS__A 0x3410023 +#define OFDM_EC_SB_CSI_DIS__W 1 +#define OFDM_EC_SB_CSI_DIS__M 0x1 +#define OFDM_EC_SB_CSI_DIS__PRE 0x0 + + + +#define OFDM_EC_VD_COMM_EXEC__A 0x3420000 +#define OFDM_EC_VD_COMM_EXEC__W 3 +#define OFDM_EC_VD_COMM_EXEC__M 0x7 +#define OFDM_EC_VD_COMM_EXEC__PRE 0x0 +#define OFDM_EC_VD_COMM_EXEC_STOP 0x0 +#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_VD_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_VD_COMM_STATE__A 0x3420001 +#define OFDM_EC_VD_COMM_STATE__W 4 +#define OFDM_EC_VD_COMM_STATE__M 0xF +#define OFDM_EC_VD_COMM_STATE__PRE 0x0 +#define OFDM_EC_VD_COMM_MB__A 0x3420002 +#define OFDM_EC_VD_COMM_MB__W 2 +#define OFDM_EC_VD_COMM_MB__M 0x3 +#define OFDM_EC_VD_COMM_MB__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL__B 0 +#define OFDM_EC_VD_COMM_MB_CTL__W 1 +#define OFDM_EC_VD_COMM_MB_CTL__M 0x1 +#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_VD_COMM_MB_OBS__B 1 +#define OFDM_EC_VD_COMM_MB_OBS__W 1 +#define OFDM_EC_VD_COMM_MB_OBS__M 0x2 +#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003 +#define OFDM_EC_VD_COMM_INT_REQ__W 1 +#define OFDM_EC_VD_COMM_INT_REQ__M 0x1 +#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005 +#define OFDM_EC_VD_COMM_INT_STA__W 1 +#define OFDM_EC_VD_COMM_INT_STA__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006 +#define OFDM_EC_VD_COMM_INT_MSK__W 1 +#define OFDM_EC_VD_COMM_INT_MSK__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0 + +#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007 +#define OFDM_EC_VD_COMM_INT_STM__W 1 +#define OFDM_EC_VD_COMM_INT_STM__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1 +#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0 + + +#define OFDM_EC_VD_FORCE__A 0x3420010 +#define OFDM_EC_VD_FORCE__W 2 +#define OFDM_EC_VD_FORCE__M 0x3 +#define OFDM_EC_VD_FORCE__PRE 0x2 +#define OFDM_EC_VD_FORCE_FREE 0x0 +#define OFDM_EC_VD_FORCE_PROP 0x1 +#define OFDM_EC_VD_FORCE_FORCED 0x2 +#define OFDM_EC_VD_FORCE_FIXED 0x3 + + +#define OFDM_EC_VD_SET_CODERATE__A 0x3420011 +#define OFDM_EC_VD_SET_CODERATE__W 3 +#define OFDM_EC_VD_SET_CODERATE__M 0x7 +#define OFDM_EC_VD_SET_CODERATE__PRE 0x1 +#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012 +#define OFDM_EC_VD_REQ_SMB_CNT__W 16 +#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1 + +#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013 +#define OFDM_EC_VD_REQ_BIT_CNT__W 16 +#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF + +#define OFDM_EC_VD_RLK_ENA__A 0x3420014 +#define OFDM_EC_VD_RLK_ENA__W 1 +#define OFDM_EC_VD_RLK_ENA__M 0x1 +#define OFDM_EC_VD_RLK_ENA__PRE 0x1 +#define OFDM_EC_VD_RLK_ENA_OFF 0x0 +#define OFDM_EC_VD_RLK_ENA_ON 0x1 + + +#define OFDM_EC_VD_VAL__A 0x3420015 +#define OFDM_EC_VD_VAL__W 2 +#define OFDM_EC_VD_VAL__M 0x3 +#define OFDM_EC_VD_VAL__PRE 0x0 +#define OFDM_EC_VD_VAL_CODE 0x1 +#define OFDM_EC_VD_VAL_CNT 0x2 + + +#define OFDM_EC_VD_GET_CODERATE__A 0x3420016 +#define OFDM_EC_VD_GET_CODERATE__W 3 +#define OFDM_EC_VD_GET_CODERATE__M 0x7 +#define OFDM_EC_VD_GET_CODERATE__PRE 0x0 +#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0 +#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1 +#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2 +#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3 +#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4 + + +#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 +#define OFDM_EC_VD_ERR_BIT_CNT__W 16 +#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF + +#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 +#define OFDM_EC_VD_IN_BIT_CNT__W 16 +#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF +#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0 + +#define OFDM_EC_VD_STS__A 0x3420019 +#define OFDM_EC_VD_STS__W 1 +#define OFDM_EC_VD_STS__M 0x1 +#define OFDM_EC_VD_STS__PRE 0x0 +#define OFDM_EC_VD_STS_NO_LOCK 0x0 +#define OFDM_EC_VD_STS_IN_LOCK 0x1 + + +#define OFDM_EC_VD_RLK_CNT__A 0x342001A +#define OFDM_EC_VD_RLK_CNT__W 16 +#define OFDM_EC_VD_RLK_CNT__M 0xFFFF +#define OFDM_EC_VD_RLK_CNT__PRE 0x0 + + + +#define OFDM_EC_SY_COMM_EXEC__A 0x3430000 +#define OFDM_EC_SY_COMM_EXEC__W 2 +#define OFDM_EC_SY_COMM_EXEC__M 0x3 +#define OFDM_EC_SY_COMM_EXEC__PRE 0x0 +#define OFDM_EC_SY_COMM_EXEC_STOP 0x0 +#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2 +#define OFDM_EC_SY_COMM_EXEC_STEP 0x3 + +#define OFDM_EC_SY_COMM_MB__A 0x3430002 +#define OFDM_EC_SY_COMM_MB__W 2 +#define OFDM_EC_SY_COMM_MB__M 0x3 +#define OFDM_EC_SY_COMM_MB__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL__B 0 +#define OFDM_EC_SY_COMM_MB_CTL__W 1 +#define OFDM_EC_SY_COMM_MB_CTL__M 0x1 +#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1 +#define OFDM_EC_SY_COMM_MB_OBS__B 1 +#define OFDM_EC_SY_COMM_MB_OBS__W 1 +#define OFDM_EC_SY_COMM_MB_OBS__M 0x2 +#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0 +#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2 + +#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003 +#define OFDM_EC_SY_COMM_INT_REQ__W 1 +#define OFDM_EC_SY_COMM_INT_REQ__M 0x1 +#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005 +#define OFDM_EC_SY_COMM_INT_STA__W 3 +#define OFDM_EC_SY_COMM_INT_STA__M 0x7 +#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006 +#define OFDM_EC_SY_COMM_INT_MSK__W 3 +#define OFDM_EC_SY_COMM_INT_MSK__M 0x7 +#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007 +#define OFDM_EC_SY_COMM_INT_STM__W 3 +#define OFDM_EC_SY_COMM_INT_STM__M 0x7 +#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 + +#define OFDM_EC_SY_STATUS__A 0x3430010 +#define OFDM_EC_SY_STATUS__W 2 +#define OFDM_EC_SY_STATUS__M 0x3 +#define OFDM_EC_SY_STATUS__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0 +#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2 +#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3 +#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0 +#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1 +#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2 + + +#define OFDM_EC_SY_TIMEOUT__A 0x3430011 +#define OFDM_EC_SY_TIMEOUT__W 16 +#define OFDM_EC_SY_TIMEOUT__M 0xFFFF +#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98 + +#define OFDM_EC_SY_SYNC_LWM__A 0x3430012 +#define OFDM_EC_SY_SYNC_LWM__W 4 +#define OFDM_EC_SY_SYNC_LWM__M 0xF +#define OFDM_EC_SY_SYNC_LWM__PRE 0x2 + +#define OFDM_EC_SY_SYNC_AWM__A 0x3430013 +#define OFDM_EC_SY_SYNC_AWM__W 4 +#define OFDM_EC_SY_SYNC_AWM__M 0xF +#define OFDM_EC_SY_SYNC_AWM__PRE 0x3 + +#define OFDM_EC_SY_SYNC_HWM__A 0x3430014 +#define OFDM_EC_SY_SYNC_HWM__W 4 +#define OFDM_EC_SY_SYNC_HWM__M 0xF +#define OFDM_EC_SY_SYNC_HWM__PRE 0x5 + +#define OFDM_EC_SY_UNLOCK__A 0x3430015 +#define OFDM_EC_SY_UNLOCK__W 1 +#define OFDM_EC_SY_UNLOCK__M 0x1 +#define OFDM_EC_SY_UNLOCK__PRE 0x0 + + + +#define OFDM_EC_SB_BD0_RAM__A 0x3440000 + + + +#define OFDM_EC_SB_BD1_RAM__A 0x3450000 + + + +#define OFDM_EC_SB_SD_RAM__A 0x3460000 + + + +#define OFDM_EC_VD_RE_RAM__A 0x3470000 + + + +#define OFDM_EC_VD_TB0_RAM__A 0x3480000 + + + +#define OFDM_EC_VD_TB1_RAM__A 0x3490000 + + + +#define OFDM_EC_VD_TB2_RAM__A 0x34A0000 + + + +#define OFDM_EC_VD_TB3_RAM__A 0x34B0000 + + + + + +#define OFDM_EQ_COMM_EXEC__A 0x3000000 +#define OFDM_EQ_COMM_EXEC__W 3 +#define OFDM_EQ_COMM_EXEC__M 0x7 +#define OFDM_EQ_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_COMM_EXEC_STEP 0x3 +#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_EQ_COMM_STATE__A 0x3000001 +#define OFDM_EQ_COMM_STATE__W 16 +#define OFDM_EQ_COMM_STATE__M 0xFFFF +#define OFDM_EQ_COMM_STATE__PRE 0x0 +#define OFDM_EQ_COMM_MB__A 0x3000002 +#define OFDM_EQ_COMM_MB__W 16 +#define OFDM_EQ_COMM_MB__M 0xFFFF +#define OFDM_EQ_COMM_MB__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ__A 0x3000004 +#define OFDM_EQ_COMM_INT_REQ__W 16 +#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF +#define OFDM_EQ_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8 +#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0 + +#define OFDM_EQ_COMM_INT_STA__A 0x3000005 +#define OFDM_EQ_COMM_INT_STA__W 16 +#define OFDM_EQ_COMM_INT_STA__M 0xFFFF +#define OFDM_EQ_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_COMM_INT_MSK__A 0x3000006 +#define OFDM_EQ_COMM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM__A 0x3000007 +#define OFDM_EQ_COMM_INT_STM__W 16 +#define OFDM_EQ_COMM_INT_STM__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000 +#define OFDM_EQ_TOP_COMM_EXEC__W 3 +#define OFDM_EQ_TOP_COMM_EXEC__M 0x7 +#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001 +#define OFDM_EQ_TOP_COMM_STATE__W 4 +#define OFDM_EQ_TOP_COMM_STATE__M 0xF +#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB__A 0x3010002 +#define OFDM_EQ_TOP_COMM_MB__W 6 +#define OFDM_EQ_TOP_COMM_MB__M 0x3F +#define OFDM_EQ_TOP_COMM_MB__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL__B 0 +#define OFDM_EQ_TOP_COMM_MB_CTL__W 1 +#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_EQ_TOP_COMM_MB_OBS__B 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__W 1 +#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4 +#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30 + +#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004 +#define OFDM_EQ_TOP_COMM_INT_REQ__W 1 +#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005 +#define OFDM_EQ_TOP_COMM_INT_STA__W 2 +#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006 +#define OFDM_EQ_TOP_COMM_INT_MSK__W 2 +#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007 +#define OFDM_EQ_TOP_COMM_INT_STM__W 2 +#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3 +#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1 +#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2 +#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE__A 0x3010014 +#define OFDM_EQ_TOP_IS_MODE__W 4 +#define OFDM_EQ_TOP_IS_MODE__M 0xF +#define OFDM_EQ_TOP_IS_MODE__PRE 0x0 + +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4 + +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0 +#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8 + + +#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015 +#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10 +#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF +#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114 + +#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016 +#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5 +#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5 + +#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017 +#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5 +#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F +#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10 +#define OFDM_EQ_TOP_DV_MODE__A 0x301001E +#define OFDM_EQ_TOP_DV_MODE__W 4 +#define OFDM_EQ_TOP_DV_MODE__M 0xF +#define OFDM_EQ_TOP_DV_MODE__PRE 0xF + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1 + +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2 + +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4 + +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0 +#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8 + + +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16 +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF +#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE__A 0x3010028 +#define OFDM_EQ_TOP_SN_MODE__W 8 +#define OFDM_EQ_TOP_SN_MODE__M 0xFF +#define OFDM_EQ_TOP_SN_MODE__PRE 0x18 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4 + +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8 + +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10 + +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0 +#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20 + +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40 + +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0 +#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80 + + +#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029 +#define OFDM_EQ_TOP_SN_PFIX__W 8 +#define OFDM_EQ_TOP_SN_PFIX__M 0xFF +#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0 + +#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A +#define OFDM_EQ_TOP_SN_CEGAIN__W 8 +#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF +#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30 + +#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B +#define OFDM_EQ_TOP_SN_OFFSET__W 6 +#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F +#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39 + +#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C +#define OFDM_EQ_TOP_SN_NULLIFY__W 6 +#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F +#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0 +#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D +#define OFDM_EQ_TOP_SN_SQUASH__W 10 +#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF +#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6 +#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F +#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7 + +#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0 +#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032 +#define OFDM_EQ_TOP_RC_SEL_CAR__W 8 +#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF +#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1 + +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4 +#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6 + +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40 +#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60 + +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0 +#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80 + +#define OFDM_EQ_TOP_RC_STS__A 0x3010033 +#define OFDM_EQ_TOP_RC_STS__W 16 +#define OFDM_EQ_TOP_RC_STS__M 0xFFFF +#define OFDM_EQ_TOP_RC_STS__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_DIFF__B 0 +#define OFDM_EQ_TOP_RC_STS_DIFF__W 11 +#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF +#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0 + +#define OFDM_EQ_TOP_RC_STS_FIRST__B 11 +#define OFDM_EQ_TOP_RC_STS_FIRST__W 1 +#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800 +#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800 + +#define OFDM_EQ_TOP_RC_STS_SELEC__B 12 +#define OFDM_EQ_TOP_RC_STS_SELEC__W 1 +#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000 +#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0 +#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000 + +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000 + +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000 + +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0 +#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000 + + +#define OFDM_EQ_TOP_OT_CONST__A 0x3010046 +#define OFDM_EQ_TOP_OT_CONST__W 2 +#define OFDM_EQ_TOP_OT_CONST__M 0x3 +#define OFDM_EQ_TOP_OT_CONST__PRE 0x2 + +#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047 +#define OFDM_EQ_TOP_OT_ALPHA__W 2 +#define OFDM_EQ_TOP_OT_ALPHA__M 0x3 +#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0 + +#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048 +#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E + +#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049 +#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5 +#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F +#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F + +#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A +#define OFDM_EQ_TOP_OT_CSI_STEP__W 4 +#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF +#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B +#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8 +#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5 + +#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C +#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8 +#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF +#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B + +#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D +#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7 +#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0 + +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7 +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F +#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050 +#define OFDM_EQ_TOP_TD_TPS_INIT__W 1 +#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1 +#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0 +#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051 +#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16 +#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF +#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE +#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11 + + +#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052 +#define OFDM_EQ_TOP_TD_TPS_LEN__W 6 +#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17 +#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F + + +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2 +#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 +#define OFDM_EQ_TOP_TD_TPS_CONST__W 2 +#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0 +#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1 +#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 + + +#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055 +#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3 +#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2 +#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3 +#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 + + +#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058 +#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2 +#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0 +#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1 +#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2 +#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3 + + +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0 +#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1 + + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8 +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF +#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C +#define OFDM_EQ_TOP_TD_TPS_RSV__W 6 +#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F +#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0 + +#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D +#define OFDM_EQ_TOP_TD_TPS_BCH__W 14 +#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF +#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E +#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16 +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF +#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0 + +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4 +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF +#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0 + +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16 +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200 + +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10 +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF +#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F + + + + + +#define OFDM_FE_COMM_EXEC__A 0x2000000 +#define OFDM_FE_COMM_EXEC__W 3 +#define OFDM_FE_COMM_EXEC__M 0x7 +#define OFDM_FE_COMM_EXEC__PRE 0x0 +#define OFDM_FE_COMM_EXEC_STOP 0x0 +#define OFDM_FE_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_COMM_STATE__A 0x2000001 +#define OFDM_FE_COMM_STATE__W 16 +#define OFDM_FE_COMM_STATE__M 0xFFFF +#define OFDM_FE_COMM_STATE__PRE 0x0 +#define OFDM_FE_COMM_MB__A 0x2000002 +#define OFDM_FE_COMM_MB__W 16 +#define OFDM_FE_COMM_MB__M 0xFFFF +#define OFDM_FE_COMM_MB__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ__A 0x2000004 +#define OFDM_FE_COMM_INT_REQ__W 16 +#define OFDM_FE_COMM_INT_REQ__M 0xFFFF +#define OFDM_FE_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1 +#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0 + +#define OFDM_FE_COMM_INT_STA__A 0x2000005 +#define OFDM_FE_COMM_INT_STA__W 16 +#define OFDM_FE_COMM_INT_STA__M 0xFFFF +#define OFDM_FE_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_COMM_INT_MSK__A 0x2000006 +#define OFDM_FE_COMM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_COMM_INT_STM__A 0x2000007 +#define OFDM_FE_COMM_INT_STM__W 16 +#define OFDM_FE_COMM_INT_STM__M 0xFFFF +#define OFDM_FE_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_FE_CU_COMM_EXEC__A 0x2010000 +#define OFDM_FE_CU_COMM_EXEC__W 3 +#define OFDM_FE_CU_COMM_EXEC__M 0x7 +#define OFDM_FE_CU_COMM_EXEC__PRE 0x0 +#define OFDM_FE_CU_COMM_EXEC_STOP 0x0 +#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2 +#define OFDM_FE_CU_COMM_EXEC_STEP 0x3 + +#define OFDM_FE_CU_COMM_STATE__A 0x2010001 +#define OFDM_FE_CU_COMM_STATE__W 4 +#define OFDM_FE_CU_COMM_STATE__M 0xF +#define OFDM_FE_CU_COMM_STATE__PRE 0x0 +#define OFDM_FE_CU_COMM_MB__A 0x2010002 +#define OFDM_FE_CU_COMM_MB__W 2 +#define OFDM_FE_CU_COMM_MB__M 0x3 +#define OFDM_FE_CU_COMM_MB__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL__B 0 +#define OFDM_FE_CU_COMM_MB_CTL__W 1 +#define OFDM_FE_CU_COMM_MB_CTL__M 0x1 +#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1 +#define OFDM_FE_CU_COMM_MB_OBS__B 1 +#define OFDM_FE_CU_COMM_MB_OBS__W 1 +#define OFDM_FE_CU_COMM_MB_OBS__M 0x2 +#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0 +#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2 + +#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004 +#define OFDM_FE_CU_COMM_INT_REQ__W 1 +#define OFDM_FE_CU_COMM_INT_REQ__M 0x1 +#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005 +#define OFDM_FE_CU_COMM_INT_STA__W 4 +#define OFDM_FE_CU_COMM_INT_STA__M 0xF +#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006 +#define OFDM_FE_CU_COMM_INT_MSK__W 4 +#define OFDM_FE_CU_COMM_INT_MSK__M 0xF +#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007 +#define OFDM_FE_CU_COMM_INT_STM__W 4 +#define OFDM_FE_CU_COMM_INT_STM__M 0xF +#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1 +#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2 +#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4 +#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8 +#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0 + +#define OFDM_FE_CU_MODE__A 0x2010010 +#define OFDM_FE_CU_MODE__W 8 +#define OFDM_FE_CU_MODE__M 0xFF +#define OFDM_FE_CU_MODE__PRE 0x20 + +#define OFDM_FE_CU_MODE_FFT__B 0 +#define OFDM_FE_CU_MODE_FFT__W 1 +#define OFDM_FE_CU_MODE_FFT__M 0x1 +#define OFDM_FE_CU_MODE_FFT__PRE 0x0 +#define OFDM_FE_CU_MODE_FFT_M8K 0x0 +#define OFDM_FE_CU_MODE_FFT_M2K 0x1 + +#define OFDM_FE_CU_MODE_COR__B 1 +#define OFDM_FE_CU_MODE_COR__W 1 +#define OFDM_FE_CU_MODE_COR__M 0x2 +#define OFDM_FE_CU_MODE_COR__PRE 0x0 +#define OFDM_FE_CU_MODE_COR_OFF 0x0 +#define OFDM_FE_CU_MODE_COR_ON 0x2 + +#define OFDM_FE_CU_MODE_IFD__B 2 +#define OFDM_FE_CU_MODE_IFD__W 1 +#define OFDM_FE_CU_MODE_IFD__M 0x4 +#define OFDM_FE_CU_MODE_IFD__PRE 0x0 +#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0 +#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4 + +#define OFDM_FE_CU_MODE_SEL__B 3 +#define OFDM_FE_CU_MODE_SEL__W 1 +#define OFDM_FE_CU_MODE_SEL__M 0x8 +#define OFDM_FE_CU_MODE_SEL__PRE 0x0 +#define OFDM_FE_CU_MODE_SEL_COR 0x0 +#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8 + +#define OFDM_FE_CU_MODE_FES__B 4 +#define OFDM_FE_CU_MODE_FES__W 1 +#define OFDM_FE_CU_MODE_FES__M 0x10 +#define OFDM_FE_CU_MODE_FES__PRE 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0 +#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10 +#define OFDM_FE_CU_MODE_AVG__B 5 +#define OFDM_FE_CU_MODE_AVG__W 1 +#define OFDM_FE_CU_MODE_AVG__M 0x20 +#define OFDM_FE_CU_MODE_AVG__PRE 0x20 +#define OFDM_FE_CU_MODE_AVG_OFF 0x0 +#define OFDM_FE_CU_MODE_AVG_ON 0x20 +#define OFDM_FE_CU_MODE_SHF_ENA__B 6 +#define OFDM_FE_CU_MODE_SHF_ENA__W 1 +#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40 +#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0 +#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40 +#define OFDM_FE_CU_MODE_SHF_DIR__B 7 +#define OFDM_FE_CU_MODE_SHF_DIR__W 1 +#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80 +#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0 +#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80 + + +#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011 +#define OFDM_FE_CU_FRM_CNT_RST__W 15 +#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF + +#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012 +#define OFDM_FE_CU_FRM_CNT_STR__W 15 +#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E + +#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013 +#define OFDM_FE_CU_FRM_SMP_CNT__W 15 +#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF +#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0 + +#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014 +#define OFDM_FE_CU_FRM_SMB_CNT__W 16 +#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF +#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015 +#define OFDM_FE_CU_CMP_MAX_DAT__W 12 +#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016 +#define OFDM_FE_CU_CMP_MAX_ADR__W 10 +#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF +#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017 +#define OFDM_FE_CU_CMP_MAX_RE__W 12 +#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018 +#define OFDM_FE_CU_CMP_MAX_IM__W 12 +#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0 + +#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F +#define OFDM_FE_CU_BUF_NFC_DEL__W 14 +#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF +#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020 +#define OFDM_FE_CU_CTR_NFC_ICR__W 5 +#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F +#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1 + +#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021 +#define OFDM_FE_CU_CTR_NFC_OCR__W 15 +#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8 + +#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022 +#define OFDM_FE_CU_CTR_NFC_CNT__W 15 +#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF +#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0 + +#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023 +#define OFDM_FE_CU_CTR_NFC_STS__W 3 +#define OFDM_FE_CU_CTR_NFC_STS__M 0x7 +#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1 +#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2 +#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4 + + +#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024 +#define OFDM_FE_CU_DIV_NFC_REA__W 14 +#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0 + +#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025 +#define OFDM_FE_CU_DIV_NFC_IMA__W 14 +#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF +#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0 + +#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026 +#define OFDM_FE_CU_FRM_CNT_UPD__W 15 +#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF +#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF + +#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027 +#define OFDM_FE_CU_DIV_NFC_CLP__W 2 +#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3 +#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2 +#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3 + + +#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028 +#define OFDM_FE_CU_CMP_MAX_32__W 12 +#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029 +#define OFDM_FE_CU_CMP_MAX_16__W 12 +#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A +#define OFDM_FE_CU_CMP_MAX_8__W 12 +#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0 + +#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B +#define OFDM_FE_CU_CMP_MAX_4__W 12 +#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF +#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C +#define OFDM_FE_CU_CMP_SUM_32_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D +#define OFDM_FE_CU_CMP_SUM_32_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E +#define OFDM_FE_CU_CMP_SUM_16_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F +#define OFDM_FE_CU_CMP_SUM_16_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030 +#define OFDM_FE_CU_CMP_SUM_8_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031 +#define OFDM_FE_CU_CMP_SUM_8_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032 +#define OFDM_FE_CU_CMP_SUM_4_RE__W 14 +#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0 + +#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033 +#define OFDM_FE_CU_CMP_SUM_4_IM__W 14 +#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF +#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0 + + + +#define OFDM_FE_CU_BUF_RAM__A 0x2020000 + + + +#define OFDM_FE_CU_CMP_RAM__A 0x2030000 + + + + + +#define OFDM_FT_COMM_EXEC__A 0x2400000 +#define OFDM_FT_COMM_EXEC__W 3 +#define OFDM_FT_COMM_EXEC__M 0x7 +#define OFDM_FT_COMM_EXEC__PRE 0x0 +#define OFDM_FT_COMM_EXEC_STOP 0x0 +#define OFDM_FT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_COMM_EXEC_STEP 0x3 +#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_FT_COMM_STATE__A 0x2400001 +#define OFDM_FT_COMM_STATE__W 16 +#define OFDM_FT_COMM_STATE__M 0xFFFF +#define OFDM_FT_COMM_STATE__PRE 0x0 +#define OFDM_FT_COMM_MB__A 0x2400002 +#define OFDM_FT_COMM_MB__W 16 +#define OFDM_FT_COMM_MB__M 0xFFFF +#define OFDM_FT_COMM_MB__PRE 0x0 + + + +#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000 +#define OFDM_FT_TOP_COMM_EXEC__W 3 +#define OFDM_FT_TOP_COMM_EXEC__M 0x7 +#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0 +#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0 +#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1 +#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2 +#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3 + +#define OFDM_FT_TOP_COMM_MB__A 0x2410002 +#define OFDM_FT_TOP_COMM_MB__W 2 +#define OFDM_FT_TOP_COMM_MB__M 0x3 +#define OFDM_FT_TOP_COMM_MB__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL__B 0 +#define OFDM_FT_TOP_COMM_MB_CTL__W 1 +#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1 +#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1 +#define OFDM_FT_TOP_COMM_MB_OBS__B 1 +#define OFDM_FT_TOP_COMM_MB_OBS__W 1 +#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2 +#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0 +#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2 + + +#define OFDM_FT_TOP_MODE_2K__A 0x2410010 +#define OFDM_FT_TOP_MODE_2K__W 1 +#define OFDM_FT_TOP_MODE_2K__M 0x1 +#define OFDM_FT_TOP_MODE_2K__PRE 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0 +#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1 + + +#define OFDM_FT_TOP_NORM_OFF__A 0x2410016 +#define OFDM_FT_TOP_NORM_OFF__W 4 +#define OFDM_FT_TOP_NORM_OFF__M 0xF +#define OFDM_FT_TOP_NORM_OFF__PRE 0x2 + + + +#define OFDM_FT_0TO2_0_RAM__A 0x2420000 + + + +#define OFDM_FT_0TO2_1_RAM__A 0x2430000 + + + +#define OFDM_FT_0TO2_2_RAM__A 0x2440000 + + + +#define OFDM_FT_3TO7_0_RAM__A 0x2450000 + + + +#define OFDM_FT_3TO7_1_RAM__A 0x2460000 + + + + + +#define OFDM_LC_COMM_EXEC__A 0x3800000 +#define OFDM_LC_COMM_EXEC__W 3 +#define OFDM_LC_COMM_EXEC__M 0x7 +#define OFDM_LC_COMM_EXEC__PRE 0x0 +#define OFDM_LC_COMM_EXEC_STOP 0x0 +#define OFDM_LC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_COMM_EXEC_STEP 0x3 +#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_LC_COMM_STATE__A 0x3800001 +#define OFDM_LC_COMM_STATE__W 16 +#define OFDM_LC_COMM_STATE__M 0xFFFF +#define OFDM_LC_COMM_STATE__PRE 0x0 +#define OFDM_LC_COMM_MB__A 0x3800002 +#define OFDM_LC_COMM_MB__W 16 +#define OFDM_LC_COMM_MB__M 0xFFFF +#define OFDM_LC_COMM_MB__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ__A 0x3800004 +#define OFDM_LC_COMM_INT_REQ__W 16 +#define OFDM_LC_COMM_INT_REQ__M 0xFFFF +#define OFDM_LC_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40 +#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_LC_COMM_INT_STA__A 0x3800005 +#define OFDM_LC_COMM_INT_STA__W 16 +#define OFDM_LC_COMM_INT_STA__M 0xFFFF +#define OFDM_LC_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_COMM_INT_MSK__A 0x3800006 +#define OFDM_LC_COMM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_COMM_INT_STM__A 0x3800007 +#define OFDM_LC_COMM_INT_STM__W 16 +#define OFDM_LC_COMM_INT_STM__M 0xFFFF +#define OFDM_LC_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_LC_CT_COMM_EXEC__A 0x3810000 +#define OFDM_LC_CT_COMM_EXEC__W 3 +#define OFDM_LC_CT_COMM_EXEC__M 0x7 +#define OFDM_LC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_LC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_LC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_LC_CT_COMM_STATE__A 0x3810001 +#define OFDM_LC_CT_COMM_STATE__W 10 +#define OFDM_LC_CT_COMM_STATE__M 0x3FF +#define OFDM_LC_CT_COMM_STATE__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004 +#define OFDM_LC_CT_COMM_INT_REQ__W 1 +#define OFDM_LC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005 +#define OFDM_LC_CT_COMM_INT_STA__W 1 +#define OFDM_LC_CT_COMM_INT_STA__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006 +#define OFDM_LC_CT_COMM_INT_MSK__W 1 +#define OFDM_LC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007 +#define OFDM_LC_CT_COMM_INT_STM__W 1 +#define OFDM_LC_CT_COMM_INT_STM__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_LC_CT_CTL_STK_0__A 0x3810010 +#define OFDM_LC_CT_CTL_STK_0__W 10 +#define OFDM_LC_CT_CTL_STK_0__M 0x3FF +#define OFDM_LC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_1__A 0x3810011 +#define OFDM_LC_CT_CTL_STK_1__W 10 +#define OFDM_LC_CT_CTL_STK_1__M 0x3FF +#define OFDM_LC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_2__A 0x3810012 +#define OFDM_LC_CT_CTL_STK_2__W 10 +#define OFDM_LC_CT_CTL_STK_2__M 0x3FF +#define OFDM_LC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_LC_CT_CTL_STK_3__A 0x3810013 +#define OFDM_LC_CT_CTL_STK_3__W 10 +#define OFDM_LC_CT_CTL_STK_3__M 0x3FF +#define OFDM_LC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F +#define OFDM_LC_CT_CTL_BPT_IDX__W 1 +#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_LC_CT_CTL_BPT__A 0x3810020 +#define OFDM_LC_CT_CTL_BPT__W 10 +#define OFDM_LC_CT_CTL_BPT__M 0x3FF +#define OFDM_LC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_LC_RA_RAM__A 0x3820000 + + + + +#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002 +#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004 +#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006 +#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0 + +#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007 +#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12 +#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF +#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0 + + + + + + + +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16 +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A +#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16 +#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16 +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16 +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010 +#define OFDM_LC_RA_RAM_MODE_2K__W 16 +#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011 +#define OFDM_LC_RA_RAM_MODE_GUARD__W 16 +#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0 +#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1 +#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2 +#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3 + +#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012 +#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16 +#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000 +#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0 + +#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014 +#define OFDM_LC_RA_RAM_RC_STS__W 16 +#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF +#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16 +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16 +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16 +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16 +#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16 +#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16 +#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF +#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E +#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16 +#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF +#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16 +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF +#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0 + + + + + +#define OFDM_SC_COMM_EXEC__A 0x3C00000 +#define OFDM_SC_COMM_EXEC__W 3 +#define OFDM_SC_COMM_EXEC__M 0x7 +#define OFDM_SC_COMM_EXEC__PRE 0x0 +#define OFDM_SC_COMM_EXEC_STOP 0x0 +#define OFDM_SC_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_COMM_EXEC_STEP 0x3 +#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4 +#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6 + +#define OFDM_SC_COMM_STATE__A 0x3C00001 +#define OFDM_SC_COMM_STATE__W 16 +#define OFDM_SC_COMM_STATE__M 0xFFFF +#define OFDM_SC_COMM_STATE__PRE 0x0 +#define OFDM_SC_COMM_MB__A 0x3C00002 +#define OFDM_SC_COMM_MB__W 16 +#define OFDM_SC_COMM_MB__M 0xFFFF +#define OFDM_SC_COMM_MB__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ__A 0x3C00004 +#define OFDM_SC_COMM_INT_REQ__W 16 +#define OFDM_SC_COMM_INT_REQ__M 0xFFFF +#define OFDM_SC_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80 +#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0 + +#define OFDM_SC_COMM_INT_STA__A 0x3C00005 +#define OFDM_SC_COMM_INT_STA__W 16 +#define OFDM_SC_COMM_INT_STA__M 0xFFFF +#define OFDM_SC_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_COMM_INT_MSK__A 0x3C00006 +#define OFDM_SC_COMM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_COMM_INT_STM__A 0x3C00007 +#define OFDM_SC_COMM_INT_STM__W 16 +#define OFDM_SC_COMM_INT_STM__M 0xFFFF +#define OFDM_SC_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0 +#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16 +#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF +#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0 + + + +#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000 +#define OFDM_SC_CT_COMM_EXEC__W 3 +#define OFDM_SC_CT_COMM_EXEC__M 0x7 +#define OFDM_SC_CT_COMM_EXEC__PRE 0x0 +#define OFDM_SC_CT_COMM_EXEC_STOP 0x0 +#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1 +#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2 +#define OFDM_SC_CT_COMM_EXEC_STEP 0x3 + + +#define OFDM_SC_CT_COMM_STATE__A 0x3C10001 +#define OFDM_SC_CT_COMM_STATE__W 10 +#define OFDM_SC_CT_COMM_STATE__M 0x3FF +#define OFDM_SC_CT_COMM_STATE__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004 +#define OFDM_SC_CT_COMM_INT_REQ__W 1 +#define OFDM_SC_CT_COMM_INT_REQ__M 0x1 +#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005 +#define OFDM_SC_CT_COMM_INT_STA__W 1 +#define OFDM_SC_CT_COMM_INT_STA__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006 +#define OFDM_SC_CT_COMM_INT_MSK__W 1 +#define OFDM_SC_CT_COMM_INT_MSK__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0 + +#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007 +#define OFDM_SC_CT_COMM_INT_STM__W 1 +#define OFDM_SC_CT_COMM_INT_STM__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1 +#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0 + + +#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010 +#define OFDM_SC_CT_CTL_STK_0__W 10 +#define OFDM_SC_CT_CTL_STK_0__M 0x3FF +#define OFDM_SC_CT_CTL_STK_0__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011 +#define OFDM_SC_CT_CTL_STK_1__W 10 +#define OFDM_SC_CT_CTL_STK_1__M 0x3FF +#define OFDM_SC_CT_CTL_STK_1__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012 +#define OFDM_SC_CT_CTL_STK_2__W 10 +#define OFDM_SC_CT_CTL_STK_2__M 0x3FF +#define OFDM_SC_CT_CTL_STK_2__PRE 0x0 + +#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013 +#define OFDM_SC_CT_CTL_STK_3__W 10 +#define OFDM_SC_CT_CTL_STK_3__M 0x3FF +#define OFDM_SC_CT_CTL_STK_3__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F +#define OFDM_SC_CT_CTL_BPT_IDX__W 1 +#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1 +#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0 + +#define OFDM_SC_CT_CTL_BPT__A 0x3C10020 +#define OFDM_SC_CT_CTL_BPT__W 13 +#define OFDM_SC_CT_CTL_BPT__M 0x1FFF +#define OFDM_SC_CT_CTL_BPT__PRE 0x0 + + + +#define OFDM_SC_RA_RAM__A 0x3C20000 + + + + +#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000 +#define OFDM_SC_IF_RAM_TRP_RST_0__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001 +#define OFDM_SC_IF_RAM_TRP_RST_1__W 12 +#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12 +#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004 +#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0 + +#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005 +#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12 +#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF +#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE +#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12 +#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0 + +#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12 +#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF +#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0 + + + + + + + +#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 +#define OFDM_SC_RA_RAM_PARAM0__W 16 +#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0 +#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 +#define OFDM_SC_RA_RAM_PARAM1__W 16 +#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF +#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 +#define OFDM_SC_RA_RAM_CMD_ADDR__W 16 +#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD__A 0x3C20043 +#define OFDM_SC_RA_RAM_CMD__W 16 +#define OFDM_SC_RA_RAM_CMD__M 0xFFFF +#define OFDM_SC_RA_RAM_CMD__PRE 0x0 +#define OFDM_SC_RA_RAM_CMD_NULL 0x0 +#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 +#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 +#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define OFDM_SC_RA_RAM_CMD_MAX 0x9 +#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4 + +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16 +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16 +#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046 +#define OFDM_SC_RA_RAM_SW_EVENT__W 14 +#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF +#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 +#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0 + +#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047 +#define OFDM_SC_RA_RAM_LOCKTRACK__W 16 +#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4 +#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5 +#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7 +#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8 +#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9 + +#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 +#define OFDM_SC_RA_RAM_OP_PARAM__W 13 +#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF +#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049 +#define OFDM_SC_RA_RAM_OP_AUTO__W 6 +#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F +#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 +#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0 + +#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A +#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16 +#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 + +#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B +#define OFDM_SC_RA_RAM_LOCK__W 4 +#define OFDM_SC_RA_RAM_LOCK__M 0xF +#define OFDM_SC_RA_RAM_LOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_FEC__B 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__W 1 +#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 +#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2 +#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1 +#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 +#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0 + +#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C +#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5 +#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10 +#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10 + +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F +#define OFDM_SC_RA_RAM_ECHO_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF +#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 +#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400 + +#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 +#define OFDM_SC_RA_RAM_CONFIG__W 16 +#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF +#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14 +#define OFDM_SC_RA_RAM_CONFIG_ID__B 0 +#define OFDM_SC_RA_RAM_CONFIG_ID__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1 +#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 +#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 +#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0 + +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16 +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F +#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16 +#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16 +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16 +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF +#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C +#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6 +#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D +#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16 +#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C +#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E +#define OFDM_SC_RA_RAM_STATUS__W 16 +#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF +#define OFDM_SC_RA_RAM_STATUS__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16 +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080 +#define OFDM_SC_RA_RAM_TIMER__W 16 +#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF +#define OFDM_SC_RA_RAM_TIMER__PRE 0x0 +#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081 +#define OFDM_SC_RA_RAM_FI_OFFSET__W 16 +#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082 +#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16 +#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16 +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF +#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640 +#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E +#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F +#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16 +#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16 +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF +#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16 +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16 +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400 + +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14 +#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0 +#define OFDM_SC_RA_RAM_IR_FREQ__W 16 +#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 +#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400 + +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16 +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16 +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC +#define OFDM_SC_RA_RAM_BAND__W 16 +#define OFDM_SC_RA_RAM_BAND__M 0xFFFF +#define OFDM_SC_RA_RAM_BAND__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4 +#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF +#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 +#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0 + +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16 +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B +#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0 +#define OFDM_SC_RA_RAM_REG_0__W 16 +#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_0__PRE 0x0 +#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1 +#define OFDM_SC_RA_RAM_REG_1__W 16 +#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF +#define OFDM_SC_RA_RAM_REG_1__PRE 0x0 +#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2 +#define OFDM_SC_RA_RAM_BREAK__W 16 +#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF +#define OFDM_SC_RA_RAM_BREAK__PRE 0x0 +#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3 +#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16 +#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF +#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0 +#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4 +#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5 +#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16 +#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16 +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF +#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16 +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF +#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F + +#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9 +#define OFDM_SC_RA_RAM_LC_CP__W 16 +#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1 +#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA +#define OFDM_SC_RA_RAM_LC_DIFF__W 16 +#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF +#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16 +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0 + +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16 +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF +#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38 +#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE +#define OFDM_SC_RA_RAM_RELOCK__W 16 +#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF +#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16 +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF +#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149 +#define OFDM_SC_RA_RAM_NF_PREPOST__W 16 +#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A +#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16 +#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B +#define OFDM_SC_RA_RAM_NF_START__W 16 +#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_START__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C +#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D +#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16 +#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F +#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16 +#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16 +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF +#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16 +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF +#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0 + + + + + +#define QAM_COMM_EXEC__A 0x1400000 +#define QAM_COMM_EXEC__W 2 +#define QAM_COMM_EXEC__M 0x3 +#define QAM_COMM_EXEC__PRE 0x0 +#define QAM_COMM_EXEC_STOP 0x0 +#define QAM_COMM_EXEC_ACTIVE 0x1 +#define QAM_COMM_EXEC_HOLD 0x2 + +#define QAM_COMM_MB__A 0x1400002 +#define QAM_COMM_MB__W 16 +#define QAM_COMM_MB__M 0xFFFF +#define QAM_COMM_MB__PRE 0x0 +#define QAM_COMM_INT_REQ__A 0x1400003 +#define QAM_COMM_INT_REQ__W 16 +#define QAM_COMM_INT_REQ__M 0xFFFF +#define QAM_COMM_INT_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SL_REQ__B 0 +#define QAM_COMM_INT_REQ_SL_REQ__W 1 +#define QAM_COMM_INT_REQ_SL_REQ__M 0x1 +#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_LC_REQ__B 1 +#define QAM_COMM_INT_REQ_LC_REQ__W 1 +#define QAM_COMM_INT_REQ_LC_REQ__M 0x2 +#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_VD_REQ__B 2 +#define QAM_COMM_INT_REQ_VD_REQ__W 1 +#define QAM_COMM_INT_REQ_VD_REQ__M 0x4 +#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0 + +#define QAM_COMM_INT_REQ_SY_REQ__B 3 +#define QAM_COMM_INT_REQ_SY_REQ__W 1 +#define QAM_COMM_INT_REQ_SY_REQ__M 0x8 +#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0 + +#define QAM_COMM_INT_STA__A 0x1400005 +#define QAM_COMM_INT_STA__W 16 +#define QAM_COMM_INT_STA__M 0xFFFF +#define QAM_COMM_INT_STA__PRE 0x0 +#define QAM_COMM_INT_MSK__A 0x1400006 +#define QAM_COMM_INT_MSK__W 16 +#define QAM_COMM_INT_MSK__M 0xFFFF +#define QAM_COMM_INT_MSK__PRE 0x0 +#define QAM_COMM_INT_STM__A 0x1400007 +#define QAM_COMM_INT_STM__W 16 +#define QAM_COMM_INT_STM__M 0xFFFF +#define QAM_COMM_INT_STM__PRE 0x0 + + + +#define QAM_TOP_COMM_EXEC__A 0x1410000 +#define QAM_TOP_COMM_EXEC__W 2 +#define QAM_TOP_COMM_EXEC__M 0x3 +#define QAM_TOP_COMM_EXEC__PRE 0x0 +#define QAM_TOP_COMM_EXEC_STOP 0x0 +#define QAM_TOP_COMM_EXEC_ACTIVE 0x1 +#define QAM_TOP_COMM_EXEC_HOLD 0x2 + + +#define QAM_TOP_ANNEX__A 0x1410010 +#define QAM_TOP_ANNEX__W 2 +#define QAM_TOP_ANNEX__M 0x3 +#define QAM_TOP_ANNEX__PRE 0x0 +#define QAM_TOP_ANNEX_A 0x0 +#define QAM_TOP_ANNEX_B 0x1 +#define QAM_TOP_ANNEX_C 0x2 +#define QAM_TOP_ANNEX_D 0x3 + + +#define QAM_TOP_CONSTELLATION__A 0x1410011 +#define QAM_TOP_CONSTELLATION__W 3 +#define QAM_TOP_CONSTELLATION__M 0x7 +#define QAM_TOP_CONSTELLATION__PRE 0x5 +#define QAM_TOP_CONSTELLATION_NONE 0x0 +#define QAM_TOP_CONSTELLATION_QPSK 0x1 +#define QAM_TOP_CONSTELLATION_QAM8 0x2 +#define QAM_TOP_CONSTELLATION_QAM16 0x3 +#define QAM_TOP_CONSTELLATION_QAM32 0x4 +#define QAM_TOP_CONSTELLATION_QAM64 0x5 +#define QAM_TOP_CONSTELLATION_QAM128 0x6 +#define QAM_TOP_CONSTELLATION_QAM256 0x7 + + + +#define QAM_FQ_COMM_EXEC__A 0x1420000 +#define QAM_FQ_COMM_EXEC__W 2 +#define QAM_FQ_COMM_EXEC__M 0x3 +#define QAM_FQ_COMM_EXEC__PRE 0x0 +#define QAM_FQ_COMM_EXEC_STOP 0x0 +#define QAM_FQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_FQ_COMM_EXEC_HOLD 0x2 + +#define QAM_FQ_MODE__A 0x1420010 +#define QAM_FQ_MODE__W 3 +#define QAM_FQ_MODE__M 0x7 +#define QAM_FQ_MODE__PRE 0x0 + +#define QAM_FQ_MODE_TAPRESET__B 0 +#define QAM_FQ_MODE_TAPRESET__W 1 +#define QAM_FQ_MODE_TAPRESET__M 0x1 +#define QAM_FQ_MODE_TAPRESET__PRE 0x0 +#define QAM_FQ_MODE_TAPRESET_RST 0x1 + +#define QAM_FQ_MODE_TAPLMS__B 1 +#define QAM_FQ_MODE_TAPLMS__W 1 +#define QAM_FQ_MODE_TAPLMS__M 0x2 +#define QAM_FQ_MODE_TAPLMS__PRE 0x0 +#define QAM_FQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_FQ_MODE_TAPDRAIN__B 2 +#define QAM_FQ_MODE_TAPDRAIN__W 1 +#define QAM_FQ_MODE_TAPDRAIN__M 0x4 +#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4 + + +#define QAM_FQ_MU_FACTOR__A 0x1420011 +#define QAM_FQ_MU_FACTOR__W 3 +#define QAM_FQ_MU_FACTOR__M 0x7 +#define QAM_FQ_MU_FACTOR__PRE 0x0 + +#define QAM_FQ_LA_FACTOR__A 0x1420012 +#define QAM_FQ_LA_FACTOR__W 4 +#define QAM_FQ_LA_FACTOR__M 0xF +#define QAM_FQ_LA_FACTOR__PRE 0xC +#define QAM_FQ_CENTTAP_IDX__A 0x1420016 +#define QAM_FQ_CENTTAP_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_IDX_IDX__B 0 +#define QAM_FQ_CENTTAP_IDX_IDX__W 5 +#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F +#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13 + +#define QAM_FQ_CENTTAP_VALUE__A 0x1420017 +#define QAM_FQ_CENTTAP_VALUE__W 12 +#define QAM_FQ_CENTTAP_VALUE__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE__PRE 0x600 + +#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 +#define QAM_FQ_CENTTAP_VALUE_TAP__W 12 +#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF +#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL0__A 0x1420020 +#define QAM_FQ_TAP_RE_EL0__W 12 +#define QAM_FQ_TAP_RE_EL0__M 0xFFF +#define QAM_FQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL0_TAP__B 0 +#define QAM_FQ_TAP_RE_EL0_TAP__W 12 +#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0__A 0x1420021 +#define QAM_FQ_TAP_IM_EL0__W 12 +#define QAM_FQ_TAP_IM_EL0__M 0xFFF +#define QAM_FQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL0_TAP__B 0 +#define QAM_FQ_TAP_IM_EL0_TAP__W 12 +#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1__A 0x1420022 +#define QAM_FQ_TAP_RE_EL1__W 12 +#define QAM_FQ_TAP_RE_EL1__M 0xFFF +#define QAM_FQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL1_TAP__B 0 +#define QAM_FQ_TAP_RE_EL1_TAP__W 12 +#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1__A 0x1420023 +#define QAM_FQ_TAP_IM_EL1__W 12 +#define QAM_FQ_TAP_IM_EL1__M 0xFFF +#define QAM_FQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL1_TAP__B 0 +#define QAM_FQ_TAP_IM_EL1_TAP__W 12 +#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2__A 0x1420024 +#define QAM_FQ_TAP_RE_EL2__W 12 +#define QAM_FQ_TAP_RE_EL2__M 0xFFF +#define QAM_FQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL2_TAP__B 0 +#define QAM_FQ_TAP_RE_EL2_TAP__W 12 +#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2__A 0x1420025 +#define QAM_FQ_TAP_IM_EL2__W 12 +#define QAM_FQ_TAP_IM_EL2__M 0xFFF +#define QAM_FQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL2_TAP__B 0 +#define QAM_FQ_TAP_IM_EL2_TAP__W 12 +#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3__A 0x1420026 +#define QAM_FQ_TAP_RE_EL3__W 12 +#define QAM_FQ_TAP_RE_EL3__M 0xFFF +#define QAM_FQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL3_TAP__B 0 +#define QAM_FQ_TAP_RE_EL3_TAP__W 12 +#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3__A 0x1420027 +#define QAM_FQ_TAP_IM_EL3__W 12 +#define QAM_FQ_TAP_IM_EL3__M 0xFFF +#define QAM_FQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL3_TAP__B 0 +#define QAM_FQ_TAP_IM_EL3_TAP__W 12 +#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4__A 0x1420028 +#define QAM_FQ_TAP_RE_EL4__W 12 +#define QAM_FQ_TAP_RE_EL4__M 0xFFF +#define QAM_FQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL4_TAP__B 0 +#define QAM_FQ_TAP_RE_EL4_TAP__W 12 +#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4__A 0x1420029 +#define QAM_FQ_TAP_IM_EL4__W 12 +#define QAM_FQ_TAP_IM_EL4__M 0xFFF +#define QAM_FQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL4_TAP__B 0 +#define QAM_FQ_TAP_IM_EL4_TAP__W 12 +#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5__A 0x142002A +#define QAM_FQ_TAP_RE_EL5__W 12 +#define QAM_FQ_TAP_RE_EL5__M 0xFFF +#define QAM_FQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL5_TAP__B 0 +#define QAM_FQ_TAP_RE_EL5_TAP__W 12 +#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5__A 0x142002B +#define QAM_FQ_TAP_IM_EL5__W 12 +#define QAM_FQ_TAP_IM_EL5__M 0xFFF +#define QAM_FQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL5_TAP__B 0 +#define QAM_FQ_TAP_IM_EL5_TAP__W 12 +#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6__A 0x142002C +#define QAM_FQ_TAP_RE_EL6__W 12 +#define QAM_FQ_TAP_RE_EL6__M 0xFFF +#define QAM_FQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL6_TAP__B 0 +#define QAM_FQ_TAP_RE_EL6_TAP__W 12 +#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6__A 0x142002D +#define QAM_FQ_TAP_IM_EL6__W 12 +#define QAM_FQ_TAP_IM_EL6__M 0xFFF +#define QAM_FQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL6_TAP__B 0 +#define QAM_FQ_TAP_IM_EL6_TAP__W 12 +#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7__A 0x142002E +#define QAM_FQ_TAP_RE_EL7__W 12 +#define QAM_FQ_TAP_RE_EL7__M 0xFFF +#define QAM_FQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL7_TAP__B 0 +#define QAM_FQ_TAP_RE_EL7_TAP__W 12 +#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7__A 0x142002F +#define QAM_FQ_TAP_IM_EL7__W 12 +#define QAM_FQ_TAP_IM_EL7__M 0xFFF +#define QAM_FQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL7_TAP__B 0 +#define QAM_FQ_TAP_IM_EL7_TAP__W 12 +#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8__A 0x1420030 +#define QAM_FQ_TAP_RE_EL8__W 12 +#define QAM_FQ_TAP_RE_EL8__M 0xFFF +#define QAM_FQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL8_TAP__B 0 +#define QAM_FQ_TAP_RE_EL8_TAP__W 12 +#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8__A 0x1420031 +#define QAM_FQ_TAP_IM_EL8__W 12 +#define QAM_FQ_TAP_IM_EL8__M 0xFFF +#define QAM_FQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL8_TAP__B 0 +#define QAM_FQ_TAP_IM_EL8_TAP__W 12 +#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9__A 0x1420032 +#define QAM_FQ_TAP_RE_EL9__W 12 +#define QAM_FQ_TAP_RE_EL9__M 0xFFF +#define QAM_FQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL9_TAP__B 0 +#define QAM_FQ_TAP_RE_EL9_TAP__W 12 +#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9__A 0x1420033 +#define QAM_FQ_TAP_IM_EL9__W 12 +#define QAM_FQ_TAP_IM_EL9__M 0xFFF +#define QAM_FQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL9_TAP__B 0 +#define QAM_FQ_TAP_IM_EL9_TAP__W 12 +#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10__A 0x1420034 +#define QAM_FQ_TAP_RE_EL10__W 12 +#define QAM_FQ_TAP_RE_EL10__M 0xFFF +#define QAM_FQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL10_TAP__B 0 +#define QAM_FQ_TAP_RE_EL10_TAP__W 12 +#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10__A 0x1420035 +#define QAM_FQ_TAP_IM_EL10__W 12 +#define QAM_FQ_TAP_IM_EL10__M 0xFFF +#define QAM_FQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL10_TAP__B 0 +#define QAM_FQ_TAP_IM_EL10_TAP__W 12 +#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11__A 0x1420036 +#define QAM_FQ_TAP_RE_EL11__W 12 +#define QAM_FQ_TAP_RE_EL11__M 0xFFF +#define QAM_FQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL11_TAP__B 0 +#define QAM_FQ_TAP_RE_EL11_TAP__W 12 +#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11__A 0x1420037 +#define QAM_FQ_TAP_IM_EL11__W 12 +#define QAM_FQ_TAP_IM_EL11__M 0xFFF +#define QAM_FQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL11_TAP__B 0 +#define QAM_FQ_TAP_IM_EL11_TAP__W 12 +#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12__A 0x1420038 +#define QAM_FQ_TAP_RE_EL12__W 12 +#define QAM_FQ_TAP_RE_EL12__M 0xFFF +#define QAM_FQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL12_TAP__B 0 +#define QAM_FQ_TAP_RE_EL12_TAP__W 12 +#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12__A 0x1420039 +#define QAM_FQ_TAP_IM_EL12__W 12 +#define QAM_FQ_TAP_IM_EL12__M 0xFFF +#define QAM_FQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL12_TAP__B 0 +#define QAM_FQ_TAP_IM_EL12_TAP__W 12 +#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13__A 0x142003A +#define QAM_FQ_TAP_RE_EL13__W 12 +#define QAM_FQ_TAP_RE_EL13__M 0xFFF +#define QAM_FQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL13_TAP__B 0 +#define QAM_FQ_TAP_RE_EL13_TAP__W 12 +#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13__A 0x142003B +#define QAM_FQ_TAP_IM_EL13__W 12 +#define QAM_FQ_TAP_IM_EL13__M 0xFFF +#define QAM_FQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL13_TAP__B 0 +#define QAM_FQ_TAP_IM_EL13_TAP__W 12 +#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14__A 0x142003C +#define QAM_FQ_TAP_RE_EL14__W 12 +#define QAM_FQ_TAP_RE_EL14__M 0xFFF +#define QAM_FQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL14_TAP__B 0 +#define QAM_FQ_TAP_RE_EL14_TAP__W 12 +#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14__A 0x142003D +#define QAM_FQ_TAP_IM_EL14__W 12 +#define QAM_FQ_TAP_IM_EL14__M 0xFFF +#define QAM_FQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL14_TAP__B 0 +#define QAM_FQ_TAP_IM_EL14_TAP__W 12 +#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15__A 0x142003E +#define QAM_FQ_TAP_RE_EL15__W 12 +#define QAM_FQ_TAP_RE_EL15__M 0xFFF +#define QAM_FQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL15_TAP__B 0 +#define QAM_FQ_TAP_RE_EL15_TAP__W 12 +#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15__A 0x142003F +#define QAM_FQ_TAP_IM_EL15__W 12 +#define QAM_FQ_TAP_IM_EL15__M 0xFFF +#define QAM_FQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL15_TAP__B 0 +#define QAM_FQ_TAP_IM_EL15_TAP__W 12 +#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16__A 0x1420040 +#define QAM_FQ_TAP_RE_EL16__W 12 +#define QAM_FQ_TAP_RE_EL16__M 0xFFF +#define QAM_FQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL16_TAP__B 0 +#define QAM_FQ_TAP_RE_EL16_TAP__W 12 +#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16__A 0x1420041 +#define QAM_FQ_TAP_IM_EL16__W 12 +#define QAM_FQ_TAP_IM_EL16__M 0xFFF +#define QAM_FQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL16_TAP__B 0 +#define QAM_FQ_TAP_IM_EL16_TAP__W 12 +#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17__A 0x1420042 +#define QAM_FQ_TAP_RE_EL17__W 12 +#define QAM_FQ_TAP_RE_EL17__M 0xFFF +#define QAM_FQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL17_TAP__B 0 +#define QAM_FQ_TAP_RE_EL17_TAP__W 12 +#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17__A 0x1420043 +#define QAM_FQ_TAP_IM_EL17__W 12 +#define QAM_FQ_TAP_IM_EL17__M 0xFFF +#define QAM_FQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL17_TAP__B 0 +#define QAM_FQ_TAP_IM_EL17_TAP__W 12 +#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18__A 0x1420044 +#define QAM_FQ_TAP_RE_EL18__W 12 +#define QAM_FQ_TAP_RE_EL18__M 0xFFF +#define QAM_FQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL18_TAP__B 0 +#define QAM_FQ_TAP_RE_EL18_TAP__W 12 +#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18__A 0x1420045 +#define QAM_FQ_TAP_IM_EL18__W 12 +#define QAM_FQ_TAP_IM_EL18__M 0xFFF +#define QAM_FQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL18_TAP__B 0 +#define QAM_FQ_TAP_IM_EL18_TAP__W 12 +#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL19__A 0x1420046 +#define QAM_FQ_TAP_RE_EL19__W 12 +#define QAM_FQ_TAP_RE_EL19__M 0xFFF +#define QAM_FQ_TAP_RE_EL19__PRE 0x600 + +#define QAM_FQ_TAP_RE_EL19_TAP__B 0 +#define QAM_FQ_TAP_RE_EL19_TAP__W 12 +#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600 + +#define QAM_FQ_TAP_IM_EL19__A 0x1420047 +#define QAM_FQ_TAP_IM_EL19__W 12 +#define QAM_FQ_TAP_IM_EL19__M 0xFFF +#define QAM_FQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL19_TAP__B 0 +#define QAM_FQ_TAP_IM_EL19_TAP__W 12 +#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20__A 0x1420048 +#define QAM_FQ_TAP_RE_EL20__W 12 +#define QAM_FQ_TAP_RE_EL20__M 0xFFF +#define QAM_FQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL20_TAP__B 0 +#define QAM_FQ_TAP_RE_EL20_TAP__W 12 +#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20__A 0x1420049 +#define QAM_FQ_TAP_IM_EL20__W 12 +#define QAM_FQ_TAP_IM_EL20__M 0xFFF +#define QAM_FQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL20_TAP__B 0 +#define QAM_FQ_TAP_IM_EL20_TAP__W 12 +#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21__A 0x142004A +#define QAM_FQ_TAP_RE_EL21__W 12 +#define QAM_FQ_TAP_RE_EL21__M 0xFFF +#define QAM_FQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL21_TAP__B 0 +#define QAM_FQ_TAP_RE_EL21_TAP__W 12 +#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21__A 0x142004B +#define QAM_FQ_TAP_IM_EL21__W 12 +#define QAM_FQ_TAP_IM_EL21__M 0xFFF +#define QAM_FQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL21_TAP__B 0 +#define QAM_FQ_TAP_IM_EL21_TAP__W 12 +#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22__A 0x142004C +#define QAM_FQ_TAP_RE_EL22__W 12 +#define QAM_FQ_TAP_RE_EL22__M 0xFFF +#define QAM_FQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL22_TAP__B 0 +#define QAM_FQ_TAP_RE_EL22_TAP__W 12 +#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22__A 0x142004D +#define QAM_FQ_TAP_IM_EL22__W 12 +#define QAM_FQ_TAP_IM_EL22__M 0xFFF +#define QAM_FQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL22_TAP__B 0 +#define QAM_FQ_TAP_IM_EL22_TAP__W 12 +#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23__A 0x142004E +#define QAM_FQ_TAP_RE_EL23__W 12 +#define QAM_FQ_TAP_RE_EL23__M 0xFFF +#define QAM_FQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_FQ_TAP_RE_EL23_TAP__B 0 +#define QAM_FQ_TAP_RE_EL23_TAP__W 12 +#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23__A 0x142004F +#define QAM_FQ_TAP_IM_EL23__W 12 +#define QAM_FQ_TAP_IM_EL23__M 0xFFF +#define QAM_FQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_FQ_TAP_IM_EL23_TAP__B 0 +#define QAM_FQ_TAP_IM_EL23_TAP__W 12 +#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2 + + + +#define QAM_SL_COMM_EXEC__A 0x1430000 +#define QAM_SL_COMM_EXEC__W 2 +#define QAM_SL_COMM_EXEC__M 0x3 +#define QAM_SL_COMM_EXEC__PRE 0x0 +#define QAM_SL_COMM_EXEC_STOP 0x0 +#define QAM_SL_COMM_EXEC_ACTIVE 0x1 +#define QAM_SL_COMM_EXEC_HOLD 0x2 + +#define QAM_SL_COMM_MB__A 0x1430002 +#define QAM_SL_COMM_MB__W 4 +#define QAM_SL_COMM_MB__M 0xF +#define QAM_SL_COMM_MB__PRE 0x0 +#define QAM_SL_COMM_MB_CTL__B 0 +#define QAM_SL_COMM_MB_CTL__W 1 +#define QAM_SL_COMM_MB_CTL__M 0x1 +#define QAM_SL_COMM_MB_CTL__PRE 0x0 +#define QAM_SL_COMM_MB_CTL_OFF 0x0 +#define QAM_SL_COMM_MB_CTL_ON 0x1 +#define QAM_SL_COMM_MB_OBS__B 1 +#define QAM_SL_COMM_MB_OBS__W 1 +#define QAM_SL_COMM_MB_OBS__M 0x2 +#define QAM_SL_COMM_MB_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_OBS_OFF 0x0 +#define QAM_SL_COMM_MB_OBS_ON 0x2 +#define QAM_SL_COMM_MB_MUX_OBS__B 2 +#define QAM_SL_COMM_MB_MUX_OBS__W 2 +#define QAM_SL_COMM_MB_MUX_OBS__M 0xC +#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4 +#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8 +#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC + +#define QAM_SL_COMM_INT_REQ__A 0x1430003 +#define QAM_SL_COMM_INT_REQ__W 1 +#define QAM_SL_COMM_INT_REQ__M 0x1 +#define QAM_SL_COMM_INT_REQ__PRE 0x0 +#define QAM_SL_COMM_INT_STA__A 0x1430005 +#define QAM_SL_COMM_INT_STA__W 2 +#define QAM_SL_COMM_INT_STA__M 0x3 +#define QAM_SL_COMM_INT_STA__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1 +#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_STA_MER_INT__B 1 +#define QAM_SL_COMM_INT_STA_MER_INT__W 1 +#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2 +#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0 + +#define QAM_SL_COMM_INT_MSK__A 0x1430006 +#define QAM_SL_COMM_INT_MSK__W 2 +#define QAM_SL_COMM_INT_MSK__M 0x3 +#define QAM_SL_COMM_INT_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1 +#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0 +#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 +#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2 +#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0 + +#define QAM_SL_COMM_INT_STM__A 0x1430007 +#define QAM_SL_COMM_INT_STM__W 2 +#define QAM_SL_COMM_INT_STM__M 0x3 +#define QAM_SL_COMM_INT_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1 +#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0 +#define QAM_SL_COMM_INT_STM_MER_STM__B 1 +#define QAM_SL_COMM_INT_STM_MER_STM__W 1 +#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2 +#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0 + +#define QAM_SL_MODE__A 0x1430010 +#define QAM_SL_MODE__W 11 +#define QAM_SL_MODE__M 0x7FF +#define QAM_SL_MODE__PRE 0xA + +#define QAM_SL_MODE_SLICER4LC__B 0 +#define QAM_SL_MODE_SLICER4LC__W 2 +#define QAM_SL_MODE_SLICER4LC__M 0x3 +#define QAM_SL_MODE_SLICER4LC__PRE 0x2 +#define QAM_SL_MODE_SLICER4LC_RECT 0x0 +#define QAM_SL_MODE_SLICER4LC_ONET 0x1 +#define QAM_SL_MODE_SLICER4LC_RAD 0x2 + +#define QAM_SL_MODE_SLICER4DQ__B 2 +#define QAM_SL_MODE_SLICER4DQ__W 2 +#define QAM_SL_MODE_SLICER4DQ__M 0xC +#define QAM_SL_MODE_SLICER4DQ__PRE 0x8 +#define QAM_SL_MODE_SLICER4DQ_RECT 0x0 +#define QAM_SL_MODE_SLICER4DQ_ONET 0x4 +#define QAM_SL_MODE_SLICER4DQ_RAD 0x8 + +#define QAM_SL_MODE_SLICER4VD__B 4 +#define QAM_SL_MODE_SLICER4VD__W 2 +#define QAM_SL_MODE_SLICER4VD__M 0x30 +#define QAM_SL_MODE_SLICER4VD__PRE 0x0 +#define QAM_SL_MODE_SLICER4VD_RECT 0x0 +#define QAM_SL_MODE_SLICER4VD_ONET 0x10 +#define QAM_SL_MODE_SLICER4VD_RAD 0x20 + +#define QAM_SL_MODE_ROT_DIS__B 6 +#define QAM_SL_MODE_ROT_DIS__W 1 +#define QAM_SL_MODE_ROT_DIS__M 0x40 +#define QAM_SL_MODE_ROT_DIS__PRE 0x0 +#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40 + +#define QAM_SL_MODE_DQROT_DIS__B 7 +#define QAM_SL_MODE_DQROT_DIS__W 1 +#define QAM_SL_MODE_DQROT_DIS__M 0x80 +#define QAM_SL_MODE_DQROT_DIS__PRE 0x0 +#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0 +#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80 + +#define QAM_SL_MODE_DFE_DIS__B 8 +#define QAM_SL_MODE_DFE_DIS__W 1 +#define QAM_SL_MODE_DFE_DIS__M 0x100 +#define QAM_SL_MODE_DFE_DIS__PRE 0x0 +#define QAM_SL_MODE_DFE_DIS_DQ 0x0 +#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100 + +#define QAM_SL_MODE_RADIUS_MIX__B 9 +#define QAM_SL_MODE_RADIUS_MIX__W 1 +#define QAM_SL_MODE_RADIUS_MIX__M 0x200 +#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0 +#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0 +#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200 + +#define QAM_SL_MODE_TILT_COMP__B 10 +#define QAM_SL_MODE_TILT_COMP__W 1 +#define QAM_SL_MODE_TILT_COMP__M 0x400 +#define QAM_SL_MODE_TILT_COMP__PRE 0x0 +#define QAM_SL_MODE_TILT_COMP_OFF 0x0 +#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400 + + +#define QAM_SL_K_FACTOR__A 0x1430011 +#define QAM_SL_K_FACTOR__W 4 +#define QAM_SL_K_FACTOR__M 0xF +#define QAM_SL_K_FACTOR__PRE 0xC +#define QAM_SL_MEDIAN__A 0x1430012 +#define QAM_SL_MEDIAN__W 14 +#define QAM_SL_MEDIAN__M 0x3FFF +#define QAM_SL_MEDIAN__PRE 0x2C86 + +#define QAM_SL_MEDIAN_LENGTH__B 0 +#define QAM_SL_MEDIAN_LENGTH__W 2 +#define QAM_SL_MEDIAN_LENGTH__M 0x3 +#define QAM_SL_MEDIAN_LENGTH__PRE 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0 +#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1 +#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2 +#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3 + +#define QAM_SL_MEDIAN_CORRECT__B 2 +#define QAM_SL_MEDIAN_CORRECT__W 4 +#define QAM_SL_MEDIAN_CORRECT__M 0x3C +#define QAM_SL_MEDIAN_CORRECT__PRE 0x4 + +#define QAM_SL_MEDIAN_TOLERANCE__B 6 +#define QAM_SL_MEDIAN_TOLERANCE__W 7 +#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0 +#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80 + +#define QAM_SL_MEDIAN_FAST__B 13 +#define QAM_SL_MEDIAN_FAST__W 1 +#define QAM_SL_MEDIAN_FAST__M 0x2000 +#define QAM_SL_MEDIAN_FAST__PRE 0x2000 +#define QAM_SL_MEDIAN_FAST_AVER 0x0 +#define QAM_SL_MEDIAN_FAST_LAST 0x2000 + + +#define QAM_SL_ALPHA__A 0x1430013 +#define QAM_SL_ALPHA__W 3 +#define QAM_SL_ALPHA__M 0x7 +#define QAM_SL_ALPHA__PRE 0x0 + +#define QAM_SL_PHASELIMIT__A 0x1430014 +#define QAM_SL_PHASELIMIT__W 9 +#define QAM_SL_PHASELIMIT__M 0x1FF +#define QAM_SL_PHASELIMIT__PRE 0x0 +#define QAM_SL_MTA_LENGTH__A 0x1430015 +#define QAM_SL_MTA_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH__PRE 0x1 + +#define QAM_SL_MTA_LENGTH_LENGTH__B 0 +#define QAM_SL_MTA_LENGTH_LENGTH__W 2 +#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1 + +#define QAM_SL_MEDIAN_ERROR__A 0x1430016 +#define QAM_SL_MEDIAN_ERROR__W 10 +#define QAM_SL_MEDIAN_ERROR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR__PRE 0x0 + +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF +#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0 + + +#define QAM_SL_ERR_POWER__A 0x1430017 +#define QAM_SL_ERR_POWER__W 16 +#define QAM_SL_ERR_POWER__M 0xFFFF +#define QAM_SL_ERR_POWER__PRE 0x0 +#define QAM_SL_QUAL_QAM_4_0__A 0x1430018 +#define QAM_SL_QUAL_QAM_4_0__W 3 +#define QAM_SL_QUAL_QAM_4_0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_4_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_4_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0__A 0x1430019 +#define QAM_SL_QUAL_QAM_8_0__W 6 +#define QAM_SL_QUAL_QAM_8_0__M 0x3F +#define QAM_SL_QUAL_QAM_8_0__PRE 0xD + +#define QAM_SL_QUAL_QAM_8_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_8_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_8_0_Q1__B 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__W 3 +#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_16_0__A 0x143001A +#define QAM_SL_QUAL_QAM_16_0__W 3 +#define QAM_SL_QUAL_QAM_16_0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_16_1__A 0x143001B +#define QAM_SL_QUAL_QAM_16_1__W 6 +#define QAM_SL_QUAL_QAM_16_1__M 0x3F +#define QAM_SL_QUAL_QAM_16_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_16_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_16_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_0__A 0x143001C +#define QAM_SL_QUAL_QAM_32_0__W 3 +#define QAM_SL_QUAL_QAM_32_0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_32_1__A 0x143001D +#define QAM_SL_QUAL_QAM_32_1__W 6 +#define QAM_SL_QUAL_QAM_32_1__M 0x3F +#define QAM_SL_QUAL_QAM_32_1__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_32_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2__A 0x143001E +#define QAM_SL_QUAL_QAM_32_2__W 9 +#define QAM_SL_QUAL_QAM_32_2__M 0x1FF +#define QAM_SL_QUAL_QAM_32_2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_32_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_32_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_32_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_0__A 0x143001F +#define QAM_SL_QUAL_QAM_64_0__W 3 +#define QAM_SL_QUAL_QAM_64_0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_1__A 0x1430020 +#define QAM_SL_QUAL_QAM_64_1__W 6 +#define QAM_SL_QUAL_QAM_64_1__M 0x3F +#define QAM_SL_QUAL_QAM_64_1__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_64_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_2__A 0x1430021 +#define QAM_SL_QUAL_QAM_64_2__W 9 +#define QAM_SL_QUAL_QAM_64_2__M 0x1FF +#define QAM_SL_QUAL_QAM_64_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_64_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_64_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3__A 0x1430022 +#define QAM_SL_QUAL_QAM_64_3__W 12 +#define QAM_SL_QUAL_QAM_64_3__M 0xFFF +#define QAM_SL_QUAL_QAM_64_3__PRE 0xD + +#define QAM_SL_QUAL_QAM_64_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_64_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_64_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_64_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_64_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_64_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_64_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_0__A 0x1430023 +#define QAM_SL_QUAL_QAM_128_0__W 3 +#define QAM_SL_QUAL_QAM_128_0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4 + +#define QAM_SL_QUAL_QAM_128_1__A 0x1430024 +#define QAM_SL_QUAL_QAM_128_1__W 6 +#define QAM_SL_QUAL_QAM_128_1__M 0x3F +#define QAM_SL_QUAL_QAM_128_1__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_128_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2__A 0x1430025 +#define QAM_SL_QUAL_QAM_128_2__W 9 +#define QAM_SL_QUAL_QAM_128_2__M 0x1FF +#define QAM_SL_QUAL_QAM_128_2__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3__A 0x1430026 +#define QAM_SL_QUAL_QAM_128_3__W 12 +#define QAM_SL_QUAL_QAM_128_3__M 0xFFF +#define QAM_SL_QUAL_QAM_128_3__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_128_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4__A 0x1430027 +#define QAM_SL_QUAL_QAM_128_4__W 15 +#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5__A 0x1430028 +#define QAM_SL_QUAL_QAM_128_5__W 15 +#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_128_5__PRE 0x90 + +#define QAM_SL_QUAL_QAM_128_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_128_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_128_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_128_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_128_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_128_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_128_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029 +#define QAM_SL_QUAL_QAM_128_5H__W 3 +#define QAM_SL_QUAL_QAM_128_5H__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_0__A 0x143002A +#define QAM_SL_QUAL_QAM_256_0__W 3 +#define QAM_SL_QUAL_QAM_256_0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_0_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_0_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_1__A 0x143002B +#define QAM_SL_QUAL_QAM_256_1__W 6 +#define QAM_SL_QUAL_QAM_256_1__M 0x3F +#define QAM_SL_QUAL_QAM_256_1__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_1_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_1_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_2__A 0x143002C +#define QAM_SL_QUAL_QAM_256_2__W 9 +#define QAM_SL_QUAL_QAM_256_2__M 0x1FF +#define QAM_SL_QUAL_QAM_256_2__PRE 0x9 + +#define QAM_SL_QUAL_QAM_256_2_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_2_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_2_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_2_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_2_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3__A 0x143002D +#define QAM_SL_QUAL_QAM_256_3__W 12 +#define QAM_SL_QUAL_QAM_256_3__M 0xFFF +#define QAM_SL_QUAL_QAM_256_3__PRE 0x13 + +#define QAM_SL_QUAL_QAM_256_3_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_3_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3 + +#define QAM_SL_QUAL_QAM_256_3_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10 + +#define QAM_SL_QUAL_QAM_256_3_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_3_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_3_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_3_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4__A 0x143002E +#define QAM_SL_QUAL_QAM_256_4__W 15 +#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_4__PRE 0x49 + +#define QAM_SL_QUAL_QAM_256_4_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_4_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_4_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8 + +#define QAM_SL_QUAL_QAM_256_4_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_4_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_4_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_4_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_4_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_4_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5__A 0x143002F +#define QAM_SL_QUAL_QAM_256_5__W 15 +#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_5__PRE 0x59 + +#define QAM_SL_QUAL_QAM_256_5_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_5_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1 + +#define QAM_SL_QUAL_QAM_256_5_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_5_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_5_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40 + +#define QAM_SL_QUAL_QAM_256_5_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_5_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_5_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030 +#define QAM_SL_QUAL_QAM_256_5H__W 3 +#define QAM_SL_QUAL_QAM_256_5H__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6__A 0x1430031 +#define QAM_SL_QUAL_QAM_256_6__W 15 +#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A + +#define QAM_SL_QUAL_QAM_256_6_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_6_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2 + +#define QAM_SL_QUAL_QAM_256_6_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_6_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_6_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_6_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_6_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_6_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032 +#define QAM_SL_QUAL_QAM_256_6H__W 6 +#define QAM_SL_QUAL_QAM_256_6H__M 0x3F +#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7__A 0x1430033 +#define QAM_SL_QUAL_QAM_256_7__W 15 +#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF +#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D + +#define QAM_SL_QUAL_QAM_256_7_Q0__B 0 +#define QAM_SL_QUAL_QAM_256_7_Q0__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7 +#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5 + +#define QAM_SL_QUAL_QAM_256_7_Q1__B 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38 +#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18 + +#define QAM_SL_QUAL_QAM_256_7_Q2__B 6 +#define QAM_SL_QUAL_QAM_256_7_Q2__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80 + +#define QAM_SL_QUAL_QAM_256_7_Q3__B 9 +#define QAM_SL_QUAL_QAM_256_7_Q3__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00 +#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200 + +#define QAM_SL_QUAL_QAM_256_7_Q4__B 12 +#define QAM_SL_QUAL_QAM_256_7_Q4__W 3 +#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000 +#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034 +#define QAM_SL_QUAL_QAM_256_7H__W 9 +#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF +#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0 +#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7 +#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38 +#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0 + +#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6 +#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3 +#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0 +#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0 + + + +#define QAM_DQ_COMM_EXEC__A 0x1440000 +#define QAM_DQ_COMM_EXEC__W 2 +#define QAM_DQ_COMM_EXEC__M 0x3 +#define QAM_DQ_COMM_EXEC__PRE 0x0 +#define QAM_DQ_COMM_EXEC_STOP 0x0 +#define QAM_DQ_COMM_EXEC_ACTIVE 0x1 +#define QAM_DQ_COMM_EXEC_HOLD 0x2 + +#define QAM_DQ_MODE__A 0x1440010 +#define QAM_DQ_MODE__W 5 +#define QAM_DQ_MODE__M 0x1F +#define QAM_DQ_MODE__PRE 0x0 + +#define QAM_DQ_MODE_TAPRESET__B 0 +#define QAM_DQ_MODE_TAPRESET__W 1 +#define QAM_DQ_MODE_TAPRESET__M 0x1 +#define QAM_DQ_MODE_TAPRESET__PRE 0x0 +#define QAM_DQ_MODE_TAPRESET_RST 0x1 + +#define QAM_DQ_MODE_TAPLMS__B 1 +#define QAM_DQ_MODE_TAPLMS__W 1 +#define QAM_DQ_MODE_TAPLMS__M 0x2 +#define QAM_DQ_MODE_TAPLMS__PRE 0x0 +#define QAM_DQ_MODE_TAPLMS_UPD 0x2 + +#define QAM_DQ_MODE_TAPDRAIN__B 2 +#define QAM_DQ_MODE_TAPDRAIN__W 1 +#define QAM_DQ_MODE_TAPDRAIN__M 0x4 +#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0 +#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4 + +#define QAM_DQ_MODE_FB__B 3 +#define QAM_DQ_MODE_FB__W 2 +#define QAM_DQ_MODE_FB__M 0x18 +#define QAM_DQ_MODE_FB__PRE 0x0 +#define QAM_DQ_MODE_FB_CMA 0x0 +#define QAM_DQ_MODE_FB_RADIUS 0x8 +#define QAM_DQ_MODE_FB_DFB 0x10 +#define QAM_DQ_MODE_FB_TRELLIS 0x18 + + +#define QAM_DQ_MU_FACTOR__A 0x1440011 +#define QAM_DQ_MU_FACTOR__W 3 +#define QAM_DQ_MU_FACTOR__M 0x7 +#define QAM_DQ_MU_FACTOR__PRE 0x0 + +#define QAM_DQ_LA_FACTOR__A 0x1440012 +#define QAM_DQ_LA_FACTOR__W 4 +#define QAM_DQ_LA_FACTOR__M 0xF +#define QAM_DQ_LA_FACTOR__PRE 0xC + +#define QAM_DQ_CMA_RATIO__A 0x1440013 +#define QAM_DQ_CMA_RATIO__W 14 +#define QAM_DQ_CMA_RATIO__M 0x3FFF +#define QAM_DQ_CMA_RATIO__PRE 0x3CF9 +#define QAM_DQ_CMA_RATIO_QPSK 0x2000 +#define QAM_DQ_CMA_RATIO_QAM16 0x34CD +#define QAM_DQ_CMA_RATIO_QAM64 0x3A00 +#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D +#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0 + +#define QAM_DQ_QUAL_RADSEL__A 0x1440014 +#define QAM_DQ_QUAL_RADSEL__W 3 +#define QAM_DQ_QUAL_RADSEL__M 0x7 +#define QAM_DQ_QUAL_RADSEL__PRE 0x0 + +#define QAM_DQ_QUAL_RADSEL_BIT__B 0 +#define QAM_DQ_QUAL_RADSEL_BIT__W 3 +#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7 +#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0 +#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6 + +#define QAM_DQ_QUAL_ENA__A 0x1440015 +#define QAM_DQ_QUAL_ENA__W 1 +#define QAM_DQ_QUAL_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA__PRE 0x0 + +#define QAM_DQ_QUAL_ENA_ENA__B 0 +#define QAM_DQ_QUAL_ENA_ENA__W 1 +#define QAM_DQ_QUAL_ENA_ENA__M 0x1 +#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0 +#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1 + +#define QAM_DQ_QUAL_FUN0__A 0x1440018 +#define QAM_DQ_QUAL_FUN0__W 6 +#define QAM_DQ_QUAL_FUN0__M 0x3F +#define QAM_DQ_QUAL_FUN0__PRE 0x4 + +#define QAM_DQ_QUAL_FUN0_BIT__B 0 +#define QAM_DQ_QUAL_FUN0_BIT__W 6 +#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1__A 0x1440019 +#define QAM_DQ_QUAL_FUN1__W 6 +#define QAM_DQ_QUAL_FUN1__M 0x3F +#define QAM_DQ_QUAL_FUN1__PRE 0x4 + +#define QAM_DQ_QUAL_FUN1_BIT__B 0 +#define QAM_DQ_QUAL_FUN1_BIT__W 6 +#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2__A 0x144001A +#define QAM_DQ_QUAL_FUN2__W 6 +#define QAM_DQ_QUAL_FUN2__M 0x3F +#define QAM_DQ_QUAL_FUN2__PRE 0x4 + +#define QAM_DQ_QUAL_FUN2_BIT__B 0 +#define QAM_DQ_QUAL_FUN2_BIT__W 6 +#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3__A 0x144001B +#define QAM_DQ_QUAL_FUN3__W 6 +#define QAM_DQ_QUAL_FUN3__M 0x3F +#define QAM_DQ_QUAL_FUN3__PRE 0x4 + +#define QAM_DQ_QUAL_FUN3_BIT__B 0 +#define QAM_DQ_QUAL_FUN3_BIT__W 6 +#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4 + +#define QAM_DQ_QUAL_FUN4__A 0x144001C +#define QAM_DQ_QUAL_FUN4__W 6 +#define QAM_DQ_QUAL_FUN4__M 0x3F +#define QAM_DQ_QUAL_FUN4__PRE 0x6 + +#define QAM_DQ_QUAL_FUN4_BIT__B 0 +#define QAM_DQ_QUAL_FUN4_BIT__W 6 +#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5__A 0x144001D +#define QAM_DQ_QUAL_FUN5__W 6 +#define QAM_DQ_QUAL_FUN5__M 0x3F +#define QAM_DQ_QUAL_FUN5__PRE 0x6 + +#define QAM_DQ_QUAL_FUN5_BIT__B 0 +#define QAM_DQ_QUAL_FUN5_BIT__W 6 +#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F +#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6 + +#define QAM_DQ_RAW_LIM__A 0x144001E +#define QAM_DQ_RAW_LIM__W 5 +#define QAM_DQ_RAW_LIM__M 0x1F +#define QAM_DQ_RAW_LIM__PRE 0x1F + +#define QAM_DQ_RAW_LIM_BIT__B 0 +#define QAM_DQ_RAW_LIM_BIT__W 5 +#define QAM_DQ_RAW_LIM_BIT__M 0x1F +#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F + +#define QAM_DQ_TAP_RE_EL0__A 0x1440020 +#define QAM_DQ_TAP_RE_EL0__W 12 +#define QAM_DQ_TAP_RE_EL0__M 0xFFF +#define QAM_DQ_TAP_RE_EL0__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL0_TAP__B 0 +#define QAM_DQ_TAP_RE_EL0_TAP__W 12 +#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0__A 0x1440021 +#define QAM_DQ_TAP_IM_EL0__W 12 +#define QAM_DQ_TAP_IM_EL0__M 0xFFF +#define QAM_DQ_TAP_IM_EL0__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL0_TAP__B 0 +#define QAM_DQ_TAP_IM_EL0_TAP__W 12 +#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1__A 0x1440022 +#define QAM_DQ_TAP_RE_EL1__W 12 +#define QAM_DQ_TAP_RE_EL1__M 0xFFF +#define QAM_DQ_TAP_RE_EL1__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL1_TAP__B 0 +#define QAM_DQ_TAP_RE_EL1_TAP__W 12 +#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1__A 0x1440023 +#define QAM_DQ_TAP_IM_EL1__W 12 +#define QAM_DQ_TAP_IM_EL1__M 0xFFF +#define QAM_DQ_TAP_IM_EL1__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL1_TAP__B 0 +#define QAM_DQ_TAP_IM_EL1_TAP__W 12 +#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2__A 0x1440024 +#define QAM_DQ_TAP_RE_EL2__W 12 +#define QAM_DQ_TAP_RE_EL2__M 0xFFF +#define QAM_DQ_TAP_RE_EL2__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL2_TAP__B 0 +#define QAM_DQ_TAP_RE_EL2_TAP__W 12 +#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2__A 0x1440025 +#define QAM_DQ_TAP_IM_EL2__W 12 +#define QAM_DQ_TAP_IM_EL2__M 0xFFF +#define QAM_DQ_TAP_IM_EL2__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL2_TAP__B 0 +#define QAM_DQ_TAP_IM_EL2_TAP__W 12 +#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3__A 0x1440026 +#define QAM_DQ_TAP_RE_EL3__W 12 +#define QAM_DQ_TAP_RE_EL3__M 0xFFF +#define QAM_DQ_TAP_RE_EL3__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL3_TAP__B 0 +#define QAM_DQ_TAP_RE_EL3_TAP__W 12 +#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3__A 0x1440027 +#define QAM_DQ_TAP_IM_EL3__W 12 +#define QAM_DQ_TAP_IM_EL3__M 0xFFF +#define QAM_DQ_TAP_IM_EL3__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL3_TAP__B 0 +#define QAM_DQ_TAP_IM_EL3_TAP__W 12 +#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4__A 0x1440028 +#define QAM_DQ_TAP_RE_EL4__W 12 +#define QAM_DQ_TAP_RE_EL4__M 0xFFF +#define QAM_DQ_TAP_RE_EL4__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL4_TAP__B 0 +#define QAM_DQ_TAP_RE_EL4_TAP__W 12 +#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4__A 0x1440029 +#define QAM_DQ_TAP_IM_EL4__W 12 +#define QAM_DQ_TAP_IM_EL4__M 0xFFF +#define QAM_DQ_TAP_IM_EL4__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL4_TAP__B 0 +#define QAM_DQ_TAP_IM_EL4_TAP__W 12 +#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5__A 0x144002A +#define QAM_DQ_TAP_RE_EL5__W 12 +#define QAM_DQ_TAP_RE_EL5__M 0xFFF +#define QAM_DQ_TAP_RE_EL5__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL5_TAP__B 0 +#define QAM_DQ_TAP_RE_EL5_TAP__W 12 +#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5__A 0x144002B +#define QAM_DQ_TAP_IM_EL5__W 12 +#define QAM_DQ_TAP_IM_EL5__M 0xFFF +#define QAM_DQ_TAP_IM_EL5__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL5_TAP__B 0 +#define QAM_DQ_TAP_IM_EL5_TAP__W 12 +#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6__A 0x144002C +#define QAM_DQ_TAP_RE_EL6__W 12 +#define QAM_DQ_TAP_RE_EL6__M 0xFFF +#define QAM_DQ_TAP_RE_EL6__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL6_TAP__B 0 +#define QAM_DQ_TAP_RE_EL6_TAP__W 12 +#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6__A 0x144002D +#define QAM_DQ_TAP_IM_EL6__W 12 +#define QAM_DQ_TAP_IM_EL6__M 0xFFF +#define QAM_DQ_TAP_IM_EL6__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL6_TAP__B 0 +#define QAM_DQ_TAP_IM_EL6_TAP__W 12 +#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7__A 0x144002E +#define QAM_DQ_TAP_RE_EL7__W 12 +#define QAM_DQ_TAP_RE_EL7__M 0xFFF +#define QAM_DQ_TAP_RE_EL7__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL7_TAP__B 0 +#define QAM_DQ_TAP_RE_EL7_TAP__W 12 +#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7__A 0x144002F +#define QAM_DQ_TAP_IM_EL7__W 12 +#define QAM_DQ_TAP_IM_EL7__M 0xFFF +#define QAM_DQ_TAP_IM_EL7__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL7_TAP__B 0 +#define QAM_DQ_TAP_IM_EL7_TAP__W 12 +#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8__A 0x1440030 +#define QAM_DQ_TAP_RE_EL8__W 12 +#define QAM_DQ_TAP_RE_EL8__M 0xFFF +#define QAM_DQ_TAP_RE_EL8__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL8_TAP__B 0 +#define QAM_DQ_TAP_RE_EL8_TAP__W 12 +#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8__A 0x1440031 +#define QAM_DQ_TAP_IM_EL8__W 12 +#define QAM_DQ_TAP_IM_EL8__M 0xFFF +#define QAM_DQ_TAP_IM_EL8__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL8_TAP__B 0 +#define QAM_DQ_TAP_IM_EL8_TAP__W 12 +#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9__A 0x1440032 +#define QAM_DQ_TAP_RE_EL9__W 12 +#define QAM_DQ_TAP_RE_EL9__M 0xFFF +#define QAM_DQ_TAP_RE_EL9__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL9_TAP__B 0 +#define QAM_DQ_TAP_RE_EL9_TAP__W 12 +#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9__A 0x1440033 +#define QAM_DQ_TAP_IM_EL9__W 12 +#define QAM_DQ_TAP_IM_EL9__M 0xFFF +#define QAM_DQ_TAP_IM_EL9__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL9_TAP__B 0 +#define QAM_DQ_TAP_IM_EL9_TAP__W 12 +#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10__A 0x1440034 +#define QAM_DQ_TAP_RE_EL10__W 12 +#define QAM_DQ_TAP_RE_EL10__M 0xFFF +#define QAM_DQ_TAP_RE_EL10__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL10_TAP__B 0 +#define QAM_DQ_TAP_RE_EL10_TAP__W 12 +#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10__A 0x1440035 +#define QAM_DQ_TAP_IM_EL10__W 12 +#define QAM_DQ_TAP_IM_EL10__M 0xFFF +#define QAM_DQ_TAP_IM_EL10__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL10_TAP__B 0 +#define QAM_DQ_TAP_IM_EL10_TAP__W 12 +#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11__A 0x1440036 +#define QAM_DQ_TAP_RE_EL11__W 12 +#define QAM_DQ_TAP_RE_EL11__M 0xFFF +#define QAM_DQ_TAP_RE_EL11__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL11_TAP__B 0 +#define QAM_DQ_TAP_RE_EL11_TAP__W 12 +#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11__A 0x1440037 +#define QAM_DQ_TAP_IM_EL11__W 12 +#define QAM_DQ_TAP_IM_EL11__M 0xFFF +#define QAM_DQ_TAP_IM_EL11__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL11_TAP__B 0 +#define QAM_DQ_TAP_IM_EL11_TAP__W 12 +#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12__A 0x1440038 +#define QAM_DQ_TAP_RE_EL12__W 12 +#define QAM_DQ_TAP_RE_EL12__M 0xFFF +#define QAM_DQ_TAP_RE_EL12__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL12_TAP__B 0 +#define QAM_DQ_TAP_RE_EL12_TAP__W 12 +#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12__A 0x1440039 +#define QAM_DQ_TAP_IM_EL12__W 12 +#define QAM_DQ_TAP_IM_EL12__M 0xFFF +#define QAM_DQ_TAP_IM_EL12__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL12_TAP__B 0 +#define QAM_DQ_TAP_IM_EL12_TAP__W 12 +#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13__A 0x144003A +#define QAM_DQ_TAP_RE_EL13__W 12 +#define QAM_DQ_TAP_RE_EL13__M 0xFFF +#define QAM_DQ_TAP_RE_EL13__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL13_TAP__B 0 +#define QAM_DQ_TAP_RE_EL13_TAP__W 12 +#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13__A 0x144003B +#define QAM_DQ_TAP_IM_EL13__W 12 +#define QAM_DQ_TAP_IM_EL13__M 0xFFF +#define QAM_DQ_TAP_IM_EL13__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL13_TAP__B 0 +#define QAM_DQ_TAP_IM_EL13_TAP__W 12 +#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14__A 0x144003C +#define QAM_DQ_TAP_RE_EL14__W 12 +#define QAM_DQ_TAP_RE_EL14__M 0xFFF +#define QAM_DQ_TAP_RE_EL14__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL14_TAP__B 0 +#define QAM_DQ_TAP_RE_EL14_TAP__W 12 +#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14__A 0x144003D +#define QAM_DQ_TAP_IM_EL14__W 12 +#define QAM_DQ_TAP_IM_EL14__M 0xFFF +#define QAM_DQ_TAP_IM_EL14__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL14_TAP__B 0 +#define QAM_DQ_TAP_IM_EL14_TAP__W 12 +#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15__A 0x144003E +#define QAM_DQ_TAP_RE_EL15__W 12 +#define QAM_DQ_TAP_RE_EL15__M 0xFFF +#define QAM_DQ_TAP_RE_EL15__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL15_TAP__B 0 +#define QAM_DQ_TAP_RE_EL15_TAP__W 12 +#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15__A 0x144003F +#define QAM_DQ_TAP_IM_EL15__W 12 +#define QAM_DQ_TAP_IM_EL15__M 0xFFF +#define QAM_DQ_TAP_IM_EL15__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL15_TAP__B 0 +#define QAM_DQ_TAP_IM_EL15_TAP__W 12 +#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16__A 0x1440040 +#define QAM_DQ_TAP_RE_EL16__W 12 +#define QAM_DQ_TAP_RE_EL16__M 0xFFF +#define QAM_DQ_TAP_RE_EL16__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL16_TAP__B 0 +#define QAM_DQ_TAP_RE_EL16_TAP__W 12 +#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16__A 0x1440041 +#define QAM_DQ_TAP_IM_EL16__W 12 +#define QAM_DQ_TAP_IM_EL16__M 0xFFF +#define QAM_DQ_TAP_IM_EL16__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL16_TAP__B 0 +#define QAM_DQ_TAP_IM_EL16_TAP__W 12 +#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17__A 0x1440042 +#define QAM_DQ_TAP_RE_EL17__W 12 +#define QAM_DQ_TAP_RE_EL17__M 0xFFF +#define QAM_DQ_TAP_RE_EL17__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL17_TAP__B 0 +#define QAM_DQ_TAP_RE_EL17_TAP__W 12 +#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17__A 0x1440043 +#define QAM_DQ_TAP_IM_EL17__W 12 +#define QAM_DQ_TAP_IM_EL17__M 0xFFF +#define QAM_DQ_TAP_IM_EL17__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL17_TAP__B 0 +#define QAM_DQ_TAP_IM_EL17_TAP__W 12 +#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18__A 0x1440044 +#define QAM_DQ_TAP_RE_EL18__W 12 +#define QAM_DQ_TAP_RE_EL18__M 0xFFF +#define QAM_DQ_TAP_RE_EL18__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL18_TAP__B 0 +#define QAM_DQ_TAP_RE_EL18_TAP__W 12 +#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18__A 0x1440045 +#define QAM_DQ_TAP_IM_EL18__W 12 +#define QAM_DQ_TAP_IM_EL18__M 0xFFF +#define QAM_DQ_TAP_IM_EL18__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL18_TAP__B 0 +#define QAM_DQ_TAP_IM_EL18_TAP__W 12 +#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19__A 0x1440046 +#define QAM_DQ_TAP_RE_EL19__W 12 +#define QAM_DQ_TAP_RE_EL19__M 0xFFF +#define QAM_DQ_TAP_RE_EL19__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL19_TAP__B 0 +#define QAM_DQ_TAP_RE_EL19_TAP__W 12 +#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19__A 0x1440047 +#define QAM_DQ_TAP_IM_EL19__W 12 +#define QAM_DQ_TAP_IM_EL19__M 0xFFF +#define QAM_DQ_TAP_IM_EL19__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL19_TAP__B 0 +#define QAM_DQ_TAP_IM_EL19_TAP__W 12 +#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20__A 0x1440048 +#define QAM_DQ_TAP_RE_EL20__W 12 +#define QAM_DQ_TAP_RE_EL20__M 0xFFF +#define QAM_DQ_TAP_RE_EL20__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL20_TAP__B 0 +#define QAM_DQ_TAP_RE_EL20_TAP__W 12 +#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20__A 0x1440049 +#define QAM_DQ_TAP_IM_EL20__W 12 +#define QAM_DQ_TAP_IM_EL20__M 0xFFF +#define QAM_DQ_TAP_IM_EL20__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL20_TAP__B 0 +#define QAM_DQ_TAP_IM_EL20_TAP__W 12 +#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21__A 0x144004A +#define QAM_DQ_TAP_RE_EL21__W 12 +#define QAM_DQ_TAP_RE_EL21__M 0xFFF +#define QAM_DQ_TAP_RE_EL21__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL21_TAP__B 0 +#define QAM_DQ_TAP_RE_EL21_TAP__W 12 +#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21__A 0x144004B +#define QAM_DQ_TAP_IM_EL21__W 12 +#define QAM_DQ_TAP_IM_EL21__M 0xFFF +#define QAM_DQ_TAP_IM_EL21__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL21_TAP__B 0 +#define QAM_DQ_TAP_IM_EL21_TAP__W 12 +#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22__A 0x144004C +#define QAM_DQ_TAP_RE_EL22__W 12 +#define QAM_DQ_TAP_RE_EL22__M 0xFFF +#define QAM_DQ_TAP_RE_EL22__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL22_TAP__B 0 +#define QAM_DQ_TAP_RE_EL22_TAP__W 12 +#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22__A 0x144004D +#define QAM_DQ_TAP_IM_EL22__W 12 +#define QAM_DQ_TAP_IM_EL22__M 0xFFF +#define QAM_DQ_TAP_IM_EL22__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL22_TAP__B 0 +#define QAM_DQ_TAP_IM_EL22_TAP__W 12 +#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23__A 0x144004E +#define QAM_DQ_TAP_RE_EL23__W 12 +#define QAM_DQ_TAP_RE_EL23__M 0xFFF +#define QAM_DQ_TAP_RE_EL23__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL23_TAP__B 0 +#define QAM_DQ_TAP_RE_EL23_TAP__W 12 +#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23__A 0x144004F +#define QAM_DQ_TAP_IM_EL23__W 12 +#define QAM_DQ_TAP_IM_EL23__M 0xFFF +#define QAM_DQ_TAP_IM_EL23__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL23_TAP__B 0 +#define QAM_DQ_TAP_IM_EL23_TAP__W 12 +#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24__A 0x1440050 +#define QAM_DQ_TAP_RE_EL24__W 12 +#define QAM_DQ_TAP_RE_EL24__M 0xFFF +#define QAM_DQ_TAP_RE_EL24__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL24_TAP__B 0 +#define QAM_DQ_TAP_RE_EL24_TAP__W 12 +#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24__A 0x1440051 +#define QAM_DQ_TAP_IM_EL24__W 12 +#define QAM_DQ_TAP_IM_EL24__M 0xFFF +#define QAM_DQ_TAP_IM_EL24__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL24_TAP__B 0 +#define QAM_DQ_TAP_IM_EL24_TAP__W 12 +#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25__A 0x1440052 +#define QAM_DQ_TAP_RE_EL25__W 12 +#define QAM_DQ_TAP_RE_EL25__M 0xFFF +#define QAM_DQ_TAP_RE_EL25__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL25_TAP__B 0 +#define QAM_DQ_TAP_RE_EL25_TAP__W 12 +#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25__A 0x1440053 +#define QAM_DQ_TAP_IM_EL25__W 12 +#define QAM_DQ_TAP_IM_EL25__M 0xFFF +#define QAM_DQ_TAP_IM_EL25__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL25_TAP__B 0 +#define QAM_DQ_TAP_IM_EL25_TAP__W 12 +#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26__A 0x1440054 +#define QAM_DQ_TAP_RE_EL26__W 12 +#define QAM_DQ_TAP_RE_EL26__M 0xFFF +#define QAM_DQ_TAP_RE_EL26__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL26_TAP__B 0 +#define QAM_DQ_TAP_RE_EL26_TAP__W 12 +#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26__A 0x1440055 +#define QAM_DQ_TAP_IM_EL26__W 12 +#define QAM_DQ_TAP_IM_EL26__M 0xFFF +#define QAM_DQ_TAP_IM_EL26__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL26_TAP__B 0 +#define QAM_DQ_TAP_IM_EL26_TAP__W 12 +#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27__A 0x1440056 +#define QAM_DQ_TAP_RE_EL27__W 12 +#define QAM_DQ_TAP_RE_EL27__M 0xFFF +#define QAM_DQ_TAP_RE_EL27__PRE 0x2 + +#define QAM_DQ_TAP_RE_EL27_TAP__B 0 +#define QAM_DQ_TAP_RE_EL27_TAP__W 12 +#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27__A 0x1440057 +#define QAM_DQ_TAP_IM_EL27__W 12 +#define QAM_DQ_TAP_IM_EL27__M 0xFFF +#define QAM_DQ_TAP_IM_EL27__PRE 0x2 + +#define QAM_DQ_TAP_IM_EL27_TAP__B 0 +#define QAM_DQ_TAP_IM_EL27_TAP__W 12 +#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF +#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2 + + + +#define QAM_LC_COMM_EXEC__A 0x1450000 +#define QAM_LC_COMM_EXEC__W 2 +#define QAM_LC_COMM_EXEC__M 0x3 +#define QAM_LC_COMM_EXEC__PRE 0x0 +#define QAM_LC_COMM_EXEC_STOP 0x0 +#define QAM_LC_COMM_EXEC_ACTIVE 0x1 +#define QAM_LC_COMM_EXEC_HOLD 0x2 + +#define QAM_LC_COMM_MB__A 0x1450002 +#define QAM_LC_COMM_MB__W 2 +#define QAM_LC_COMM_MB__M 0x3 +#define QAM_LC_COMM_MB__PRE 0x0 +#define QAM_LC_COMM_MB_CTL__B 0 +#define QAM_LC_COMM_MB_CTL__W 1 +#define QAM_LC_COMM_MB_CTL__M 0x1 +#define QAM_LC_COMM_MB_CTL__PRE 0x0 +#define QAM_LC_COMM_MB_CTL_OFF 0x0 +#define QAM_LC_COMM_MB_CTL_ON 0x1 +#define QAM_LC_COMM_MB_OBS__B 1 +#define QAM_LC_COMM_MB_OBS__W 1 +#define QAM_LC_COMM_MB_OBS__M 0x2 +#define QAM_LC_COMM_MB_OBS__PRE 0x0 +#define QAM_LC_COMM_MB_OBS_OFF 0x0 +#define QAM_LC_COMM_MB_OBS_ON 0x2 + +#define QAM_LC_COMM_INT_REQ__A 0x1450003 +#define QAM_LC_COMM_INT_REQ__W 1 +#define QAM_LC_COMM_INT_REQ__M 0x1 +#define QAM_LC_COMM_INT_REQ__PRE 0x0 +#define QAM_LC_COMM_INT_STA__A 0x1450005 +#define QAM_LC_COMM_INT_STA__W 3 +#define QAM_LC_COMM_INT_STA__M 0x7 +#define QAM_LC_COMM_INT_STA__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_READY__B 0 +#define QAM_LC_COMM_INT_STA_READY__W 1 +#define QAM_LC_COMM_INT_STA_READY__M 0x1 +#define QAM_LC_COMM_INT_STA_READY__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0 + +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_MSK__A 0x1450006 +#define QAM_LC_COMM_INT_MSK__W 3 +#define QAM_LC_COMM_INT_MSK__M 0x7 +#define QAM_LC_COMM_INT_MSK__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_READY__B 0 +#define QAM_LC_COMM_INT_MSK_READY__W 1 +#define QAM_LC_COMM_INT_MSK_READY__M 0x1 +#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_COMM_INT_STM__A 0x1450007 +#define QAM_LC_COMM_INT_STM__W 3 +#define QAM_LC_COMM_INT_STM__M 0x7 +#define QAM_LC_COMM_INT_STM__PRE 0x0 +#define QAM_LC_COMM_INT_STM_READY__B 0 +#define QAM_LC_COMM_INT_STM_READY__W 1 +#define QAM_LC_COMM_INT_STM_READY__M 0x1 +#define QAM_LC_COMM_INT_STM_READY__PRE 0x0 +#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 +#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2 +#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4 +#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0 + +#define QAM_LC_MODE__A 0x1450010 +#define QAM_LC_MODE__W 4 +#define QAM_LC_MODE__M 0xF +#define QAM_LC_MODE__PRE 0xE + +#define QAM_LC_MODE_ENABLE_A__B 0 +#define QAM_LC_MODE_ENABLE_A__W 1 +#define QAM_LC_MODE_ENABLE_A__M 0x1 +#define QAM_LC_MODE_ENABLE_A__PRE 0x0 + +#define QAM_LC_MODE_ENABLE_F__B 1 +#define QAM_LC_MODE_ENABLE_F__W 1 +#define QAM_LC_MODE_ENABLE_F__M 0x2 +#define QAM_LC_MODE_ENABLE_F__PRE 0x2 + +#define QAM_LC_MODE_ENABLE_R__B 2 +#define QAM_LC_MODE_ENABLE_R__W 1 +#define QAM_LC_MODE_ENABLE_R__M 0x4 +#define QAM_LC_MODE_ENABLE_R__PRE 0x4 + +#define QAM_LC_MODE_ENABLE_PQUAL__B 3 +#define QAM_LC_MODE_ENABLE_PQUAL__W 1 +#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8 +#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8 + +#define QAM_LC_CA__A 0x1450011 +#define QAM_LC_CA__W 6 +#define QAM_LC_CA__M 0x3F +#define QAM_LC_CA__PRE 0x28 + +#define QAM_LC_CA_COEF__B 0 +#define QAM_LC_CA_COEF__W 6 +#define QAM_LC_CA_COEF__M 0x3F +#define QAM_LC_CA_COEF__PRE 0x28 + +#define QAM_LC_CF__A 0x1450012 +#define QAM_LC_CF__W 8 +#define QAM_LC_CF__M 0xFF +#define QAM_LC_CF__PRE 0x30 + +#define QAM_LC_CF_COEF__B 0 +#define QAM_LC_CF_COEF__W 8 +#define QAM_LC_CF_COEF__M 0xFF +#define QAM_LC_CF_COEF__PRE 0x30 + +#define QAM_LC_CF1__A 0x1450013 +#define QAM_LC_CF1__W 8 +#define QAM_LC_CF1__M 0xFF +#define QAM_LC_CF1__PRE 0x14 + +#define QAM_LC_CF1_COEF__B 0 +#define QAM_LC_CF1_COEF__W 8 +#define QAM_LC_CF1_COEF__M 0xFF +#define QAM_LC_CF1_COEF__PRE 0x14 + +#define QAM_LC_CP__A 0x1450014 +#define QAM_LC_CP__W 8 +#define QAM_LC_CP__M 0xFF +#define QAM_LC_CP__PRE 0x64 + +#define QAM_LC_CP_COEF__B 0 +#define QAM_LC_CP_COEF__W 8 +#define QAM_LC_CP_COEF__M 0xFF +#define QAM_LC_CP_COEF__PRE 0x64 + +#define QAM_LC_CI__A 0x1450015 +#define QAM_LC_CI__W 8 +#define QAM_LC_CI__M 0xFF +#define QAM_LC_CI__PRE 0x32 + +#define QAM_LC_CI_COEF__B 0 +#define QAM_LC_CI_COEF__W 8 +#define QAM_LC_CI_COEF__M 0xFF +#define QAM_LC_CI_COEF__PRE 0x32 + +#define QAM_LC_EP__A 0x1450016 +#define QAM_LC_EP__W 6 +#define QAM_LC_EP__M 0x3F +#define QAM_LC_EP__PRE 0x0 + +#define QAM_LC_EP_COEF__B 0 +#define QAM_LC_EP_COEF__W 6 +#define QAM_LC_EP_COEF__M 0x3F +#define QAM_LC_EP_COEF__PRE 0x0 + +#define QAM_LC_EI__A 0x1450017 +#define QAM_LC_EI__W 6 +#define QAM_LC_EI__M 0x3F +#define QAM_LC_EI__PRE 0x0 + +#define QAM_LC_EI_COEF__B 0 +#define QAM_LC_EI_COEF__W 6 +#define QAM_LC_EI_COEF__M 0x3F +#define QAM_LC_EI_COEF__PRE 0x0 + +#define QAM_LC_QUAL_TAB0__A 0x1450018 +#define QAM_LC_QUAL_TAB0__W 5 +#define QAM_LC_QUAL_TAB0__M 0x1F +#define QAM_LC_QUAL_TAB0__PRE 0x0 + +#define QAM_LC_QUAL_TAB0_VALUE__B 0 +#define QAM_LC_QUAL_TAB0_VALUE__W 5 +#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0 + +#define QAM_LC_QUAL_TAB1__A 0x1450019 +#define QAM_LC_QUAL_TAB1__W 5 +#define QAM_LC_QUAL_TAB1__M 0x1F +#define QAM_LC_QUAL_TAB1__PRE 0x1 + +#define QAM_LC_QUAL_TAB1_VALUE__B 0 +#define QAM_LC_QUAL_TAB1_VALUE__W 5 +#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1 + +#define QAM_LC_QUAL_TAB2__A 0x145001A +#define QAM_LC_QUAL_TAB2__W 5 +#define QAM_LC_QUAL_TAB2__M 0x1F +#define QAM_LC_QUAL_TAB2__PRE 0x2 + +#define QAM_LC_QUAL_TAB2_VALUE__B 0 +#define QAM_LC_QUAL_TAB2_VALUE__W 5 +#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2 + +#define QAM_LC_QUAL_TAB3__A 0x145001B +#define QAM_LC_QUAL_TAB3__W 5 +#define QAM_LC_QUAL_TAB3__M 0x1F +#define QAM_LC_QUAL_TAB3__PRE 0x3 + +#define QAM_LC_QUAL_TAB3_VALUE__B 0 +#define QAM_LC_QUAL_TAB3_VALUE__W 5 +#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3 + +#define QAM_LC_QUAL_TAB4__A 0x145001C +#define QAM_LC_QUAL_TAB4__W 5 +#define QAM_LC_QUAL_TAB4__M 0x1F +#define QAM_LC_QUAL_TAB4__PRE 0x4 + +#define QAM_LC_QUAL_TAB4_VALUE__B 0 +#define QAM_LC_QUAL_TAB4_VALUE__W 5 +#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4 + +#define QAM_LC_QUAL_TAB5__A 0x145001D +#define QAM_LC_QUAL_TAB5__W 5 +#define QAM_LC_QUAL_TAB5__M 0x1F +#define QAM_LC_QUAL_TAB5__PRE 0x5 + +#define QAM_LC_QUAL_TAB5_VALUE__B 0 +#define QAM_LC_QUAL_TAB5_VALUE__W 5 +#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5 + +#define QAM_LC_QUAL_TAB6__A 0x145001E +#define QAM_LC_QUAL_TAB6__W 5 +#define QAM_LC_QUAL_TAB6__M 0x1F +#define QAM_LC_QUAL_TAB6__PRE 0x6 + +#define QAM_LC_QUAL_TAB6_VALUE__B 0 +#define QAM_LC_QUAL_TAB6_VALUE__W 5 +#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6 + +#define QAM_LC_QUAL_TAB8__A 0x145001F +#define QAM_LC_QUAL_TAB8__W 5 +#define QAM_LC_QUAL_TAB8__M 0x1F +#define QAM_LC_QUAL_TAB8__PRE 0x8 + +#define QAM_LC_QUAL_TAB8_VALUE__B 0 +#define QAM_LC_QUAL_TAB8_VALUE__W 5 +#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8 + +#define QAM_LC_QUAL_TAB9__A 0x1450020 +#define QAM_LC_QUAL_TAB9__W 5 +#define QAM_LC_QUAL_TAB9__M 0x1F +#define QAM_LC_QUAL_TAB9__PRE 0x9 + +#define QAM_LC_QUAL_TAB9_VALUE__B 0 +#define QAM_LC_QUAL_TAB9_VALUE__W 5 +#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9 + +#define QAM_LC_QUAL_TAB10__A 0x1450021 +#define QAM_LC_QUAL_TAB10__W 5 +#define QAM_LC_QUAL_TAB10__M 0x1F +#define QAM_LC_QUAL_TAB10__PRE 0xA + +#define QAM_LC_QUAL_TAB10_VALUE__B 0 +#define QAM_LC_QUAL_TAB10_VALUE__W 5 +#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA + +#define QAM_LC_QUAL_TAB12__A 0x1450022 +#define QAM_LC_QUAL_TAB12__W 5 +#define QAM_LC_QUAL_TAB12__M 0x1F +#define QAM_LC_QUAL_TAB12__PRE 0xC + +#define QAM_LC_QUAL_TAB12_VALUE__B 0 +#define QAM_LC_QUAL_TAB12_VALUE__W 5 +#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC + +#define QAM_LC_QUAL_TAB15__A 0x1450023 +#define QAM_LC_QUAL_TAB15__W 5 +#define QAM_LC_QUAL_TAB15__M 0x1F +#define QAM_LC_QUAL_TAB15__PRE 0xF + +#define QAM_LC_QUAL_TAB15_VALUE__B 0 +#define QAM_LC_QUAL_TAB15_VALUE__W 5 +#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF + +#define QAM_LC_QUAL_TAB16__A 0x1450024 +#define QAM_LC_QUAL_TAB16__W 5 +#define QAM_LC_QUAL_TAB16__M 0x1F +#define QAM_LC_QUAL_TAB16__PRE 0x10 + +#define QAM_LC_QUAL_TAB16_VALUE__B 0 +#define QAM_LC_QUAL_TAB16_VALUE__W 5 +#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10 + +#define QAM_LC_QUAL_TAB20__A 0x1450025 +#define QAM_LC_QUAL_TAB20__W 5 +#define QAM_LC_QUAL_TAB20__M 0x1F +#define QAM_LC_QUAL_TAB20__PRE 0x14 + +#define QAM_LC_QUAL_TAB20_VALUE__B 0 +#define QAM_LC_QUAL_TAB20_VALUE__W 5 +#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14 + +#define QAM_LC_QUAL_TAB25__A 0x1450026 +#define QAM_LC_QUAL_TAB25__W 5 +#define QAM_LC_QUAL_TAB25__M 0x1F +#define QAM_LC_QUAL_TAB25__PRE 0x19 + +#define QAM_LC_QUAL_TAB25_VALUE__B 0 +#define QAM_LC_QUAL_TAB25_VALUE__W 5 +#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F +#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19 + +#define QAM_LC_EQ_TIMING__A 0x1450027 +#define QAM_LC_EQ_TIMING__W 10 +#define QAM_LC_EQ_TIMING__M 0x3FF +#define QAM_LC_EQ_TIMING__PRE 0x0 + +#define QAM_LC_EQ_TIMING_OFFS__B 0 +#define QAM_LC_EQ_TIMING_OFFS__W 10 +#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF +#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0 + +#define QAM_LC_LPF_FACTORP__A 0x1450028 +#define QAM_LC_LPF_FACTORP__W 3 +#define QAM_LC_LPF_FACTORP__M 0x7 +#define QAM_LC_LPF_FACTORP__PRE 0x3 + +#define QAM_LC_LPF_FACTORP_FACTOR__B 0 +#define QAM_LC_LPF_FACTORP_FACTOR__W 3 +#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3 + +#define QAM_LC_LPF_FACTORI__A 0x1450029 +#define QAM_LC_LPF_FACTORI__W 3 +#define QAM_LC_LPF_FACTORI__M 0x7 +#define QAM_LC_LPF_FACTORI__PRE 0x3 + +#define QAM_LC_LPF_FACTORI_FACTOR__B 0 +#define QAM_LC_LPF_FACTORI_FACTOR__W 3 +#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7 +#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3 + +#define QAM_LC_RATE_LIMIT__A 0x145002A +#define QAM_LC_RATE_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT__PRE 0x3 + +#define QAM_LC_RATE_LIMIT_LIMIT__B 0 +#define QAM_LC_RATE_LIMIT_LIMIT__W 2 +#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3 +#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3 + +#define QAM_LC_SYMBOL_FREQ__A 0x145002B +#define QAM_LC_SYMBOL_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF + +#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 +#define QAM_LC_SYMBOL_FREQ_FREQ__W 10 +#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF +#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF + +#define QAM_LC_MTA_LENGTH__A 0x145002C +#define QAM_LC_MTA_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH__PRE 0x2 + +#define QAM_LC_MTA_LENGTH_LENGTH__B 0 +#define QAM_LC_MTA_LENGTH_LENGTH__W 2 +#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3 +#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2 + +#define QAM_LC_AMP_ACCU__A 0x145002D +#define QAM_LC_AMP_ACCU__W 14 +#define QAM_LC_AMP_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU__PRE 0x600 + +#define QAM_LC_AMP_ACCU_ACCU__B 0 +#define QAM_LC_AMP_ACCU_ACCU__W 14 +#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF +#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600 + +#define QAM_LC_FREQ_ACCU__A 0x145002E +#define QAM_LC_FREQ_ACCU__W 10 +#define QAM_LC_FREQ_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU__PRE 0x0 + +#define QAM_LC_FREQ_ACCU_ACCU__B 0 +#define QAM_LC_FREQ_ACCU_ACCU__W 10 +#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF +#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU__A 0x145002F +#define QAM_LC_RATE_ACCU__W 10 +#define QAM_LC_RATE_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU__PRE 0x0 + +#define QAM_LC_RATE_ACCU_ACCU__B 0 +#define QAM_LC_RATE_ACCU_ACCU__W 10 +#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF +#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0 + +#define QAM_LC_AMPLITUDE__A 0x1450030 +#define QAM_LC_AMPLITUDE__W 10 +#define QAM_LC_AMPLITUDE__M 0x3FF +#define QAM_LC_AMPLITUDE__PRE 0x0 + +#define QAM_LC_AMPLITUDE_SIZE__B 0 +#define QAM_LC_AMPLITUDE_SIZE__W 10 +#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF +#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0 + +#define QAM_LC_RAD_ERROR__A 0x1450031 +#define QAM_LC_RAD_ERROR__W 10 +#define QAM_LC_RAD_ERROR__M 0x3FF +#define QAM_LC_RAD_ERROR__PRE 0x0 + +#define QAM_LC_RAD_ERROR_SIZE__B 0 +#define QAM_LC_RAD_ERROR_SIZE__W 10 +#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF +#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0 + +#define QAM_LC_FREQ_OFFS__A 0x1450032 +#define QAM_LC_FREQ_OFFS__W 10 +#define QAM_LC_FREQ_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS__PRE 0x0 + +#define QAM_LC_FREQ_OFFS_OFFS__B 0 +#define QAM_LC_FREQ_OFFS_OFFS__W 10 +#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF +#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0 + +#define QAM_LC_PHASE_ERROR__A 0x1450033 +#define QAM_LC_PHASE_ERROR__W 10 +#define QAM_LC_PHASE_ERROR__M 0x3FF +#define QAM_LC_PHASE_ERROR__PRE 0x0 + +#define QAM_LC_PHASE_ERROR_SIZE__B 0 +#define QAM_LC_PHASE_ERROR_SIZE__W 10 +#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF +#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0 + + + +#define QAM_SY_COMM_EXEC__A 0x1470000 +#define QAM_SY_COMM_EXEC__W 2 +#define QAM_SY_COMM_EXEC__M 0x3 +#define QAM_SY_COMM_EXEC__PRE 0x0 +#define QAM_SY_COMM_EXEC_STOP 0x0 +#define QAM_SY_COMM_EXEC_ACTIVE 0x1 +#define QAM_SY_COMM_EXEC_HOLD 0x2 + +#define QAM_SY_COMM_MB__A 0x1470002 +#define QAM_SY_COMM_MB__W 4 +#define QAM_SY_COMM_MB__M 0xF +#define QAM_SY_COMM_MB__PRE 0x0 +#define QAM_SY_COMM_MB_CTL__B 0 +#define QAM_SY_COMM_MB_CTL__W 1 +#define QAM_SY_COMM_MB_CTL__M 0x1 +#define QAM_SY_COMM_MB_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_CTL_OFF 0x0 +#define QAM_SY_COMM_MB_CTL_ON 0x1 +#define QAM_SY_COMM_MB_OBS__B 1 +#define QAM_SY_COMM_MB_OBS__W 1 +#define QAM_SY_COMM_MB_OBS__M 0x2 +#define QAM_SY_COMM_MB_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_OBS_OFF 0x0 +#define QAM_SY_COMM_MB_OBS_ON 0x2 +#define QAM_SY_COMM_MB_MUX_CTL__B 2 +#define QAM_SY_COMM_MB_MUX_CTL__W 1 +#define QAM_SY_COMM_MB_MUX_CTL__M 0x4 +#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4 +#define QAM_SY_COMM_MB_MUX_OBS__B 3 +#define QAM_SY_COMM_MB_MUX_OBS__W 1 +#define QAM_SY_COMM_MB_MUX_OBS__M 0x8 +#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0 +#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8 + +#define QAM_SY_COMM_INT_REQ__A 0x1470003 +#define QAM_SY_COMM_INT_REQ__W 1 +#define QAM_SY_COMM_INT_REQ__M 0x1 +#define QAM_SY_COMM_INT_REQ__PRE 0x0 +#define QAM_SY_COMM_INT_STA__A 0x1470005 +#define QAM_SY_COMM_INT_STA__W 4 +#define QAM_SY_COMM_INT_STA__M 0xF +#define QAM_SY_COMM_INT_STA__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 +#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1 +#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2 +#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4 +#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8 +#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0 + +#define QAM_SY_COMM_INT_MSK__A 0x1470006 +#define QAM_SY_COMM_INT_MSK__W 4 +#define QAM_SY_COMM_INT_MSK__M 0xF +#define QAM_SY_COMM_INT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_COMM_INT_STM__A 0x1470007 +#define QAM_SY_COMM_INT_STM__W 4 +#define QAM_SY_COMM_INT_STM__M 0xF +#define QAM_SY_COMM_INT_STM__PRE 0x0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1 +#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2 +#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4 +#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8 +#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0 + +#define QAM_SY_STATUS__A 0x1470010 +#define QAM_SY_STATUS__W 2 +#define QAM_SY_STATUS__M 0x3 +#define QAM_SY_STATUS__PRE 0x0 + +#define QAM_SY_STATUS_SYNC_STATE__B 0 +#define QAM_SY_STATUS_SYNC_STATE__W 2 +#define QAM_SY_STATUS_SYNC_STATE__M 0x3 +#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0 + + +#define QAM_SY_TIMEOUT__A 0x1470011 +#define QAM_SY_TIMEOUT__W 16 +#define QAM_SY_TIMEOUT__M 0xFFFF +#define QAM_SY_TIMEOUT__PRE 0x3A98 + +#define QAM_SY_SYNC_LWM__A 0x1470012 +#define QAM_SY_SYNC_LWM__W 4 +#define QAM_SY_SYNC_LWM__M 0xF +#define QAM_SY_SYNC_LWM__PRE 0x2 + +#define QAM_SY_SYNC_AWM__A 0x1470013 +#define QAM_SY_SYNC_AWM__W 4 +#define QAM_SY_SYNC_AWM__M 0xF +#define QAM_SY_SYNC_AWM__PRE 0x3 + +#define QAM_SY_SYNC_HWM__A 0x1470014 +#define QAM_SY_SYNC_HWM__W 4 +#define QAM_SY_SYNC_HWM__M 0xF +#define QAM_SY_SYNC_HWM__PRE 0x5 + +#define QAM_SY_UNLOCK__A 0x1470015 +#define QAM_SY_UNLOCK__W 1 +#define QAM_SY_UNLOCK__M 0x1 +#define QAM_SY_UNLOCK__PRE 0x0 +#define QAM_SY_CONTROL_WORD__A 0x1470016 +#define QAM_SY_CONTROL_WORD__W 4 +#define QAM_SY_CONTROL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD__PRE 0x0 + +#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 +#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF +#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0 + + +#define QAM_SY_SP_INV__A 0x1470017 +#define QAM_SY_SP_INV__W 1 +#define QAM_SY_SP_INV__M 0x1 +#define QAM_SY_SP_INV__PRE 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 +#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1 + + + +#define QAM_VD_ISS_RAM__A 0x1480000 + + + +#define QAM_VD_QSS_RAM__A 0x1490000 + + + +#define QAM_VD_SYM_RAM__A 0x14A0000 + + + + + +#define SCU_COMM_EXEC__A 0x800000 +#define SCU_COMM_EXEC__W 2 +#define SCU_COMM_EXEC__M 0x3 +#define SCU_COMM_EXEC__PRE 0x0 +#define SCU_COMM_EXEC_STOP 0x0 +#define SCU_COMM_EXEC_ACTIVE 0x1 +#define SCU_COMM_EXEC_HOLD 0x2 + +#define SCU_COMM_STATE__A 0x800001 +#define SCU_COMM_STATE__W 16 +#define SCU_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE__PRE 0x0 + +#define SCU_COMM_STATE_COMM_STATE__B 0 +#define SCU_COMM_STATE_COMM_STATE__W 16 +#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF +#define SCU_COMM_STATE_COMM_STATE__PRE 0x0 + + + +#define SCU_TOP_COMM_EXEC__A 0x810000 +#define SCU_TOP_COMM_EXEC__W 2 +#define SCU_TOP_COMM_EXEC__M 0x3 +#define SCU_TOP_COMM_EXEC__PRE 0x0 +#define SCU_TOP_COMM_EXEC_STOP 0x0 +#define SCU_TOP_COMM_EXEC_ACTIVE 0x1 +#define SCU_TOP_COMM_EXEC_HOLD 0x2 + + +#define SCU_TOP_COMM_STATE__A 0x810001 +#define SCU_TOP_COMM_STATE__W 16 +#define SCU_TOP_COMM_STATE__M 0xFFFF +#define SCU_TOP_COMM_STATE__PRE 0x0 +#define SCU_TOP_MWAIT_CTR__A 0x810010 +#define SCU_TOP_MWAIT_CTR__W 2 +#define SCU_TOP_MWAIT_CTR__M 0x3 +#define SCU_TOP_MWAIT_CTR__PRE 0x0 + +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0 +#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1 + +#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 +#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2 +#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0 +#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2 + + + +#define SCU_LOW_RAM__A 0x820000 + +#define SCU_LOW_RAM_LOW__B 0 +#define SCU_LOW_RAM_LOW__W 16 +#define SCU_LOW_RAM_LOW__M 0xFFFF +#define SCU_LOW_RAM_LOW__PRE 0x0 + + + +#define SCU_HIGH_RAM__A 0x830000 + +#define SCU_HIGH_RAM_HIGH__B 0 +#define SCU_HIGH_RAM_HIGH__W 16 +#define SCU_HIGH_RAM_HIGH__M 0xFFFF +#define SCU_HIGH_RAM_HIGH__PRE 0x0 + + + + + + +#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF +#define SCU_RAM_DRIVER_DEBUG__W 16 +#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF +#define SCU_RAM_DRIVER_DEBUG__PRE 0x0 + +#define SCU_RAM_SP__A 0x831EC0 +#define SCU_RAM_SP__W 16 +#define SCU_RAM_SP__M 0xFFFF +#define SCU_RAM_SP__PRE 0x0 + +#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1 +#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16 +#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF +#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0 + +#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2 +#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16 +#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF +#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0 + +#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3 +#define SCU_RAM_QAM_NO_ACQ_CNT__W 16 +#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF +#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16 +#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF +#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0 + +#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0 +#define SCU_RAM_GPIO__A 0x831EC7 +#define SCU_RAM_GPIO__W 2 +#define SCU_RAM_GPIO__M 0x3 +#define SCU_RAM_GPIO__PRE 0x0 + +#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 +#define SCU_RAM_GPIO_HW_LOCK_IND__W 1 +#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1 +#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1 + +#define SCU_RAM_GPIO_VSYNC_IND__B 1 +#define SCU_RAM_GPIO_VSYNC_IND__W 1 +#define SCU_RAM_GPIO_VSYNC_IND__M 0x2 +#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0 +#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 +#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF +#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2 + +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0 +#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4 + + +#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA +#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 +#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0 + +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF +#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0 + +#define SCU_RAM_INHIBIT_1__A 0x831ECC +#define SCU_RAM_INHIBIT_1__W 16 +#define SCU_RAM_INHIBIT_1__M 0xFFFF +#define SCU_RAM_INHIBIT_1__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_0__A 0x831ECD +#define SCU_RAM_HTOL_BUF_0__W 16 +#define SCU_RAM_HTOL_BUF_0__M 0xFFFF +#define SCU_RAM_HTOL_BUF_0__PRE 0x0 + +#define SCU_RAM_HTOL_BUF_1__A 0x831ECE +#define SCU_RAM_HTOL_BUF_1__W 16 +#define SCU_RAM_HTOL_BUF_1__M 0xFFFF +#define SCU_RAM_HTOL_BUF_1__PRE 0x0 + +#define SCU_RAM_INHIBIT_2__A 0x831ECF +#define SCU_RAM_INHIBIT_2__W 16 +#define SCU_RAM_INHIBIT_2__M 0xFFFF +#define SCU_RAM_INHIBIT_2__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0 +#define SCU_RAM_TR_SHORT_BUF_0__W 16 +#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1 +#define SCU_RAM_TR_SHORT_BUF_1__W 16 +#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF +#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2 +#define SCU_RAM_TR_LONG_BUF_0__W 16 +#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3 +#define SCU_RAM_TR_LONG_BUF_1__W 16 +#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4 +#define SCU_RAM_TR_LONG_BUF_2__W 16 +#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5 +#define SCU_RAM_TR_LONG_BUF_3__W 16 +#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6 +#define SCU_RAM_TR_LONG_BUF_4__W 16 +#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7 +#define SCU_RAM_TR_LONG_BUF_5__W 16 +#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8 +#define SCU_RAM_TR_LONG_BUF_6__W 16 +#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9 +#define SCU_RAM_TR_LONG_BUF_7__W 16 +#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA +#define SCU_RAM_TR_LONG_BUF_8__W 16 +#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB +#define SCU_RAM_TR_LONG_BUF_9__W 16 +#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC +#define SCU_RAM_TR_LONG_BUF_10__W 16 +#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD +#define SCU_RAM_TR_LONG_BUF_11__W 16 +#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE +#define SCU_RAM_TR_LONG_BUF_12__W 16 +#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF +#define SCU_RAM_TR_LONG_BUF_13__W 16 +#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0 +#define SCU_RAM_TR_LONG_BUF_14__W 16 +#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1 +#define SCU_RAM_TR_LONG_BUF_15__W 16 +#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2 +#define SCU_RAM_TR_LONG_BUF_16__W 16 +#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3 +#define SCU_RAM_TR_LONG_BUF_17__W 16 +#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4 +#define SCU_RAM_TR_LONG_BUF_18__W 16 +#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5 +#define SCU_RAM_TR_LONG_BUF_19__W 16 +#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6 +#define SCU_RAM_TR_LONG_BUF_20__W 16 +#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7 +#define SCU_RAM_TR_LONG_BUF_21__W 16 +#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8 +#define SCU_RAM_TR_LONG_BUF_22__W 16 +#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9 +#define SCU_RAM_TR_LONG_BUF_23__W 16 +#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA +#define SCU_RAM_TR_LONG_BUF_24__W 16 +#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB +#define SCU_RAM_TR_LONG_BUF_25__W 16 +#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC +#define SCU_RAM_TR_LONG_BUF_26__W 16 +#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED +#define SCU_RAM_TR_LONG_BUF_27__W 16 +#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE +#define SCU_RAM_TR_LONG_BUF_28__W 16 +#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF +#define SCU_RAM_TR_LONG_BUF_29__W 16 +#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0 +#define SCU_RAM_TR_LONG_BUF_30__W 16 +#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0 + +#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1 +#define SCU_RAM_TR_LONG_BUF_31__W 16 +#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF +#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0 +#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2 +#define SCU_RAM_ATV_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0 + +#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3 +#define SCU_RAM_ATV_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF +#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF + +#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4 +#define SCU_RAM_ATV_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF +#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5 +#define SCU_RAM_ATV_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0 +#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1 + +#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6 +#define SCU_RAM_ATV_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF +#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL__A 0x831EF7 +#define SCU_RAM_ATV_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 +#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF +#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY__A 0x831EF8 +#define SCU_RAM_ATV_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 +#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF +#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA__A 0x831EF9 +#define SCU_RAM_ATV_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 +#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF +#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF__A 0x831EFA +#define SCU_RAM_ATV_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 +#define SCU_RAM_ATV_BP_REF_BP_REF__W 11 +#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF +#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0 + +#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB +#define SCU_RAM_ATV_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64 + +#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC +#define SCU_RAM_ATV_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF +#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104 + +#define SCU_RAM_ATV_BP_CNT__A 0x831EFD +#define SCU_RAM_ATV_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 +#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF +#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE +#define SCU_RAM_ATV_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF +#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF +#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445 + +#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00 +#define SCU_RAM_ATV_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223 + +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223 + + +#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01 +#define SCU_RAM_OFDM_AGC_POW_TGT__W 15 +#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF +#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848 + +#define SCU_RAM_OFDM_RSV_01__A 0x831F02 +#define SCU_RAM_OFDM_RSV_01__W 16 +#define SCU_RAM_OFDM_RSV_01__M 0xFFFF +#define SCU_RAM_OFDM_RSV_01__PRE 0x0 + +#define SCU_RAM_OFDM_RSV_02__A 0x831F03 +#define SCU_RAM_OFDM_RSV_02__W 16 +#define SCU_RAM_OFDM_RSV_02__M 0xFFFF +#define SCU_RAM_OFDM_RSV_02__PRE 0x0 +#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04 +#define SCU_RAM_FEC_PRE_RS_BER__W 16 +#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0 + +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16 +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF +#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07 +#define SCU_RAM_ATV_VSYNC_PERIOD__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16 +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF +#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_FREE_7944__A 0x831F08 +#define SCU_RAM_FREE_7944__W 16 +#define SCU_RAM_FREE_7944__M 0xFFFF +#define SCU_RAM_FREE_7944__PRE 0x0 + +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7945__A 0x831F09 +#define SCU_RAM_FREE_7945__W 16 +#define SCU_RAM_FREE_7945__M 0xFFFF +#define SCU_RAM_FREE_7945__PRE 0x0 + +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7946__A 0x831F0A +#define SCU_RAM_FREE_7946__W 16 +#define SCU_RAM_FREE_7946__M 0xFFFF +#define SCU_RAM_FREE_7946__PRE 0x0 + +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7947__A 0x831F0B +#define SCU_RAM_FREE_7947__W 16 +#define SCU_RAM_FREE_7947__M 0xFFFF +#define SCU_RAM_FREE_7947__PRE 0x0 + +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7948__A 0x831F0C +#define SCU_RAM_FREE_7948__W 16 +#define SCU_RAM_FREE_7948__M 0xFFFF +#define SCU_RAM_FREE_7948__PRE 0x0 + +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7949__A 0x831F0D +#define SCU_RAM_FREE_7949__W 16 +#define SCU_RAM_FREE_7949__M 0xFFFF +#define SCU_RAM_FREE_7949__PRE 0x0 + +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7950__A 0x831F0E +#define SCU_RAM_FREE_7950__W 16 +#define SCU_RAM_FREE_7950__M 0xFFFF +#define SCU_RAM_FREE_7950__PRE 0x0 + +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7951__A 0x831F0F +#define SCU_RAM_FREE_7951__W 16 +#define SCU_RAM_FREE_7951__M 0xFFFF +#define SCU_RAM_FREE_7951__PRE 0x0 + +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7952__A 0x831F10 +#define SCU_RAM_FREE_7952__W 16 +#define SCU_RAM_FREE_7952__M 0xFFFF +#define SCU_RAM_FREE_7952__PRE 0x0 + +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7953__A 0x831F11 +#define SCU_RAM_FREE_7953__W 16 +#define SCU_RAM_FREE_7953__M 0xFFFF +#define SCU_RAM_FREE_7953__PRE 0x0 + +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7954__A 0x831F12 +#define SCU_RAM_FREE_7954__W 16 +#define SCU_RAM_FREE_7954__M 0xFFFF +#define SCU_RAM_FREE_7954__PRE 0x0 + +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7955__A 0x831F13 +#define SCU_RAM_FREE_7955__W 16 +#define SCU_RAM_FREE_7955__M 0xFFFF +#define SCU_RAM_FREE_7955__PRE 0x0 + +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0 + + +#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14 +#define SCU_RAM_ADC_COMP_CONTROL__W 3 +#define SCU_RAM_ADC_COMP_CONTROL__M 0x7 +#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0 +#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2 +#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3 + + +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32 + +#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16 +#define SCU_RAM_AGC_KI_CYCCNT__W 16 +#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 +#define SCU_RAM_AGC_KI_CYCLEN__W 16 +#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 +#define SCU_RAM_AGC_SNS_CYCLEN__W 16 +#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF + +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF +#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01 + +#define SCU_RAM_AGC_RF_MAX__A 0x831F1B +#define SCU_RAM_AGC_RF_MAX__W 15 +#define SCU_RAM_AGC_RF_MAX__M 0x7FFF +#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF +#define SCU_RAM_FREE_7964__A 0x831F1C +#define SCU_RAM_FREE_7964__W 16 +#define SCU_RAM_FREE_7964__M 0xFFFF +#define SCU_RAM_FREE_7964__PRE 0x0 + +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7965__A 0x831F1D +#define SCU_RAM_FREE_7965__W 16 +#define SCU_RAM_FREE_7965__M 0xFFFF +#define SCU_RAM_FREE_7965__PRE 0x0 + +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7966__A 0x831F1E +#define SCU_RAM_FREE_7966__W 16 +#define SCU_RAM_FREE_7966__M 0xFFFF +#define SCU_RAM_FREE_7966__PRE 0x0 + +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7967__A 0x831F1F +#define SCU_RAM_FREE_7967__W 16 +#define SCU_RAM_FREE_7967__M 0xFFFF +#define SCU_RAM_FREE_7967__PRE 0x0 + +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20 +#define SCU_RAM_QAM_PARAM_MIRRORING__W 8 +#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF +#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4 + +#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21 +#define SCU_RAM_QAM_PARAM_OPTIONS__W 8 +#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF +#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1 + +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2 + +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0 +#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10 + +#define SCU_RAM_FREE_7970__A 0x831F22 +#define SCU_RAM_FREE_7970__W 16 +#define SCU_RAM_FREE_7970__M 0xFFFF +#define SCU_RAM_FREE_7970__PRE 0x0 + +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_FREE_7971__A 0x831F23 +#define SCU_RAM_FREE_7971__W 16 +#define SCU_RAM_FREE_7971__M 0xFFFF +#define SCU_RAM_FREE_7971__PRE 0x0 + +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16 +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF +#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG__A 0x831F24 +#define SCU_RAM_AGC_CONFIG__W 16 +#define SCU_RAM_AGC_CONFIG__M 0xFFFF +#define SCU_RAM_AGC_CONFIG__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 +#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 +#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4 +#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 +#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0 + +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 +#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0 + +#define SCU_RAM_AGC_KI__A 0x831F25 +#define SCU_RAM_AGC_KI__W 15 +#define SCU_RAM_AGC_KI__M 0x7FFF +#define SCU_RAM_AGC_KI__PRE 0x22A + +#define SCU_RAM_AGC_KI_DGAIN__B 0 +#define SCU_RAM_AGC_KI_DGAIN__W 4 +#define SCU_RAM_AGC_KI_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA + +#define SCU_RAM_AGC_KI_RF__B 4 +#define SCU_RAM_AGC_KI_RF__W 4 +#define SCU_RAM_AGC_KI_RF__M 0xF0 +#define SCU_RAM_AGC_KI_RF__PRE 0x20 + +#define SCU_RAM_AGC_KI_IF__B 8 +#define SCU_RAM_AGC_KI_IF__W 4 +#define SCU_RAM_AGC_KI_IF__M 0xF00 +#define SCU_RAM_AGC_KI_IF__PRE 0x200 + +#define SCU_RAM_AGC_KI_RED__A 0x831F26 +#define SCU_RAM_AGC_KI_RED__W 6 +#define SCU_RAM_AGC_KI_RED__M 0x3F +#define SCU_RAM_AGC_KI_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 +#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 +#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3 +#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC +#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0 + +#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 +#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0 + + +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF +#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 +#define SCU_RAM_AGC_KI_MINGAIN__W 16 +#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000 + +#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 +#define SCU_RAM_AGC_KI_MAXGAIN__W 16 +#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0 + +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF +#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0 +#define SCU_RAM_AGC_KI_MIN__A 0x831F2B +#define SCU_RAM_AGC_KI_MIN__W 12 +#define SCU_RAM_AGC_KI_MIN__M 0xFFF +#define SCU_RAM_AGC_KI_MIN__PRE 0x111 + +#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1 + +#define SCU_RAM_AGC_KI_MIN_RF__B 4 +#define SCU_RAM_AGC_KI_MIN_RF__W 4 +#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10 + +#define SCU_RAM_AGC_KI_MIN_IF__B 8 +#define SCU_RAM_AGC_KI_MIN_IF__W 4 +#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100 + +#define SCU_RAM_AGC_KI_MAX__A 0x831F2C +#define SCU_RAM_AGC_KI_MAX__W 12 +#define SCU_RAM_AGC_KI_MAX__M 0xFFF +#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF + +#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 +#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 +#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF +#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF + +#define SCU_RAM_AGC_KI_MAX_RF__B 4 +#define SCU_RAM_AGC_KI_MAX_RF__W 4 +#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0 +#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0 + +#define SCU_RAM_AGC_KI_MAX_IF__B 8 +#define SCU_RAM_AGC_KI_MAX_IF__W 4 +#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00 +#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00 + + +#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D +#define SCU_RAM_AGC_CLP_SUM__W 16 +#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM__PRE 0x0 + +#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E +#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 +#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F +#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 +#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 +#define SCU_RAM_AGC_CLP_CYCLEN__W 16 +#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4 + +#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 +#define SCU_RAM_AGC_CLP_CYCCNT__W 16 +#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 +#define SCU_RAM_AGC_CLP_DIR_TO__W 8 +#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 +#define SCU_RAM_AGC_CLP_DIR_WD__W 8 +#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF +#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 +#define SCU_RAM_AGC_CLP_DIR_STP__W 16 +#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_SNS_SUM__A 0x831F35 +#define SCU_RAM_AGC_SNS_SUM__W 16 +#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM__PRE 0x0 + +#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 +#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 +#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8 + +#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 +#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 +#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF +#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400 + +#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 +#define SCU_RAM_AGC_SNS_CYCCNT__W 16 +#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF +#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 +#define SCU_RAM_AGC_SNS_DIR_TO__W 8 +#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC + +#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A +#define SCU_RAM_AGC_SNS_DIR_WD__W 8 +#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF +#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0 + +#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B +#define SCU_RAM_AGC_SNS_DIR_STP__W 16 +#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF +#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1 + +#define SCU_RAM_AGC_INGAIN__A 0x831F3C +#define SCU_RAM_AGC_INGAIN__W 16 +#define SCU_RAM_AGC_INGAIN__M 0xFFFF +#define SCU_RAM_AGC_INGAIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D +#define SCU_RAM_AGC_INGAIN_TGT__W 15 +#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E +#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708 + +#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F +#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 +#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF + +#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 +#define SCU_RAM_AGC_IF_IACCU_HI__W 16 +#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 +#define SCU_RAM_AGC_IF_IACCU_LO__W 8 +#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0 + +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF +#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C + +#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 +#define SCU_RAM_AGC_RF_IACCU_HI__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 +#define SCU_RAM_AGC_RF_IACCU_LO__W 8 +#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF +#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0 + +#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 +#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF +#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0 +#define SCU_RAM_ATV_STANDARD__A 0x831F48 +#define SCU_RAM_ATV_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD__PRE 0x2 + +#define SCU_RAM_ATV_STANDARD_STANDARD__B 0 +#define SCU_RAM_ATV_STANDARD_STANDARD__W 12 +#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF +#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2 +#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103 +#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3 +#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4 +#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9 +#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109 +#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA +#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40 + +#define SCU_RAM_ATV_DETECT__A 0x831F49 +#define SCU_RAM_ATV_DETECT__W 1 +#define SCU_RAM_ATV_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT__PRE 0x0 + +#define SCU_RAM_ATV_DETECT_DETECT__B 0 +#define SCU_RAM_ATV_DETECT_DETECT__W 1 +#define SCU_RAM_ATV_DETECT_DETECT__M 0x1 +#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0 +#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1 + +#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A +#define SCU_RAM_ATV_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8 +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF +#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F + +#define SCU_RAM_ATV_LOCK__A 0x831F4B +#define SCU_RAM_ATV_LOCK__W 2 +#define SCU_RAM_ATV_LOCK__M 0x3 +#define SCU_RAM_ATV_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0 +#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1 + +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0 +#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2 + +#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C +#define SCU_RAM_ATV_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11 +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF +#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0 + +#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D +#define SCU_RAM_ATV_AGC_MODE__W 8 +#define SCU_RAM_ATV_AGC_MODE__M 0xFF +#define SCU_RAM_ATV_AGC_MODE__PRE 0x50 + +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0 +#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4 + +#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8 +#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8 + +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10 +#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20 + +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40 + +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0 +#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80 + + +#define SCU_RAM_ATV_RSV_01__A 0x831F4E +#define SCU_RAM_ATV_RSV_01__W 16 +#define SCU_RAM_ATV_RSV_01__M 0xFFFF +#define SCU_RAM_ATV_RSV_01__PRE 0x0 + +#define SCU_RAM_ATV_RSV_02__A 0x831F4F +#define SCU_RAM_ATV_RSV_02__W 16 +#define SCU_RAM_ATV_RSV_02__M 0xFFFF +#define SCU_RAM_ATV_RSV_02__PRE 0x0 + +#define SCU_RAM_ATV_RSV_03__A 0x831F50 +#define SCU_RAM_ATV_RSV_03__W 16 +#define SCU_RAM_ATV_RSV_03__M 0xFFFF +#define SCU_RAM_ATV_RSV_03__PRE 0x0 + +#define SCU_RAM_ATV_RSV_04__A 0x831F51 +#define SCU_RAM_ATV_RSV_04__W 16 +#define SCU_RAM_ATV_RSV_04__M 0xFFFF +#define SCU_RAM_ATV_RSV_04__PRE 0x0 +#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52 +#define SCU_RAM_ATV_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8 +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF +#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA + +#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53 +#define SCU_RAM_ATV_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC + +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314 +#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A + +#define SCU_RAM_ATV_ACT_AMX__A 0x831F54 +#define SCU_RAM_ATV_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11 +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF +#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI__A 0x831F55 +#define SCU_RAM_ATV_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11 +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF +#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56 +#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16 +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57 +#define SCU_RAM_ATV_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0 + +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16 +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF +#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_07__A 0x831F58 +#define SCU_RAM_ATV_RSV_07__W 16 +#define SCU_RAM_ATV_RSV_07__M 0xFFFF +#define SCU_RAM_ATV_RSV_07__PRE 0x0 + +#define SCU_RAM_ATV_RSV_08__A 0x831F59 +#define SCU_RAM_ATV_RSV_08__W 16 +#define SCU_RAM_ATV_RSV_08__M 0xFFFF +#define SCU_RAM_ATV_RSV_08__PRE 0x0 + +#define SCU_RAM_ATV_RSV_09__A 0x831F5A +#define SCU_RAM_ATV_RSV_09__W 16 +#define SCU_RAM_ATV_RSV_09__M 0xFFFF +#define SCU_RAM_ATV_RSV_09__PRE 0x0 + +#define SCU_RAM_ATV_RSV_10__A 0x831F5B +#define SCU_RAM_ATV_RSV_10__W 16 +#define SCU_RAM_ATV_RSV_10__M 0xFFFF +#define SCU_RAM_ATV_RSV_10__PRE 0x0 + +#define SCU_RAM_ATV_RSV_11__A 0x831F5C +#define SCU_RAM_ATV_RSV_11__W 16 +#define SCU_RAM_ATV_RSV_11__M 0xFFFF +#define SCU_RAM_ATV_RSV_11__PRE 0x0 + +#define SCU_RAM_ATV_RSV_12__A 0x831F5D +#define SCU_RAM_ATV_RSV_12__W 16 +#define SCU_RAM_ATV_RSV_12__M 0xFFFF +#define SCU_RAM_ATV_RSV_12__PRE 0x0 +#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E +#define SCU_RAM_ATV_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16 +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF +#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000 + +#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F +#define SCU_RAM_ATV_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0 + +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8 +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF +#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0 + + +#define SCU_RAM_ATV_RSV_13__A 0x831F60 +#define SCU_RAM_ATV_RSV_13__W 16 +#define SCU_RAM_ATV_RSV_13__M 0xFFFF +#define SCU_RAM_ATV_RSV_13__PRE 0x0 + +#define SCU_RAM_ATV_RSV_14__A 0x831F61 +#define SCU_RAM_ATV_RSV_14__W 16 +#define SCU_RAM_ATV_RSV_14__M 0xFFFF +#define SCU_RAM_ATV_RSV_14__PRE 0x0 + +#define SCU_RAM_ATV_RSV_15__A 0x831F62 +#define SCU_RAM_ATV_RSV_15__W 16 +#define SCU_RAM_ATV_RSV_15__M 0xFFFF +#define SCU_RAM_ATV_RSV_15__PRE 0x0 + +#define SCU_RAM_ATV_RSV_16__A 0x831F63 +#define SCU_RAM_ATV_RSV_16__W 16 +#define SCU_RAM_ATV_RSV_16__M 0xFFFF +#define SCU_RAM_ATV_RSV_16__PRE 0x0 +#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64 +#define SCU_RAM_ATV_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8 +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF +#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7 + +#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65 +#define SCU_RAM_ATV_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80 + +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11 +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF +#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80 + + +#define SCU_RAM_ATV_RSV_17__A 0x831F66 +#define SCU_RAM_ATV_RSV_17__W 16 +#define SCU_RAM_ATV_RSV_17__M 0xFFFF +#define SCU_RAM_ATV_RSV_17__PRE 0x0 + +#define SCU_RAM_ATV_RSV_18__A 0x831F67 +#define SCU_RAM_ATV_RSV_18__W 16 +#define SCU_RAM_ATV_RSV_18__M 0xFFFF +#define SCU_RAM_ATV_RSV_18__PRE 0x0 + +#define SCU_RAM_ATV_RATE_OFS__A 0x831F68 +#define SCU_RAM_ATV_RATE_OFS__W 12 +#define SCU_RAM_ATV_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_LO_INCR__A 0x831F69 +#define SCU_RAM_ATV_LO_INCR__W 12 +#define SCU_RAM_ATV_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A +#define SCU_RAM_ATV_IIR_CRIT__W 12 +#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF +#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0 + +#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B +#define SCU_RAM_ATV_DEF_RATE_OFS__W 12 +#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF +#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0 + +#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C +#define SCU_RAM_ATV_DEF_LO_INCR__W 12 +#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF +#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0 + +#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D +#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1 +#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0 +#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E +#define SCU_RAM_ATV_MOD_CONTROL__W 12 +#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0 + +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0 + +#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F +#define SCU_RAM_ATV_PAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667 + +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667 + +#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70 +#define SCU_RAM_ATV_BPC_KI_MAX__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337 + +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337 + +#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71 +#define SCU_RAM_ATV_NAGC_KI_MAX__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12 +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447 + +#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72 +#define SCU_RAM_ATV_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12 +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF +#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225 + +#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73 +#define SCU_RAM_ATV_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14 + +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14 +#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28 + +#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74 +#define SCU_RAM_QAM_PARAM_ANNEX__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2 +#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5 + +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE +#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79 +#define SCU_RAM_QAM_EQ_CENTERTAP__W 16 +#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF +#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13 + +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8 +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF +#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13 + +#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A +#define SCU_RAM_QAM_WR_RSV_0__W 16 +#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D +#define SCU_RAM_QAM_WR_RSV_5__W 16 +#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E +#define SCU_RAM_QAM_WR_RSV_6__W 16 +#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F +#define SCU_RAM_QAM_WR_RSV_7__W 16 +#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80 +#define SCU_RAM_QAM_WR_RSV_8__W 16 +#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81 +#define SCU_RAM_QAM_WR_RSV_9__W 16 +#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82 +#define SCU_RAM_QAM_WR_RSV_10__W 16 +#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83 +#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258 + +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258 +#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16 +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16 +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16 +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B +#define SCU_RAM_QAM_FSM_STATE_TGT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D +#define SCU_RAM_QAM_FSM_ATH__W 16 +#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH__PRE 0x0 + +#define SCU_RAM_QAM_FSM_ATH_BIT__B 0 +#define SCU_RAM_QAM_FSM_ATH_BIT__W 16 +#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E +#define SCU_RAM_QAM_FSM_RTH__W 16 +#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B + +#define SCU_RAM_QAM_FSM_RTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_RTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32 +#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D + +#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F +#define SCU_RAM_QAM_FSM_FTH__W 16 +#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C + +#define SCU_RAM_QAM_FSM_FTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_FTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14 +#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14 + +#define SCU_RAM_QAM_FSM_PTH__A 0x831F90 +#define SCU_RAM_QAM_FSM_PTH__W 16 +#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH__PRE 0x64 + +#define SCU_RAM_QAM_FSM_PTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_PTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64 +#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64 + +#define SCU_RAM_QAM_FSM_MTH__A 0x831F91 +#define SCU_RAM_QAM_FSM_MTH__W 16 +#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E + +#define SCU_RAM_QAM_FSM_MTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_MTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C +#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50 + +#define SCU_RAM_QAM_FSM_CTH__A 0x831F92 +#define SCU_RAM_QAM_FSM_CTH__W 16 +#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH__PRE 0x50 + +#define SCU_RAM_QAM_FSM_CTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_CTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0 +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C + +#define SCU_RAM_QAM_FSM_QTH__A 0x831F93 +#define SCU_RAM_QAM_FSM_QTH__W 16 +#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH__PRE 0x96 + +#define SCU_RAM_QAM_FSM_QTH_BIT__B 0 +#define SCU_RAM_QAM_FSM_QTH_BIT__W 16 +#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3 +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C +#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96 + +#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 +#define SCU_RAM_QAM_FSM_RATE_LIM__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28 + +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46 +#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 +#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF + +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8 +#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28 + +#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 +#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4 + +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7 +#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6 + +#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 +#define SCU_RAM_QAM_LC_CA_COARSE__W 16 +#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98 +#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28 + +#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 +#define SCU_RAM_QAM_LC_CA_FINE__W 16 +#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF + +#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF + +#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A +#define SCU_RAM_QAM_LC_CP_COARSE__W 16 +#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64 + +#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B +#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C +#define SCU_RAM_QAM_LC_CP_FINE__W 16 +#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D +#define SCU_RAM_QAM_LC_CI_COARSE__W 16 +#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32 + +#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E +#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E + +#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F +#define SCU_RAM_QAM_LC_CI_FINE__W 16 +#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 +#define SCU_RAM_QAM_LC_EP_COARSE__W 16 +#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 +#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18 + +#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 +#define SCU_RAM_QAM_LC_EP_FINE__W 16 +#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 +#define SCU_RAM_QAM_LC_EI_COARSE__W 16 +#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 +#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 +#define SCU_RAM_QAM_LC_EI_FINE__W 16 +#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC + +#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC + +#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 +#define SCU_RAM_QAM_LC_CF_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30 + +#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 +#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19 + +#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 +#define SCU_RAM_QAM_LC_CF_FINE__W 16 +#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10 + +#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 +#define SCU_RAM_QAM_LC_CF1_COARSE__W 16 +#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA +#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16 +#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA + +#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB +#define SCU_RAM_QAM_LC_CF1_FINE__W 16 +#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF +#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5 + +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8 +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF +#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5 + +#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC +#define SCU_RAM_QAM_SL_SIG_POWER__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00 + +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16 +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF +#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00 + +#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD +#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418 + +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814 +#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE + +#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE +#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A + +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6 +#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34 + +#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF +#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4 + +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4 +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA +#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF + +#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 +#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909 +#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283 + +#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 +#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1 + +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00 +#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D + +#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 +#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9 + +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46 +#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19 + +#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3 +#define SCU_RAM_QAM_CTL_ENA__W 16 +#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF +#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF + +#define SCU_RAM_QAM_CTL_ENA_AMP__B 0 +#define SCU_RAM_QAM_CTL_ENA_AMP__W 1 +#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1 +#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1 + +#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1 +#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2 +#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2 + +#define SCU_RAM_QAM_CTL_ENA_EQU__B 2 +#define SCU_RAM_QAM_CTL_ENA_EQU__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4 +#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4 + +#define SCU_RAM_QAM_CTL_ENA_SLC__B 3 +#define SCU_RAM_QAM_CTL_ENA_SLC__W 1 +#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8 +#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8 + +#define SCU_RAM_QAM_CTL_ENA_LC__B 4 +#define SCU_RAM_QAM_CTL_ENA_LC__W 1 +#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10 +#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10 + +#define SCU_RAM_QAM_CTL_ENA_AGC__B 5 +#define SCU_RAM_QAM_CTL_ENA_AGC__W 1 +#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20 +#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20 + +#define SCU_RAM_QAM_CTL_ENA_FEC__B 6 +#define SCU_RAM_QAM_CTL_ENA_FEC__W 1 +#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40 +#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40 + +#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7 +#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1 +#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80 +#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80 + +#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100 +#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100 + +#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200 +#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200 + +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400 +#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400 + +#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4 +#define SCU_RAM_QAM_WR_RSV_1__W 16 +#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5 +#define SCU_RAM_QAM_WR_RSV_2__W 16 +#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6 +#define SCU_RAM_QAM_WR_RSV_3__W 16 +#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6 +#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1 + +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11 +#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE + +#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9 +#define SCU_RAM_QAM_RD_RSV_4__W 16 +#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED__A 0x831FBA +#define SCU_RAM_QAM_LOCKED__W 16 +#define SCU_RAM_QAM_LOCKED__M 0xFFFF +#define SCU_RAM_QAM_LOCKED__PRE 0x0 + +#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8 +#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF +#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6 +#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7 + +#define SCU_RAM_QAM_LOCKED_LOCKED__B 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__W 8 +#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00 +#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0 +#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 +#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 +#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 + +#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB +#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000 +#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC +#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16 +#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20 +#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40 +#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80 +#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200 +#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000 +#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD +#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE +#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0 + +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16 +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF +#define SCU_RAM_QAM_TASKLETS_SCHED__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0 +#define SCU_RAM_QAM_TASKLETS_RUN__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0 + +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16 +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF +#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0 + +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16 +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF +#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3 +#define SCU_RAM_QAM_RD_RSV_5__W 16 +#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4 +#define SCU_RAM_QAM_RD_RSV_6__W 16 +#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5 +#define SCU_RAM_QAM_RD_RSV_7__W 16 +#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6 +#define SCU_RAM_QAM_RD_RSV_8__W 16 +#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7 +#define SCU_RAM_QAM_RD_RSV_9__W 16 +#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8 +#define SCU_RAM_QAM_RD_RSV_10__W 16 +#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0 + +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16 +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF +#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA +#define SCU_RAM_QAM_FSM_STATE__W 4 +#define SCU_RAM_QAM_FSM_STATE__M 0xF +#define SCU_RAM_QAM_FSM_STATE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB +#define SCU_RAM_QAM_FSM_STATE_NEW__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF +#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0 + +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000 +#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD +#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46 + +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46 + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E + +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16 +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF +#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E + +#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF +#define SCU_RAM_QAM_ERR_STATE__W 4 +#define SCU_RAM_QAM_ERR_STATE__M 0xF +#define SCU_RAM_QAM_ERR_STATE__PRE 0x0 + +#define SCU_RAM_QAM_ERR_STATE_BIT__B 0 +#define SCU_RAM_QAM_ERR_STATE_BIT__W 4 +#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF +#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3 +#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6 +#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF +#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0 + +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1 +#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1 +#define SCU_RAM_QAM_EQ_LOCK__W 1 +#define SCU_RAM_QAM_EQ_LOCK__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0 + +#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0 +#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1 +#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2 +#define SCU_RAM_QAM_EQ_STATE__W 16 +#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE__PRE 0x0 + +#define SCU_RAM_QAM_EQ_STATE_BIT__B 0 +#define SCU_RAM_QAM_EQ_STATE_BIT__W 16 +#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF +#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3 +#define SCU_RAM_QAM_RD_RSV_0__W 16 +#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4 +#define SCU_RAM_QAM_RD_RSV_1__W 16 +#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5 +#define SCU_RAM_QAM_RD_RSV_2__W 16 +#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6 +#define SCU_RAM_QAM_RD_RSV_3__W 16 +#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0 + +#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0 +#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16 +#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF +#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0 + + +#define SCU_RAM_FREE_8151__A 0x831FD7 +#define SCU_RAM_FREE_8151__W 16 +#define SCU_RAM_FREE_8151__M 0xFFFF +#define SCU_RAM_FREE_8151__PRE 0x0 + +#define SCU_RAM_FREE_8152__A 0x831FD8 +#define SCU_RAM_FREE_8152__W 16 +#define SCU_RAM_FREE_8152__M 0xFFFF +#define SCU_RAM_FREE_8152__PRE 0x0 + +#define SCU_RAM_FREE_8153__A 0x831FD9 +#define SCU_RAM_FREE_8153__W 16 +#define SCU_RAM_FREE_8153__M 0xFFFF +#define SCU_RAM_FREE_8153__PRE 0x0 + +#define SCU_RAM_FREE_8154__A 0x831FDA +#define SCU_RAM_FREE_8154__W 16 +#define SCU_RAM_FREE_8154__M 0xFFFF +#define SCU_RAM_FREE_8154__PRE 0x0 + +#define SCU_RAM_FREE_8155__A 0x831FDB +#define SCU_RAM_FREE_8155__W 16 +#define SCU_RAM_FREE_8155__M 0xFFFF +#define SCU_RAM_FREE_8155__PRE 0x0 + +#define SCU_RAM_FREE_8156__A 0x831FDC +#define SCU_RAM_FREE_8156__W 16 +#define SCU_RAM_FREE_8156__M 0xFFFF +#define SCU_RAM_FREE_8156__PRE 0x0 + +#define SCU_RAM_FREE_8157__A 0x831FDD +#define SCU_RAM_FREE_8157__W 16 +#define SCU_RAM_FREE_8157__M 0xFFFF +#define SCU_RAM_FREE_8157__PRE 0x0 + +#define SCU_RAM_FREE_8158__A 0x831FDE +#define SCU_RAM_FREE_8158__W 16 +#define SCU_RAM_FREE_8158__M 0xFFFF +#define SCU_RAM_FREE_8158__PRE 0x0 + +#define SCU_RAM_FREE_8159__A 0x831FDF +#define SCU_RAM_FREE_8159__W 16 +#define SCU_RAM_FREE_8159__M 0xFFFF +#define SCU_RAM_FREE_8159__PRE 0x0 + +#define SCU_RAM_FREE_8160__A 0x831FE0 +#define SCU_RAM_FREE_8160__W 16 +#define SCU_RAM_FREE_8160__M 0xFFFF +#define SCU_RAM_FREE_8160__PRE 0x0 + +#define SCU_RAM_FREE_8161__A 0x831FE1 +#define SCU_RAM_FREE_8161__W 16 +#define SCU_RAM_FREE_8161__M 0xFFFF +#define SCU_RAM_FREE_8161__PRE 0x0 + +#define SCU_RAM_FREE_8162__A 0x831FE2 +#define SCU_RAM_FREE_8162__W 16 +#define SCU_RAM_FREE_8162__M 0xFFFF +#define SCU_RAM_FREE_8162__PRE 0x0 + +#define SCU_RAM_FREE_8163__A 0x831FE3 +#define SCU_RAM_FREE_8163__W 16 +#define SCU_RAM_FREE_8163__M 0xFFFF +#define SCU_RAM_FREE_8163__PRE 0x0 + +#define SCU_RAM_FREE_8164__A 0x831FE4 +#define SCU_RAM_FREE_8164__W 16 +#define SCU_RAM_FREE_8164__M 0xFFFF +#define SCU_RAM_FREE_8164__PRE 0x0 + +#define SCU_RAM_FREE_8165__A 0x831FE5 +#define SCU_RAM_FREE_8165__W 16 +#define SCU_RAM_FREE_8165__M 0xFFFF +#define SCU_RAM_FREE_8165__PRE 0x0 + +#define SCU_RAM_FREE_8166__A 0x831FE6 +#define SCU_RAM_FREE_8166__W 16 +#define SCU_RAM_FREE_8166__M 0xFFFF +#define SCU_RAM_FREE_8166__PRE 0x0 + +#define SCU_RAM_FREE_8167__A 0x831FE7 +#define SCU_RAM_FREE_8167__W 16 +#define SCU_RAM_FREE_8167__M 0xFFFF +#define SCU_RAM_FREE_8167__PRE 0x0 + +#define SCU_RAM_FREE_8168__A 0x831FE8 +#define SCU_RAM_FREE_8168__W 16 +#define SCU_RAM_FREE_8168__M 0xFFFF +#define SCU_RAM_FREE_8168__PRE 0x0 + +#define SCU_RAM_FREE_8169__A 0x831FE9 +#define SCU_RAM_FREE_8169__W 16 +#define SCU_RAM_FREE_8169__M 0xFFFF +#define SCU_RAM_FREE_8169__PRE 0x0 + +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF +#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E + +#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB +#define SCU_RAM_DRIVER_VER_HI__W 16 +#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF +#define SCU_RAM_DRIVER_VER_HI__PRE 0x0 + +#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC +#define SCU_RAM_DRIVER_VER_LO__W 16 +#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF +#define SCU_RAM_DRIVER_VER_LO__PRE 0x0 + +#define SCU_RAM_PARAM_15__A 0x831FED +#define SCU_RAM_PARAM_15__W 16 +#define SCU_RAM_PARAM_15__M 0xFFFF +#define SCU_RAM_PARAM_15__PRE 0x0 + +#define SCU_RAM_PARAM_14__A 0x831FEE +#define SCU_RAM_PARAM_14__W 16 +#define SCU_RAM_PARAM_14__M 0xFFFF +#define SCU_RAM_PARAM_14__PRE 0x0 + +#define SCU_RAM_PARAM_13__A 0x831FEF +#define SCU_RAM_PARAM_13__W 16 +#define SCU_RAM_PARAM_13__M 0xFFFF +#define SCU_RAM_PARAM_13__PRE 0x0 + +#define SCU_RAM_PARAM_12__A 0x831FF0 +#define SCU_RAM_PARAM_12__W 16 +#define SCU_RAM_PARAM_12__M 0xFFFF +#define SCU_RAM_PARAM_12__PRE 0x0 + +#define SCU_RAM_PARAM_11__A 0x831FF1 +#define SCU_RAM_PARAM_11__W 16 +#define SCU_RAM_PARAM_11__M 0xFFFF +#define SCU_RAM_PARAM_11__PRE 0x0 + +#define SCU_RAM_PARAM_10__A 0x831FF2 +#define SCU_RAM_PARAM_10__W 16 +#define SCU_RAM_PARAM_10__M 0xFFFF +#define SCU_RAM_PARAM_10__PRE 0x0 + +#define SCU_RAM_PARAM_9__A 0x831FF3 +#define SCU_RAM_PARAM_9__W 16 +#define SCU_RAM_PARAM_9__M 0xFFFF +#define SCU_RAM_PARAM_9__PRE 0x0 + +#define SCU_RAM_PARAM_8__A 0x831FF4 +#define SCU_RAM_PARAM_8__W 16 +#define SCU_RAM_PARAM_8__M 0xFFFF +#define SCU_RAM_PARAM_8__PRE 0x0 + +#define SCU_RAM_PARAM_7__A 0x831FF5 +#define SCU_RAM_PARAM_7__W 16 +#define SCU_RAM_PARAM_7__M 0xFFFF +#define SCU_RAM_PARAM_7__PRE 0x0 + +#define SCU_RAM_PARAM_6__A 0x831FF6 +#define SCU_RAM_PARAM_6__W 16 +#define SCU_RAM_PARAM_6__M 0xFFFF +#define SCU_RAM_PARAM_6__PRE 0x0 + +#define SCU_RAM_PARAM_5__A 0x831FF7 +#define SCU_RAM_PARAM_5__W 16 +#define SCU_RAM_PARAM_5__M 0xFFFF +#define SCU_RAM_PARAM_5__PRE 0x0 + +#define SCU_RAM_PARAM_4__A 0x831FF8 +#define SCU_RAM_PARAM_4__W 16 +#define SCU_RAM_PARAM_4__M 0xFFFF +#define SCU_RAM_PARAM_4__PRE 0x0 + +#define SCU_RAM_PARAM_3__A 0x831FF9 +#define SCU_RAM_PARAM_3__W 16 +#define SCU_RAM_PARAM_3__M 0xFFFF +#define SCU_RAM_PARAM_3__PRE 0x0 + +#define SCU_RAM_PARAM_2__A 0x831FFA +#define SCU_RAM_PARAM_2__W 16 +#define SCU_RAM_PARAM_2__M 0xFFFF +#define SCU_RAM_PARAM_2__PRE 0x0 + +#define SCU_RAM_PARAM_1__A 0x831FFB +#define SCU_RAM_PARAM_1__W 16 +#define SCU_RAM_PARAM_1__M 0xFFFF +#define SCU_RAM_PARAM_1__PRE 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000 +#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000 + + +#define SCU_RAM_PARAM_0__A 0x831FFC +#define SCU_RAM_PARAM_0__W 16 +#define SCU_RAM_PARAM_0__M 0xFFFF +#define SCU_RAM_PARAM_0__PRE 0x0 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109 +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA +#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2 +#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3 +#define SCU_RAM_PARAM_0_RESULT_OK 0x0 +#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF +#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE +#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD +#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC + + +#define SCU_RAM_COMMAND__A 0x831FFD +#define SCU_RAM_COMMAND__W 16 +#define SCU_RAM_COMMAND__M 0xFFFF +#define SCU_RAM_COMMAND__PRE 0x0 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 +#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 +#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 +#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6 +#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7 +#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8 +#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82 +#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83 +#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84 +#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80 +#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82 +#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83 +#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84 +#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85 +#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86 +#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87 +#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE +#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD +#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0 +#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1 + +#define SCU_RAM_COMMAND_STANDARD__B 8 +#define SCU_RAM_COMMAND_STANDARD__W 8 +#define SCU_RAM_COMMAND_STANDARD__M 0xFF00 +#define SCU_RAM_COMMAND_STANDARD__PRE 0x0 +#define SCU_RAM_COMMAND_STANDARD_ATV 0x100 +#define SCU_RAM_COMMAND_STANDARD_QAM 0x200 +#define SCU_RAM_COMMAND_STANDARD_VSB 0x300 +#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 +#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000 +#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00 + +#define SCU_RAM_VERSION_HI__A 0x831FFE +#define SCU_RAM_VERSION_HI__W 16 +#define SCU_RAM_VERSION_HI__M 0xFFFF +#define SCU_RAM_VERSION_HI__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0 +#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4 +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF +#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0 + +#define SCU_RAM_VERSION_LO__A 0x831FFF +#define SCU_RAM_VERSION_LO__W 16 +#define SCU_RAM_VERSION_LO__M 0xFFFF +#define SCU_RAM_VERSION_LO__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000 +#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00 +#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0 + +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4 +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF +#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0 + + + + + +#define SIO_COMM_EXEC__A 0x400000 +#define SIO_COMM_EXEC__W 2 +#define SIO_COMM_EXEC__M 0x3 +#define SIO_COMM_EXEC__PRE 0x0 +#define SIO_COMM_EXEC_STOP 0x0 +#define SIO_COMM_EXEC_ACTIVE 0x1 +#define SIO_COMM_EXEC_HOLD 0x2 + +#define SIO_COMM_STATE__A 0x400001 +#define SIO_COMM_STATE__W 16 +#define SIO_COMM_STATE__M 0xFFFF +#define SIO_COMM_STATE__PRE 0x0 +#define SIO_COMM_MB__A 0x400002 +#define SIO_COMM_MB__W 16 +#define SIO_COMM_MB__M 0xFFFF +#define SIO_COMM_MB__PRE 0x0 +#define SIO_COMM_INT_REQ__A 0x400003 +#define SIO_COMM_INT_REQ__W 16 +#define SIO_COMM_INT_REQ__M 0xFFFF +#define SIO_COMM_INT_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_HI_REQ__B 0 +#define SIO_COMM_INT_REQ_HI_REQ__W 1 +#define SIO_COMM_INT_REQ_HI_REQ__M 0x1 +#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_SA_REQ__B 1 +#define SIO_COMM_INT_REQ_SA_REQ__W 1 +#define SIO_COMM_INT_REQ_SA_REQ__M 0x2 +#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0 + +#define SIO_COMM_INT_REQ_BL_REQ__B 2 +#define SIO_COMM_INT_REQ_BL_REQ__W 1 +#define SIO_COMM_INT_REQ_BL_REQ__M 0x4 +#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0 + +#define SIO_COMM_INT_STA__A 0x400005 +#define SIO_COMM_INT_STA__W 16 +#define SIO_COMM_INT_STA__M 0xFFFF +#define SIO_COMM_INT_STA__PRE 0x0 +#define SIO_COMM_INT_MSK__A 0x400006 +#define SIO_COMM_INT_MSK__W 16 +#define SIO_COMM_INT_MSK__M 0xFFFF +#define SIO_COMM_INT_MSK__PRE 0x0 +#define SIO_COMM_INT_STM__A 0x400007 +#define SIO_COMM_INT_STM__W 16 +#define SIO_COMM_INT_STM__M 0xFFFF +#define SIO_COMM_INT_STM__PRE 0x0 + + + +#define SIO_TOP_COMM_EXEC__A 0x410000 +#define SIO_TOP_COMM_EXEC__W 2 +#define SIO_TOP_COMM_EXEC__M 0x3 +#define SIO_TOP_COMM_EXEC__PRE 0x0 +#define SIO_TOP_COMM_EXEC_STOP 0x0 +#define SIO_TOP_COMM_EXEC_ACTIVE 0x1 +#define SIO_TOP_COMM_EXEC_HOLD 0x2 + + +#define SIO_TOP_COMM_KEY__A 0x41000F +#define SIO_TOP_COMM_KEY__W 16 +#define SIO_TOP_COMM_KEY__M 0xFFFF +#define SIO_TOP_COMM_KEY__PRE 0x0 +#define SIO_TOP_COMM_KEY_KEY 0xFABA + + +#define SIO_TOP_JTAGID_LO__A 0x410012 +#define SIO_TOP_JTAGID_LO__W 16 +#define SIO_TOP_JTAGID_LO__M 0xFFFF +#define SIO_TOP_JTAGID_LO__PRE 0x0 + +#define SIO_TOP_JTAGID_HI__A 0x410013 +#define SIO_TOP_JTAGID_HI__W 16 +#define SIO_TOP_JTAGID_HI__M 0xFFFF +#define SIO_TOP_JTAGID_HI__PRE 0x0 + + + + +#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010 +#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011 +#define SIO_HI_RA_RAM_S0_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012 +#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013 +#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE__A 0x420014 +#define SIO_HI_RA_RAM_S0_STATE__W 1 +#define SIO_HI_RA_RAM_S0_STATE__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015 +#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016 +#define SIO_HI_RA_RAM_S0_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S0_CRC__A 0x420017 +#define SIO_HI_RA_RAM_S0_CRC__W 16 +#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018 +#define SIO_HI_RA_RAM_S0_BUFFER__W 16 +#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019 +#define SIO_HI_RA_RAM_S0_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A +#define SIO_HI_RA_RAM_S0_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B +#define SIO_HI_RA_RAM_S0_TEMP0__W 16 +#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C +#define SIO_HI_RA_RAM_S0_TEMP1__W 16 +#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D +#define SIO_HI_RA_RAM_S0_OFFSET__W 16 +#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020 +#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021 +#define SIO_HI_RA_RAM_S1_DEV_ID__W 7 +#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F +#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52 + +#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022 +#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0 +#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023 +#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4 +#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF +#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8 +#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE__A 0x420024 +#define SIO_HI_RA_RAM_S1_STATE__W 1 +#define SIO_HI_RA_RAM_S1_STATE__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1 +#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025 +#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12 +#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF +#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2 + +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80 + +#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026 +#define SIO_HI_RA_RAM_S1_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16 +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF +#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0 + + +#define SIO_HI_RA_RAM_S1_CRC__A 0x420027 +#define SIO_HI_RA_RAM_S1_CRC__W 16 +#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF +#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028 +#define SIO_HI_RA_RAM_S1_BUFFER__W 16 +#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF +#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029 +#define SIO_HI_RA_RAM_S1_RMWBUF__W 16 +#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF +#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A +#define SIO_HI_RA_RAM_S1_FLG_VB__W 1 +#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1 +#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B +#define SIO_HI_RA_RAM_S1_TEMP0__W 16 +#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C +#define SIO_HI_RA_RAM_S1_TEMP1__W 16 +#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF +#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0 + +#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D +#define SIO_HI_RA_RAM_S1_OFFSET__W 16 +#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF +#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA__A 0x420030 +#define SIO_HI_RA_RAM_SEMA__W 1 +#define SIO_HI_RA_RAM_SEMA__M 0x1 +#define SIO_HI_RA_RAM_SEMA__PRE 0x0 +#define SIO_HI_RA_RAM_SEMA_FREE 0x0 +#define SIO_HI_RA_RAM_SEMA_BUSY 0x1 + +#define SIO_HI_RA_RAM_RES__A 0x420031 +#define SIO_HI_RA_RAM_RES__W 3 +#define SIO_HI_RA_RAM_RES__M 0x7 +#define SIO_HI_RA_RAM_RES__PRE 0x0 +#define SIO_HI_RA_RAM_RES_OK 0x0 +#define SIO_HI_RA_RAM_RES_ERROR 0x1 +#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1 +#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2 +#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3 +#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4 + +#define SIO_HI_RA_RAM_CMD__A 0x420032 +#define SIO_HI_RA_RAM_CMD__W 4 +#define SIO_HI_RA_RAM_CMD__M 0xF +#define SIO_HI_RA_RAM_CMD__PRE 0x0 +#define SIO_HI_RA_RAM_CMD_NULL 0x0 +#define SIO_HI_RA_RAM_CMD_UIO 0x1 +#define SIO_HI_RA_RAM_CMD_RESET 0x2 +#define SIO_HI_RA_RAM_CMD_CONFIG 0x3 +#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4 +#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5 +#define SIO_HI_RA_RAM_CMD_EXEC 0x6 +#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 +#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8 + +#define SIO_HI_RA_RAM_PAR_1__A 0x420033 +#define SIO_HI_RA_RAM_PAR_1__W 16 +#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0 +#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16 +#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2 + +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10 +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF +#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2__A 0x420034 +#define SIO_HI_RA_RAM_PAR_2__W 16 +#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0 +#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16 +#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7 +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F +#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25 + +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16 +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 +#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 + +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3__A 0x420035 +#define SIO_HI_RA_RAM_PAR_3__W 16 +#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0 +#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16 +#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F + +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80 +#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80 + +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16 +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7 +#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 +#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 + +#define SIO_HI_RA_RAM_PAR_4__A 0x420036 +#define SIO_HI_RA_RAM_PAR_4__W 16 +#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0 +#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16 +#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8 +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF +#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0 +#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5__A 0x420037 +#define SIO_HI_RA_RAM_PAR_5__W 16 +#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0 +#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16 +#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2 + +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 + +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0 +#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20 + +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16 +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6__A 0x420038 +#define SIO_HI_RA_RAM_PAR_6__W 16 +#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF +#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0 +#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16 +#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF +#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0 + +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF +#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF + +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00 +#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500 + + +#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E +#define SIO_HI_RA_RAM_AB_TEMP__W 16 +#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF +#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0 + +#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F +#define SIO_HI_RA_RAM_I2C_CTL__W 16 +#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF +#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070 +#define SIO_HI_RA_RAM_VB_ENTRY0__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000 +#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071 +#define SIO_HI_RA_RAM_VB_OFFSET0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072 +#define SIO_HI_RA_RAM_VB_ENTRY1__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073 +#define SIO_HI_RA_RAM_VB_OFFSET1__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074 +#define SIO_HI_RA_RAM_VB_ENTRY2__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075 +#define SIO_HI_RA_RAM_VB_OFFSET2__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076 +#define SIO_HI_RA_RAM_VB_ENTRY3__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077 +#define SIO_HI_RA_RAM_VB_OFFSET3__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078 +#define SIO_HI_RA_RAM_VB_ENTRY4__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079 +#define SIO_HI_RA_RAM_VB_OFFSET4__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A +#define SIO_HI_RA_RAM_VB_ENTRY5__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B +#define SIO_HI_RA_RAM_VB_OFFSET5__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C +#define SIO_HI_RA_RAM_VB_ENTRY6__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D +#define SIO_HI_RA_RAM_VB_OFFSET6__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0 + + +#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E +#define SIO_HI_RA_RAM_VB_ENTRY7__W 16 +#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0 +#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F +#define SIO_HI_RA_RAM_VB_OFFSET7__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0 + +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16 +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF +#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0 + + + +#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000 +#define SIO_HI_IF_RAM_TRP_BPT_0__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001 +#define SIO_HI_IF_RAM_TRP_BPT_1__W 12 +#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002 +#define SIO_HI_IF_RAM_TRP_STK_0__W 12 +#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0 +#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003 +#define SIO_HI_IF_RAM_TRP_STK_1__W 12 +#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF +#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0 +#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300 +#define SIO_HI_IF_RAM_FUN_BASE__W 12 +#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF +#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0 + + + +#define SIO_HI_IF_COMM_EXEC__A 0x440000 +#define SIO_HI_IF_COMM_EXEC__W 2 +#define SIO_HI_IF_COMM_EXEC__M 0x3 +#define SIO_HI_IF_COMM_EXEC__PRE 0x0 +#define SIO_HI_IF_COMM_EXEC_STOP 0x0 +#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1 +#define SIO_HI_IF_COMM_EXEC_HOLD 0x2 +#define SIO_HI_IF_COMM_EXEC_STEP 0x3 + + +#define SIO_HI_IF_COMM_STATE__A 0x440001 +#define SIO_HI_IF_COMM_STATE__W 10 +#define SIO_HI_IF_COMM_STATE__M 0x3FF +#define SIO_HI_IF_COMM_STATE__PRE 0x0 +#define SIO_HI_IF_COMM_INT_REQ__A 0x440003 +#define SIO_HI_IF_COMM_INT_REQ__W 1 +#define SIO_HI_IF_COMM_INT_REQ__M 0x1 +#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA__A 0x440005 +#define SIO_HI_IF_COMM_INT_STA__W 1 +#define SIO_HI_IF_COMM_INT_STA__M 0x1 +#define SIO_HI_IF_COMM_INT_STA__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STA_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STA_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_MSK__A 0x440006 +#define SIO_HI_IF_COMM_INT_MSK__W 1 +#define SIO_HI_IF_COMM_INT_MSK__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0 +#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0 + +#define SIO_HI_IF_COMM_INT_STM__A 0x440007 +#define SIO_HI_IF_COMM_INT_STM__W 1 +#define SIO_HI_IF_COMM_INT_STM__M 0x1 +#define SIO_HI_IF_COMM_INT_STM__PRE 0x0 +#define SIO_HI_IF_COMM_INT_STM_STAT__B 0 +#define SIO_HI_IF_COMM_INT_STM_STAT__W 1 +#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1 +#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0 + +#define SIO_HI_IF_STK_0__A 0x440010 +#define SIO_HI_IF_STK_0__W 10 +#define SIO_HI_IF_STK_0__M 0x3FF +#define SIO_HI_IF_STK_0__PRE 0x2 + +#define SIO_HI_IF_STK_0_ADDR__B 0 +#define SIO_HI_IF_STK_0_ADDR__W 10 +#define SIO_HI_IF_STK_0_ADDR__M 0x3FF +#define SIO_HI_IF_STK_0_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_1__A 0x440011 +#define SIO_HI_IF_STK_1__W 10 +#define SIO_HI_IF_STK_1__M 0x3FF +#define SIO_HI_IF_STK_1__PRE 0x2 +#define SIO_HI_IF_STK_1_ADDR__B 0 +#define SIO_HI_IF_STK_1_ADDR__W 10 +#define SIO_HI_IF_STK_1_ADDR__M 0x3FF +#define SIO_HI_IF_STK_1_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_2__A 0x440012 +#define SIO_HI_IF_STK_2__W 10 +#define SIO_HI_IF_STK_2__M 0x3FF +#define SIO_HI_IF_STK_2__PRE 0x2 +#define SIO_HI_IF_STK_2_ADDR__B 0 +#define SIO_HI_IF_STK_2_ADDR__W 10 +#define SIO_HI_IF_STK_2_ADDR__M 0x3FF +#define SIO_HI_IF_STK_2_ADDR__PRE 0x2 + +#define SIO_HI_IF_STK_3__A 0x440013 +#define SIO_HI_IF_STK_3__W 10 +#define SIO_HI_IF_STK_3__M 0x3FF +#define SIO_HI_IF_STK_3__PRE 0x2 + +#define SIO_HI_IF_STK_3_ADDR__B 0 +#define SIO_HI_IF_STK_3_ADDR__W 10 +#define SIO_HI_IF_STK_3_ADDR__M 0x3FF +#define SIO_HI_IF_STK_3_ADDR__PRE 0x2 + +#define SIO_HI_IF_BPT_IDX__A 0x44001F +#define SIO_HI_IF_BPT_IDX__W 1 +#define SIO_HI_IF_BPT_IDX__M 0x1 +#define SIO_HI_IF_BPT_IDX__PRE 0x0 + +#define SIO_HI_IF_BPT_IDX_ADDR__B 0 +#define SIO_HI_IF_BPT_IDX_ADDR__W 1 +#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1 +#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0 + +#define SIO_HI_IF_BPT__A 0x440020 +#define SIO_HI_IF_BPT__W 10 +#define SIO_HI_IF_BPT__M 0x3FF +#define SIO_HI_IF_BPT__PRE 0x2 + +#define SIO_HI_IF_BPT_ADDR__B 0 +#define SIO_HI_IF_BPT_ADDR__W 10 +#define SIO_HI_IF_BPT_ADDR__M 0x3FF +#define SIO_HI_IF_BPT_ADDR__PRE 0x2 + + + +#define SIO_CC_COMM_EXEC__A 0x450000 +#define SIO_CC_COMM_EXEC__W 2 +#define SIO_CC_COMM_EXEC__M 0x3 +#define SIO_CC_COMM_EXEC__PRE 0x0 +#define SIO_CC_COMM_EXEC_STOP 0x0 +#define SIO_CC_COMM_EXEC_ACTIVE 0x1 +#define SIO_CC_COMM_EXEC_HOLD 0x2 + +#define SIO_CC_PLL_MODE__A 0x450010 +#define SIO_CC_PLL_MODE__W 6 +#define SIO_CC_PLL_MODE__M 0x3F +#define SIO_CC_PLL_MODE__PRE 0x0 + +#define SIO_CC_PLL_MODE_FREF_SEL__B 0 +#define SIO_CC_PLL_MODE_FREF_SEL__W 2 +#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3 +#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0 +#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1 +#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2 +#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3 + +#define SIO_CC_PLL_MODE_LOCKSEL__B 2 +#define SIO_CC_PLL_MODE_LOCKSEL__W 2 +#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC +#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0 + +#define SIO_CC_PLL_MODE_BYPASS__B 4 +#define SIO_CC_PLL_MODE_BYPASS__W 2 +#define SIO_CC_PLL_MODE_BYPASS__M 0x30 +#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0 +#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10 +#define SIO_CC_PLL_MODE_BYPASS_ON 0x20 + + +#define SIO_CC_PLL_TEST__A 0x450011 +#define SIO_CC_PLL_TEST__W 8 +#define SIO_CC_PLL_TEST__M 0xFF +#define SIO_CC_PLL_TEST__PRE 0x0 + +#define SIO_CC_PLL_LOCK__A 0x450012 +#define SIO_CC_PLL_LOCK__W 1 +#define SIO_CC_PLL_LOCK__M 0x1 +#define SIO_CC_PLL_LOCK__PRE 0x0 +#define SIO_CC_CLK_TEST__A 0x450013 +#define SIO_CC_CLK_TEST__W 8 +#define SIO_CC_CLK_TEST__M 0xFF +#define SIO_CC_CLK_TEST__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL1__B 0 +#define SIO_CC_CLK_TEST_SEL1__W 3 +#define SIO_CC_CLK_TEST_SEL1__M 0x7 +#define SIO_CC_CLK_TEST_SEL1__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB1__B 3 +#define SIO_CC_CLK_TEST_ENAB1__W 1 +#define SIO_CC_CLK_TEST_ENAB1__M 0x8 +#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0 + +#define SIO_CC_CLK_TEST_SEL2__B 4 +#define SIO_CC_CLK_TEST_SEL2__W 3 +#define SIO_CC_CLK_TEST_SEL2__M 0x70 +#define SIO_CC_CLK_TEST_SEL2__PRE 0x0 + +#define SIO_CC_CLK_TEST_ENAB2__B 7 +#define SIO_CC_CLK_TEST_ENAB2__W 1 +#define SIO_CC_CLK_TEST_ENAB2__M 0x80 +#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0 + +#define SIO_CC_CLK_MODE__A 0x450014 +#define SIO_CC_CLK_MODE__W 7 +#define SIO_CC_CLK_MODE__M 0x7F +#define SIO_CC_CLK_MODE__PRE 0x0 + +#define SIO_CC_CLK_MODE_DELAY__B 0 +#define SIO_CC_CLK_MODE_DELAY__W 4 +#define SIO_CC_CLK_MODE_DELAY__M 0xF +#define SIO_CC_CLK_MODE_DELAY__PRE 0x0 + +#define SIO_CC_CLK_MODE_INVERT__B 4 +#define SIO_CC_CLK_MODE_INVERT__W 1 +#define SIO_CC_CLK_MODE_INVERT__M 0x10 +#define SIO_CC_CLK_MODE_INVERT__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20 +#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0 + +#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40 +#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0 + +#define SIO_CC_PWD_MODE__A 0x450015 +#define SIO_CC_PWD_MODE__W 4 +#define SIO_CC_PWD_MODE__M 0xF +#define SIO_CC_PWD_MODE__PRE 0x0 + +#define SIO_CC_PWD_MODE_LEVEL__B 0 +#define SIO_CC_PWD_MODE_LEVEL__W 3 +#define SIO_CC_PWD_MODE_LEVEL__M 0x7 +#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 +#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 +#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 +#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 +#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 + +#define SIO_CC_PWD_MODE_USE_LOCK__B 3 +#define SIO_CC_PWD_MODE_USE_LOCK__W 1 +#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8 +#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0 + +#define SIO_CC_SOFT_RST__A 0x450016 +#define SIO_CC_SOFT_RST__W 3 +#define SIO_CC_SOFT_RST__M 0x7 +#define SIO_CC_SOFT_RST__PRE 0x0 + +#define SIO_CC_SOFT_RST_OFDM__B 0 +#define SIO_CC_SOFT_RST_OFDM__W 1 +#define SIO_CC_SOFT_RST_OFDM__M 0x1 +#define SIO_CC_SOFT_RST_OFDM__PRE 0x0 + +#define SIO_CC_SOFT_RST_SYS__B 1 +#define SIO_CC_SOFT_RST_SYS__W 1 +#define SIO_CC_SOFT_RST_SYS__M 0x2 +#define SIO_CC_SOFT_RST_SYS__PRE 0x0 + +#define SIO_CC_SOFT_RST_OSC__B 2 +#define SIO_CC_SOFT_RST_OSC__W 1 +#define SIO_CC_SOFT_RST_OSC__M 0x4 +#define SIO_CC_SOFT_RST_OSC__PRE 0x0 + + +#define SIO_CC_UPDATE__A 0x450017 +#define SIO_CC_UPDATE__W 16 +#define SIO_CC_UPDATE__M 0xFFFF +#define SIO_CC_UPDATE__PRE 0x0 +#define SIO_CC_UPDATE_KEY 0xFABA + + + +#define SIO_SA_COMM_EXEC__A 0x460000 +#define SIO_SA_COMM_EXEC__W 2 +#define SIO_SA_COMM_EXEC__M 0x3 +#define SIO_SA_COMM_EXEC__PRE 0x0 +#define SIO_SA_COMM_EXEC_STOP 0x0 +#define SIO_SA_COMM_EXEC_ACTIVE 0x1 +#define SIO_SA_COMM_EXEC_HOLD 0x2 + +#define SIO_SA_COMM_INT_REQ__A 0x460003 +#define SIO_SA_COMM_INT_REQ__W 1 +#define SIO_SA_COMM_INT_REQ__M 0x1 +#define SIO_SA_COMM_INT_REQ__PRE 0x0 +#define SIO_SA_COMM_INT_STA__A 0x460005 +#define SIO_SA_COMM_INT_STA__W 4 +#define SIO_SA_COMM_INT_STA__M 0xF +#define SIO_SA_COMM_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1 +#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2 +#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4 +#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0 + +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8 +#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK__A 0x460006 +#define SIO_SA_COMM_INT_MSK__W 4 +#define SIO_SA_COMM_INT_MSK__M 0xF +#define SIO_SA_COMM_INT_MSK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM__A 0x460007 +#define SIO_SA_COMM_INT_STM__W 4 +#define SIO_SA_COMM_INT_STM__M 0xF +#define SIO_SA_COMM_INT_STM__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1 +#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2 +#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4 +#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0 + +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8 +#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0 + +#define SIO_SA_PRESCALER__A 0x460010 +#define SIO_SA_PRESCALER__W 13 +#define SIO_SA_PRESCALER__M 0x1FFF +#define SIO_SA_PRESCALER__PRE 0x18B7 +#define SIO_SA_TX_DATA0__A 0x460011 +#define SIO_SA_TX_DATA0__W 16 +#define SIO_SA_TX_DATA0__M 0xFFFF +#define SIO_SA_TX_DATA0__PRE 0x0 +#define SIO_SA_TX_DATA1__A 0x460012 +#define SIO_SA_TX_DATA1__W 16 +#define SIO_SA_TX_DATA1__M 0xFFFF +#define SIO_SA_TX_DATA1__PRE 0x0 +#define SIO_SA_TX_DATA2__A 0x460013 +#define SIO_SA_TX_DATA2__W 16 +#define SIO_SA_TX_DATA2__M 0xFFFF +#define SIO_SA_TX_DATA2__PRE 0x0 +#define SIO_SA_TX_DATA3__A 0x460014 +#define SIO_SA_TX_DATA3__W 16 +#define SIO_SA_TX_DATA3__M 0xFFFF +#define SIO_SA_TX_DATA3__PRE 0x0 +#define SIO_SA_TX_LENGTH__A 0x460015 +#define SIO_SA_TX_LENGTH__W 6 +#define SIO_SA_TX_LENGTH__M 0x3F +#define SIO_SA_TX_LENGTH__PRE 0x0 +#define SIO_SA_TX_COMMAND__A 0x460016 +#define SIO_SA_TX_COMMAND__W 2 +#define SIO_SA_TX_COMMAND__M 0x3 +#define SIO_SA_TX_COMMAND__PRE 0x3 + +#define SIO_SA_TX_COMMAND_TX_INVERT__B 0 +#define SIO_SA_TX_COMMAND_TX_INVERT__W 1 +#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1 +#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1 + +#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1 +#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2 +#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2 + +#define SIO_SA_TX_STATUS__A 0x460017 +#define SIO_SA_TX_STATUS__W 2 +#define SIO_SA_TX_STATUS__M 0x3 +#define SIO_SA_TX_STATUS__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUSY__B 0 +#define SIO_SA_TX_STATUS_BUSY__W 1 +#define SIO_SA_TX_STATUS_BUSY__M 0x1 +#define SIO_SA_TX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_TX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0 + +#define SIO_SA_RX_DATA0__A 0x460018 +#define SIO_SA_RX_DATA0__W 16 +#define SIO_SA_RX_DATA0__M 0xFFFF +#define SIO_SA_RX_DATA0__PRE 0x0 +#define SIO_SA_RX_DATA1__A 0x460019 +#define SIO_SA_RX_DATA1__W 16 +#define SIO_SA_RX_DATA1__M 0xFFFF +#define SIO_SA_RX_DATA1__PRE 0x0 +#define SIO_SA_RX_LENGTH__A 0x46001A +#define SIO_SA_RX_LENGTH__W 6 +#define SIO_SA_RX_LENGTH__M 0x3F +#define SIO_SA_RX_LENGTH__PRE 0x0 +#define SIO_SA_RX_COMMAND__A 0x46001B +#define SIO_SA_RX_COMMAND__W 1 +#define SIO_SA_RX_COMMAND__M 0x1 +#define SIO_SA_RX_COMMAND__PRE 0x1 + +#define SIO_SA_RX_COMMAND_RX_INVERT__B 0 +#define SIO_SA_RX_COMMAND_RX_INVERT__W 1 +#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1 +#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1 + +#define SIO_SA_RX_STATUS__A 0x46001C +#define SIO_SA_RX_STATUS__W 2 +#define SIO_SA_RX_STATUS__M 0x3 +#define SIO_SA_RX_STATUS__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUSY__B 0 +#define SIO_SA_RX_STATUS_BUSY__W 1 +#define SIO_SA_RX_STATUS_BUSY__M 0x1 +#define SIO_SA_RX_STATUS_BUSY__PRE 0x0 + +#define SIO_SA_RX_STATUS_BUFF_FULL__B 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__W 1 +#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2 +#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0 + + + +#define SIO_OFDM_SH_COMM_EXEC__A 0x470000 +#define SIO_OFDM_SH_COMM_EXEC__W 2 +#define SIO_OFDM_SH_COMM_EXEC__M 0x3 +#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0 +#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0 +#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1 +#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2 + +#define SIO_OFDM_SH_COMM_MB__A 0x470002 +#define SIO_OFDM_SH_COMM_MB__W 2 +#define SIO_OFDM_SH_COMM_MB__M 0x3 +#define SIO_OFDM_SH_COMM_MB__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL__B 0 +#define SIO_OFDM_SH_COMM_MB_CTL__W 1 +#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1 +#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1 +#define SIO_OFDM_SH_COMM_MB_OBS__B 1 +#define SIO_OFDM_SH_COMM_MB_OBS__W 1 +#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2 +#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0 +#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2 + +#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 +#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3 +#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1 + +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0 +#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2 + +#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 +#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1 +#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 +#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 + +#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013 +#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7 +#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6 + + + +#define SIO_BL_COMM_EXEC__A 0x480000 +#define SIO_BL_COMM_EXEC__W 2 +#define SIO_BL_COMM_EXEC__M 0x3 +#define SIO_BL_COMM_EXEC__PRE 0x0 +#define SIO_BL_COMM_EXEC_STOP 0x0 +#define SIO_BL_COMM_EXEC_ACTIVE 0x1 +#define SIO_BL_COMM_EXEC_HOLD 0x2 + +#define SIO_BL_COMM_INT_REQ__A 0x480003 +#define SIO_BL_COMM_INT_REQ__W 1 +#define SIO_BL_COMM_INT_REQ__M 0x1 +#define SIO_BL_COMM_INT_REQ__PRE 0x0 +#define SIO_BL_COMM_INT_STA__A 0x480005 +#define SIO_BL_COMM_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1 +#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK__A 0x480006 +#define SIO_BL_COMM_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_COMM_INT_STM__A 0x480007 +#define SIO_BL_COMM_INT_STM__W 1 +#define SIO_BL_COMM_INT_STM__M 0x1 +#define SIO_BL_COMM_INT_STM__PRE 0x0 + +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1 +#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0 + +#define SIO_BL_STATUS__A 0x480010 +#define SIO_BL_STATUS__W 1 +#define SIO_BL_STATUS__M 0x1 +#define SIO_BL_STATUS__PRE 0x0 +#define SIO_BL_MODE__A 0x480011 +#define SIO_BL_MODE__W 1 +#define SIO_BL_MODE__M 0x1 +#define SIO_BL_MODE__PRE 0x1 +#define SIO_BL_MODE_DIRECT 0x0 +#define SIO_BL_MODE_CHAIN 0x1 + +#define SIO_BL_ENABLE__A 0x480012 +#define SIO_BL_ENABLE__W 1 +#define SIO_BL_ENABLE__M 0x1 +#define SIO_BL_ENABLE__PRE 0x0 +#define SIO_BL_ENABLE_OFF 0x0 +#define SIO_BL_ENABLE_ON 0x1 + +#define SIO_BL_TGT_HDR__A 0x480014 +#define SIO_BL_TGT_HDR__W 12 +#define SIO_BL_TGT_HDR__M 0xFFF +#define SIO_BL_TGT_HDR__PRE 0x0 +#define SIO_BL_TGT_HDR_BANK__B 0 +#define SIO_BL_TGT_HDR_BANK__W 6 +#define SIO_BL_TGT_HDR_BANK__M 0x3F +#define SIO_BL_TGT_HDR_BANK__PRE 0x0 +#define SIO_BL_TGT_HDR_BLOCK__B 6 +#define SIO_BL_TGT_HDR_BLOCK__W 6 +#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0 +#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0 + +#define SIO_BL_TGT_ADDR__A 0x480015 +#define SIO_BL_TGT_ADDR__W 16 +#define SIO_BL_TGT_ADDR__M 0xFFFF +#define SIO_BL_TGT_ADDR__PRE 0x0 +#define SIO_BL_SRC_ADDR__A 0x480016 +#define SIO_BL_SRC_ADDR__W 16 +#define SIO_BL_SRC_ADDR__M 0xFFFF +#define SIO_BL_SRC_ADDR__PRE 0x0 +#define SIO_BL_SRC_LEN__A 0x480017 +#define SIO_BL_SRC_LEN__W 16 +#define SIO_BL_SRC_LEN__M 0xFFFF +#define SIO_BL_SRC_LEN__PRE 0x0 + +#define SIO_BL_CHAIN_ADDR__A 0x480018 +#define SIO_BL_CHAIN_ADDR__W 16 +#define SIO_BL_CHAIN_ADDR__M 0xFFFF +#define SIO_BL_CHAIN_ADDR__PRE 0x0 + +#define SIO_BL_CHAIN_LEN__A 0x480019 +#define SIO_BL_CHAIN_LEN__W 4 +#define SIO_BL_CHAIN_LEN__M 0xF +#define SIO_BL_CHAIN_LEN__PRE 0x2 + + + +#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000 + + + +#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000 + + + +#define SIO_BL_ROM__A 0x4E0000 + + + +#define SIO_PDR_COMM_EXEC__A 0x7F0000 +#define SIO_PDR_COMM_EXEC__W 2 +#define SIO_PDR_COMM_EXEC__M 0x3 +#define SIO_PDR_COMM_EXEC__PRE 0x0 +#define SIO_PDR_COMM_EXEC_STOP 0x0 +#define SIO_PDR_COMM_EXEC_ACTIVE 0x1 +#define SIO_PDR_COMM_EXEC_HOLD 0x2 + +#define SIO_PDR_MON_CFG__A 0x7F0010 +#define SIO_PDR_MON_CFG__W 4 +#define SIO_PDR_MON_CFG__M 0xF +#define SIO_PDR_MON_CFG__PRE 0x0 + +#define SIO_PDR_MON_CFG_OSEL__B 0 +#define SIO_PDR_MON_CFG_OSEL__W 1 +#define SIO_PDR_MON_CFG_OSEL__M 0x1 +#define SIO_PDR_MON_CFG_OSEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_IACT__B 1 +#define SIO_PDR_MON_CFG_IACT__W 1 +#define SIO_PDR_MON_CFG_IACT__M 0x2 +#define SIO_PDR_MON_CFG_IACT__PRE 0x0 + +#define SIO_PDR_MON_CFG_ISEL__B 2 +#define SIO_PDR_MON_CFG_ISEL__W 1 +#define SIO_PDR_MON_CFG_ISEL__M 0x4 +#define SIO_PDR_MON_CFG_ISEL__PRE 0x0 + +#define SIO_PDR_MON_CFG_INV_CLK__B 3 +#define SIO_PDR_MON_CFG_INV_CLK__W 1 +#define SIO_PDR_MON_CFG_INV_CLK__M 0x8 +#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL__A 0x7F0012 +#define SIO_PDR_SMA_RX_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_SEL_SEL__B 0 +#define SIO_PDR_SMA_RX_SEL_SEL__W 4 +#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF +#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0 + +#define SIO_PDR_SILENT__A 0x7F0013 +#define SIO_PDR_SILENT__W 13 +#define SIO_PDR_SILENT__M 0x1FFF +#define SIO_PDR_SILENT__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_WS__B 0 +#define SIO_PDR_SILENT_I2S_WS__W 1 +#define SIO_PDR_SILENT_I2S_WS__M 0x1 +#define SIO_PDR_SILENT_I2S_WS__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_DA__B 1 +#define SIO_PDR_SILENT_I2S_DA__W 1 +#define SIO_PDR_SILENT_I2S_DA__M 0x2 +#define SIO_PDR_SILENT_I2S_DA__PRE 0x0 + +#define SIO_PDR_SILENT_I2S_CL__B 2 +#define SIO_PDR_SILENT_I2S_CL__W 1 +#define SIO_PDR_SILENT_I2S_CL__M 0x4 +#define SIO_PDR_SILENT_I2S_CL__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SCL2__B 3 +#define SIO_PDR_SILENT_I2C_SCL2__W 1 +#define SIO_PDR_SILENT_I2C_SCL2__M 0x8 +#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0 + +#define SIO_PDR_SILENT_I2C_SDA2__B 4 +#define SIO_PDR_SILENT_I2C_SDA2__W 1 +#define SIO_PDR_SILENT_I2C_SDA2__M 0x10 +#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_TX__B 8 +#define SIO_PDR_SILENT_SMA_TX__W 1 +#define SIO_PDR_SILENT_SMA_TX__M 0x100 +#define SIO_PDR_SILENT_SMA_TX__PRE 0x0 + +#define SIO_PDR_SILENT_SMA_RX__B 9 +#define SIO_PDR_SILENT_SMA_RX__W 1 +#define SIO_PDR_SILENT_SMA_RX__M 0x200 +#define SIO_PDR_SILENT_SMA_RX__PRE 0x0 + +#define SIO_PDR_SILENT_GPIO__B 10 +#define SIO_PDR_SILENT_GPIO__W 1 +#define SIO_PDR_SILENT_GPIO__M 0x400 +#define SIO_PDR_SILENT_GPIO__PRE 0x0 + +#define SIO_PDR_SILENT_VSYNC__B 11 +#define SIO_PDR_SILENT_VSYNC__W 1 +#define SIO_PDR_SILENT_VSYNC__M 0x800 +#define SIO_PDR_SILENT_VSYNC__PRE 0x0 + +#define SIO_PDR_SILENT_IRQN__B 12 +#define SIO_PDR_SILENT_IRQN__W 1 +#define SIO_PDR_SILENT_IRQN__M 0x1000 +#define SIO_PDR_SILENT_IRQN__PRE 0x0 + +#define SIO_PDR_UIO_IN_LO__A 0x7F0014 +#define SIO_PDR_UIO_IN_LO__W 16 +#define SIO_PDR_UIO_IN_LO__M 0xFFFF +#define SIO_PDR_UIO_IN_LO__PRE 0x0 +#define SIO_PDR_UIO_IN_LO_DATA__B 0 +#define SIO_PDR_UIO_IN_LO_DATA__W 16 +#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_IN_HI__A 0x7F0015 +#define SIO_PDR_UIO_IN_HI__W 14 +#define SIO_PDR_UIO_IN_HI__M 0x3FFF +#define SIO_PDR_UIO_IN_HI__PRE 0x0 +#define SIO_PDR_UIO_IN_HI_DATA__B 0 +#define SIO_PDR_UIO_IN_HI_DATA__W 14 +#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_LO__A 0x7F0016 +#define SIO_PDR_UIO_OUT_LO__W 16 +#define SIO_PDR_UIO_OUT_LO__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO__PRE 0x0 +#define SIO_PDR_UIO_OUT_LO_DATA__B 0 +#define SIO_PDR_UIO_OUT_LO_DATA__W 16 +#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF +#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0 + +#define SIO_PDR_UIO_OUT_HI__A 0x7F0017 +#define SIO_PDR_UIO_OUT_HI__W 14 +#define SIO_PDR_UIO_OUT_HI__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI__PRE 0x0 +#define SIO_PDR_UIO_OUT_HI_DATA__B 0 +#define SIO_PDR_UIO_OUT_HI_DATA__W 14 +#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF +#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0 + +#define SIO_PDR_PWM1_MODE__A 0x7F0018 +#define SIO_PDR_PWM1_MODE__W 2 +#define SIO_PDR_PWM1_MODE__M 0x3 +#define SIO_PDR_PWM1_MODE__PRE 0x0 +#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019 +#define SIO_PDR_PWM1_PRESCALE__W 6 +#define SIO_PDR_PWM1_PRESCALE__M 0x3F +#define SIO_PDR_PWM1_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM1_VALUE__A 0x7F001A +#define SIO_PDR_PWM1_VALUE__W 11 +#define SIO_PDR_PWM1_VALUE__M 0x7FF +#define SIO_PDR_PWM1_VALUE__PRE 0x0 + +#define SIO_PDR_IRQN_SEL__A 0x7F001B +#define SIO_PDR_IRQN_SEL__W 4 +#define SIO_PDR_IRQN_SEL__M 0xF +#define SIO_PDR_IRQN_SEL__PRE 0x3 +#define SIO_PDR_PWM2_MODE__A 0x7F001C +#define SIO_PDR_PWM2_MODE__W 2 +#define SIO_PDR_PWM2_MODE__M 0x3 +#define SIO_PDR_PWM2_MODE__PRE 0x0 +#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D +#define SIO_PDR_PWM2_PRESCALE__W 6 +#define SIO_PDR_PWM2_PRESCALE__M 0x3F +#define SIO_PDR_PWM2_PRESCALE__PRE 0x0 +#define SIO_PDR_PWM2_VALUE__A 0x7F001E +#define SIO_PDR_PWM2_VALUE__W 11 +#define SIO_PDR_PWM2_VALUE__M 0x7FF +#define SIO_PDR_PWM2_VALUE__PRE 0x0 +#define SIO_PDR_OHW_CFG__A 0x7F001F +#define SIO_PDR_OHW_CFG__W 7 +#define SIO_PDR_OHW_CFG__M 0x7F +#define SIO_PDR_OHW_CFG__PRE 0x0 + +#define SIO_PDR_OHW_CFG_FREF_SEL__B 0 +#define SIO_PDR_OHW_CFG_FREF_SEL__W 2 +#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 +#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_BYPASS__B 2 +#define SIO_PDR_OHW_CFG_BYPASS__W 1 +#define SIO_PDR_OHW_CFG_BYPASS__M 0x4 +#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0 + +#define SIO_PDR_OHW_CFG_ASEL__B 3 +#define SIO_PDR_OHW_CFG_ASEL__W 3 +#define SIO_PDR_OHW_CFG_ASEL__M 0x38 +#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0 + +#define SIO_PDR_OHW_CFG_SPEED__B 6 +#define SIO_PDR_OHW_CFG_SPEED__W 1 +#define SIO_PDR_OHW_CFG_SPEED__M 0x40 +#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0 + +#define SIO_PDR_I2S_WS_CFG__A 0x7F0020 +#define SIO_PDR_I2S_WS_CFG__W 9 +#define SIO_PDR_I2S_WS_CFG__M 0x1FF +#define SIO_PDR_I2S_WS_CFG__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_MODE__B 0 +#define SIO_PDR_I2S_WS_CFG_MODE__W 3 +#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_WS_CFG_KEEP__B 6 +#define SIO_PDR_I2S_WS_CFG_KEEP__W 2 +#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_WS_CFG_UIO__B 8 +#define SIO_PDR_I2S_WS_CFG_UIO__W 1 +#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_CFG__A 0x7F0021 +#define SIO_PDR_GPIO_CFG__W 9 +#define SIO_PDR_GPIO_CFG__M 0x1FF +#define SIO_PDR_GPIO_CFG__PRE 0x10 +#define SIO_PDR_GPIO_CFG_MODE__B 0 +#define SIO_PDR_GPIO_CFG_MODE__W 3 +#define SIO_PDR_GPIO_CFG_MODE__M 0x7 +#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0 +#define SIO_PDR_GPIO_CFG_DRIVE__B 3 +#define SIO_PDR_GPIO_CFG_DRIVE__W 3 +#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38 +#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_GPIO_CFG_KEEP__B 6 +#define SIO_PDR_GPIO_CFG_KEEP__W 2 +#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0 +#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0 +#define SIO_PDR_GPIO_CFG_UIO__B 8 +#define SIO_PDR_GPIO_CFG_UIO__W 1 +#define SIO_PDR_GPIO_CFG_UIO__M 0x100 +#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MSTRT_CFG__A 0x7F0025 +#define SIO_PDR_MSTRT_CFG__W 9 +#define SIO_PDR_MSTRT_CFG__M 0x1FF +#define SIO_PDR_MSTRT_CFG__PRE 0x50 +#define SIO_PDR_MSTRT_CFG_MODE__B 0 +#define SIO_PDR_MSTRT_CFG_MODE__W 3 +#define SIO_PDR_MSTRT_CFG_MODE__M 0x7 +#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0 +#define SIO_PDR_MSTRT_CFG_DRIVE__B 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__W 3 +#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38 +#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MSTRT_CFG_KEEP__B 6 +#define SIO_PDR_MSTRT_CFG_KEEP__W 2 +#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0 +#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MSTRT_CFG_UIO__B 8 +#define SIO_PDR_MSTRT_CFG_UIO__W 1 +#define SIO_PDR_MSTRT_CFG_UIO__M 0x100 +#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MERR_CFG__A 0x7F0026 +#define SIO_PDR_MERR_CFG__W 9 +#define SIO_PDR_MERR_CFG__M 0x1FF +#define SIO_PDR_MERR_CFG__PRE 0x50 +#define SIO_PDR_MERR_CFG_MODE__B 0 +#define SIO_PDR_MERR_CFG_MODE__W 3 +#define SIO_PDR_MERR_CFG_MODE__M 0x7 +#define SIO_PDR_MERR_CFG_MODE__PRE 0x0 +#define SIO_PDR_MERR_CFG_DRIVE__B 3 +#define SIO_PDR_MERR_CFG_DRIVE__W 3 +#define SIO_PDR_MERR_CFG_DRIVE__M 0x38 +#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MERR_CFG_KEEP__B 6 +#define SIO_PDR_MERR_CFG_KEEP__W 2 +#define SIO_PDR_MERR_CFG_KEEP__M 0xC0 +#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MERR_CFG_UIO__B 8 +#define SIO_PDR_MERR_CFG_UIO__W 1 +#define SIO_PDR_MERR_CFG_UIO__M 0x100 +#define SIO_PDR_MERR_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MCLK_CFG__A 0x7F0028 +#define SIO_PDR_MCLK_CFG__W 9 +#define SIO_PDR_MCLK_CFG__M 0x1FF +#define SIO_PDR_MCLK_CFG__PRE 0x50 +#define SIO_PDR_MCLK_CFG_MODE__B 0 +#define SIO_PDR_MCLK_CFG_MODE__W 3 +#define SIO_PDR_MCLK_CFG_MODE__M 0x7 +#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0 +#define SIO_PDR_MCLK_CFG_DRIVE__B 3 +#define SIO_PDR_MCLK_CFG_DRIVE__W 3 +#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38 +#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MCLK_CFG_KEEP__B 6 +#define SIO_PDR_MCLK_CFG_KEEP__W 2 +#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0 +#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MCLK_CFG_UIO__B 8 +#define SIO_PDR_MCLK_CFG_UIO__W 1 +#define SIO_PDR_MCLK_CFG_UIO__M 0x100 +#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MVAL_CFG__A 0x7F0029 +#define SIO_PDR_MVAL_CFG__W 9 +#define SIO_PDR_MVAL_CFG__M 0x1FF +#define SIO_PDR_MVAL_CFG__PRE 0x50 +#define SIO_PDR_MVAL_CFG_MODE__B 0 +#define SIO_PDR_MVAL_CFG_MODE__W 3 +#define SIO_PDR_MVAL_CFG_MODE__M 0x7 +#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0 +#define SIO_PDR_MVAL_CFG_DRIVE__B 3 +#define SIO_PDR_MVAL_CFG_DRIVE__W 3 +#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38 +#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MVAL_CFG_KEEP__B 6 +#define SIO_PDR_MVAL_CFG_KEEP__W 2 +#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0 +#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MVAL_CFG_UIO__B 8 +#define SIO_PDR_MVAL_CFG_UIO__W 1 +#define SIO_PDR_MVAL_CFG_UIO__M 0x100 +#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD0_CFG__A 0x7F002A +#define SIO_PDR_MD0_CFG__W 9 +#define SIO_PDR_MD0_CFG__M 0x1FF +#define SIO_PDR_MD0_CFG__PRE 0x50 +#define SIO_PDR_MD0_CFG_MODE__B 0 +#define SIO_PDR_MD0_CFG_MODE__W 3 +#define SIO_PDR_MD0_CFG_MODE__M 0x7 +#define SIO_PDR_MD0_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD0_CFG_DRIVE__B 3 +#define SIO_PDR_MD0_CFG_DRIVE__W 3 +#define SIO_PDR_MD0_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD0_CFG_KEEP__B 6 +#define SIO_PDR_MD0_CFG_KEEP__W 2 +#define SIO_PDR_MD0_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD0_CFG_UIO__B 8 +#define SIO_PDR_MD0_CFG_UIO__W 1 +#define SIO_PDR_MD0_CFG_UIO__M 0x100 +#define SIO_PDR_MD0_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD1_CFG__A 0x7F002B +#define SIO_PDR_MD1_CFG__W 9 +#define SIO_PDR_MD1_CFG__M 0x1FF +#define SIO_PDR_MD1_CFG__PRE 0x50 +#define SIO_PDR_MD1_CFG_MODE__B 0 +#define SIO_PDR_MD1_CFG_MODE__W 3 +#define SIO_PDR_MD1_CFG_MODE__M 0x7 +#define SIO_PDR_MD1_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD1_CFG_DRIVE__B 3 +#define SIO_PDR_MD1_CFG_DRIVE__W 3 +#define SIO_PDR_MD1_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD1_CFG_KEEP__B 6 +#define SIO_PDR_MD1_CFG_KEEP__W 2 +#define SIO_PDR_MD1_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD1_CFG_UIO__B 8 +#define SIO_PDR_MD1_CFG_UIO__W 1 +#define SIO_PDR_MD1_CFG_UIO__M 0x100 +#define SIO_PDR_MD1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD2_CFG__A 0x7F002C +#define SIO_PDR_MD2_CFG__W 9 +#define SIO_PDR_MD2_CFG__M 0x1FF +#define SIO_PDR_MD2_CFG__PRE 0x50 +#define SIO_PDR_MD2_CFG_MODE__B 0 +#define SIO_PDR_MD2_CFG_MODE__W 3 +#define SIO_PDR_MD2_CFG_MODE__M 0x7 +#define SIO_PDR_MD2_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD2_CFG_DRIVE__B 3 +#define SIO_PDR_MD2_CFG_DRIVE__W 3 +#define SIO_PDR_MD2_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD2_CFG_KEEP__B 6 +#define SIO_PDR_MD2_CFG_KEEP__W 2 +#define SIO_PDR_MD2_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD2_CFG_UIO__B 8 +#define SIO_PDR_MD2_CFG_UIO__W 1 +#define SIO_PDR_MD2_CFG_UIO__M 0x100 +#define SIO_PDR_MD2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD3_CFG__A 0x7F002D +#define SIO_PDR_MD3_CFG__W 9 +#define SIO_PDR_MD3_CFG__M 0x1FF +#define SIO_PDR_MD3_CFG__PRE 0x50 +#define SIO_PDR_MD3_CFG_MODE__B 0 +#define SIO_PDR_MD3_CFG_MODE__W 3 +#define SIO_PDR_MD3_CFG_MODE__M 0x7 +#define SIO_PDR_MD3_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD3_CFG_DRIVE__B 3 +#define SIO_PDR_MD3_CFG_DRIVE__W 3 +#define SIO_PDR_MD3_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD3_CFG_KEEP__B 6 +#define SIO_PDR_MD3_CFG_KEEP__W 2 +#define SIO_PDR_MD3_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD3_CFG_UIO__B 8 +#define SIO_PDR_MD3_CFG_UIO__W 1 +#define SIO_PDR_MD3_CFG_UIO__M 0x100 +#define SIO_PDR_MD3_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD4_CFG__A 0x7F002F +#define SIO_PDR_MD4_CFG__W 9 +#define SIO_PDR_MD4_CFG__M 0x1FF +#define SIO_PDR_MD4_CFG__PRE 0x50 +#define SIO_PDR_MD4_CFG_MODE__B 0 +#define SIO_PDR_MD4_CFG_MODE__W 3 +#define SIO_PDR_MD4_CFG_MODE__M 0x7 +#define SIO_PDR_MD4_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD4_CFG_DRIVE__B 3 +#define SIO_PDR_MD4_CFG_DRIVE__W 3 +#define SIO_PDR_MD4_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD4_CFG_KEEP__B 6 +#define SIO_PDR_MD4_CFG_KEEP__W 2 +#define SIO_PDR_MD4_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD4_CFG_UIO__B 8 +#define SIO_PDR_MD4_CFG_UIO__W 1 +#define SIO_PDR_MD4_CFG_UIO__M 0x100 +#define SIO_PDR_MD4_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD5_CFG__A 0x7F0030 +#define SIO_PDR_MD5_CFG__W 9 +#define SIO_PDR_MD5_CFG__M 0x1FF +#define SIO_PDR_MD5_CFG__PRE 0x50 +#define SIO_PDR_MD5_CFG_MODE__B 0 +#define SIO_PDR_MD5_CFG_MODE__W 3 +#define SIO_PDR_MD5_CFG_MODE__M 0x7 +#define SIO_PDR_MD5_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD5_CFG_DRIVE__B 3 +#define SIO_PDR_MD5_CFG_DRIVE__W 3 +#define SIO_PDR_MD5_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD5_CFG_KEEP__B 6 +#define SIO_PDR_MD5_CFG_KEEP__W 2 +#define SIO_PDR_MD5_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD5_CFG_UIO__B 8 +#define SIO_PDR_MD5_CFG_UIO__W 1 +#define SIO_PDR_MD5_CFG_UIO__M 0x100 +#define SIO_PDR_MD5_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD6_CFG__A 0x7F0031 +#define SIO_PDR_MD6_CFG__W 9 +#define SIO_PDR_MD6_CFG__M 0x1FF +#define SIO_PDR_MD6_CFG__PRE 0x50 +#define SIO_PDR_MD6_CFG_MODE__B 0 +#define SIO_PDR_MD6_CFG_MODE__W 3 +#define SIO_PDR_MD6_CFG_MODE__M 0x7 +#define SIO_PDR_MD6_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD6_CFG_DRIVE__B 3 +#define SIO_PDR_MD6_CFG_DRIVE__W 3 +#define SIO_PDR_MD6_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD6_CFG_KEEP__B 6 +#define SIO_PDR_MD6_CFG_KEEP__W 2 +#define SIO_PDR_MD6_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD6_CFG_UIO__B 8 +#define SIO_PDR_MD6_CFG_UIO__W 1 +#define SIO_PDR_MD6_CFG_UIO__M 0x100 +#define SIO_PDR_MD6_CFG_UIO__PRE 0x0 + +#define SIO_PDR_MD7_CFG__A 0x7F0032 +#define SIO_PDR_MD7_CFG__W 9 +#define SIO_PDR_MD7_CFG__M 0x1FF +#define SIO_PDR_MD7_CFG__PRE 0x50 +#define SIO_PDR_MD7_CFG_MODE__B 0 +#define SIO_PDR_MD7_CFG_MODE__W 3 +#define SIO_PDR_MD7_CFG_MODE__M 0x7 +#define SIO_PDR_MD7_CFG_MODE__PRE 0x0 +#define SIO_PDR_MD7_CFG_DRIVE__B 3 +#define SIO_PDR_MD7_CFG_DRIVE__W 3 +#define SIO_PDR_MD7_CFG_DRIVE__M 0x38 +#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_MD7_CFG_KEEP__B 6 +#define SIO_PDR_MD7_CFG_KEEP__W 2 +#define SIO_PDR_MD7_CFG_KEEP__M 0xC0 +#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40 +#define SIO_PDR_MD7_CFG_UIO__B 8 +#define SIO_PDR_MD7_CFG_UIO__W 1 +#define SIO_PDR_MD7_CFG_UIO__M 0x100 +#define SIO_PDR_MD7_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033 +#define SIO_PDR_I2C_SCL1_CFG__W 9 +#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034 +#define SIO_PDR_I2C_SDA1_CFG__W 9 +#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0 + +#define SIO_PDR_VSYNC_CFG__A 0x7F0036 +#define SIO_PDR_VSYNC_CFG__W 9 +#define SIO_PDR_VSYNC_CFG__M 0x1FF +#define SIO_PDR_VSYNC_CFG__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_MODE__B 0 +#define SIO_PDR_VSYNC_CFG_MODE__W 3 +#define SIO_PDR_VSYNC_CFG_MODE__M 0x7 +#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_DRIVE__B 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__W 3 +#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38 +#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_VSYNC_CFG_KEEP__B 6 +#define SIO_PDR_VSYNC_CFG_KEEP__W 2 +#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0 +#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0 +#define SIO_PDR_VSYNC_CFG_UIO__B 8 +#define SIO_PDR_VSYNC_CFG_UIO__W 1 +#define SIO_PDR_VSYNC_CFG_UIO__M 0x100 +#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_RX_CFG__A 0x7F0037 +#define SIO_PDR_SMA_RX_CFG__W 9 +#define SIO_PDR_SMA_RX_CFG__M 0x1FF +#define SIO_PDR_SMA_RX_CFG__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_MODE__B 0 +#define SIO_PDR_SMA_RX_CFG_MODE__W 3 +#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_RX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_RX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0 +#define SIO_PDR_SMA_RX_CFG_UIO__B 8 +#define SIO_PDR_SMA_RX_CFG_UIO__W 1 +#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_SMA_TX_CFG__A 0x7F0038 +#define SIO_PDR_SMA_TX_CFG__W 9 +#define SIO_PDR_SMA_TX_CFG__M 0x1FF +#define SIO_PDR_SMA_TX_CFG__PRE 0x90 +#define SIO_PDR_SMA_TX_CFG_MODE__B 0 +#define SIO_PDR_SMA_TX_CFG_MODE__W 3 +#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7 +#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0 +#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3 +#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38 +#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_SMA_TX_CFG_KEEP__B 6 +#define SIO_PDR_SMA_TX_CFG_KEEP__W 2 +#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0 +#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80 +#define SIO_PDR_SMA_TX_CFG_UIO__B 8 +#define SIO_PDR_SMA_TX_CFG_UIO__W 1 +#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100 +#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F +#define SIO_PDR_I2C_SDA2_CFG__W 9 +#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF +#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040 +#define SIO_PDR_I2C_SCL2_CFG__W 9 +#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF +#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11 +#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0 +#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7 +#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8 +#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1 +#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100 +#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_CL_CFG__A 0x7F0041 +#define SIO_PDR_I2S_CL_CFG__W 9 +#define SIO_PDR_I2S_CL_CFG__M 0x1FF +#define SIO_PDR_I2S_CL_CFG__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_MODE__B 0 +#define SIO_PDR_I2S_CL_CFG_MODE__W 3 +#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_CL_CFG_KEEP__B 6 +#define SIO_PDR_I2S_CL_CFG_KEEP__W 2 +#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_CL_CFG_UIO__B 8 +#define SIO_PDR_I2S_CL_CFG_UIO__W 1 +#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0 + +#define SIO_PDR_I2S_DA_CFG__A 0x7F0042 +#define SIO_PDR_I2S_DA_CFG__W 9 +#define SIO_PDR_I2S_DA_CFG__M 0x1FF +#define SIO_PDR_I2S_DA_CFG__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_MODE__B 0 +#define SIO_PDR_I2S_DA_CFG_MODE__W 3 +#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7 +#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3 +#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38 +#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10 +#define SIO_PDR_I2S_DA_CFG_KEEP__B 6 +#define SIO_PDR_I2S_DA_CFG_KEEP__W 2 +#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0 +#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0 +#define SIO_PDR_I2S_DA_CFG_UIO__B 8 +#define SIO_PDR_I2S_DA_CFG_UIO__W 1 +#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100 +#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0 + +#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050 +#define SIO_PDR_GPIO_GPIO_FNC__W 2 +#define SIO_PDR_GPIO_GPIO_FNC__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052 +#define SIO_PDR_MSTRT_GPIO_FNC__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053 +#define SIO_PDR_MERR_GPIO_FNC__W 2 +#define SIO_PDR_MERR_GPIO_FNC__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054 +#define SIO_PDR_MCLK_GPIO_FNC__W 2 +#define SIO_PDR_MCLK_GPIO_FNC__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055 +#define SIO_PDR_MVAL_GPIO_FNC__W 2 +#define SIO_PDR_MVAL_GPIO_FNC__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056 +#define SIO_PDR_MD0_GPIO_FNC__W 2 +#define SIO_PDR_MD0_GPIO_FNC__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057 +#define SIO_PDR_MD1_GPIO_FNC__W 2 +#define SIO_PDR_MD1_GPIO_FNC__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058 +#define SIO_PDR_MD2_GPIO_FNC__W 2 +#define SIO_PDR_MD2_GPIO_FNC__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059 +#define SIO_PDR_MD3_GPIO_FNC__W 2 +#define SIO_PDR_MD3_GPIO_FNC__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A +#define SIO_PDR_MD4_GPIO_FNC__W 2 +#define SIO_PDR_MD4_GPIO_FNC__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B +#define SIO_PDR_MD5_GPIO_FNC__W 2 +#define SIO_PDR_MD5_GPIO_FNC__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C +#define SIO_PDR_MD6_GPIO_FNC__W 2 +#define SIO_PDR_MD6_GPIO_FNC__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D +#define SIO_PDR_MD7_GPIO_FNC__W 2 +#define SIO_PDR_MD7_GPIO_FNC__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0 +#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2 +#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E +#define SIO_PDR_SMA_RX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0 + +#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F +#define SIO_PDR_SMA_TX_GPIO_FNC__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3 +#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0 + +#endif + +