From: ChiHun Won <chihun.won@samsung.com>
Date: Mon, 4 Jun 2018 06:31:05 +0000 (+0900)
Subject: [9610] fbdev: dpu20: change DPP channel number for BTS calculation.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=432d50819d7c2a8097b8a0fb674e3e021487cc99;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[9610] fbdev: dpu20: change DPP channel number for BTS calculation.

There are 3 channels between AXI bus and DPU_DMA. And each channel is connected
to 2 IDMAs but this connection is different from previous SoC.

So, channel connection is initialized in DECON CAL Layer for common driver.

Change-Id: Iac174cc8e6949297e2d7c166a0470eadc6723394
Signed-off-by: ChiHun Won <chihun.won@samsung.com>
---

diff --git a/drivers/video/fbdev/exynos/dpu20/bts.c b/drivers/video/fbdev/exynos/dpu20/bts.c
index d7678741f793..f93c51e6d0f9 100644
--- a/drivers/video/fbdev/exynos/dpu20/bts.c
+++ b/drivers/video/fbdev/exynos/dpu20/bts.c
@@ -95,7 +95,7 @@ static void dpu_bts_sum_all_decon_bw(struct decon_device *decon, u32 ch_bw[])
 static void dpu_bts_find_max_disp_freq(struct decon_device *decon,
 		struct decon_reg_data *regs)
 {
-	int i, idx;
+	int i, j, idx;
 	u32 disp_ch_bw[BTS_DPU_MAX];
 	u32 max_disp_ch_bw;
 	u32 disp_op_freq = 0, freq = 0;
@@ -105,8 +105,10 @@ static void dpu_bts_find_max_disp_freq(struct decon_device *decon,
 
 	memset(disp_ch_bw, 0, sizeof(disp_ch_bw));
 
-	disp_ch_bw[BTS_DPU0] = decon->bts.bw[BTS_DPP0] + decon->bts.bw[BTS_DPP1];
-	disp_ch_bw[BTS_DPU1] = decon->bts.bw[BTS_DPP2] + decon->bts.bw[BTS_DPP3];
+	for (i = 0; i < BTS_DPP_MAX; ++i)
+		for (j = 0; j < BTS_DPU_MAX; ++j)
+			if (decon->bts.bw[i].ch_num == j)
+				disp_ch_bw[j] += decon->bts.bw[i].val;
 
 	/* must be considered other decon's bw */
 	dpu_bts_sum_all_decon_bw(decon, disp_ch_bw);
@@ -260,10 +262,10 @@ void dpu_bts_calc_bw(struct decon_device *decon, struct decon_reg_data *regs)
 	memcpy(&decon->bts.bts_info, &bts_info, sizeof(struct bts_decon_info));
 
 	for (i = 0; i < BTS_DPP_MAX; ++i) {
-		decon->bts.bw[i] = bts_info.dpp[i].bw;
-		if (decon->bts.bw[i])
+		decon->bts.bw[i].val = bts_info.dpp[i].bw;
+		if (decon->bts.bw[i].val)
 			DPU_DEBUG_BTS("\tDPP%d bandwidth = %d\n",
-					i, decon->bts.bw[i]);
+					i, decon->bts.bw[i].val);
 	}
 
 	DPU_DEBUG_BTS("\tDECON%d total bandwidth = %d\n", decon->id,
@@ -503,6 +505,10 @@ void dpu_bts_init(struct decon_device *decon)
 	pm_qos_add_request(&decon->bts.disp_qos, PM_QOS_DISPLAY_THROUGHPUT, 0);
 	decon->bts.scen_updated = 0;
 
+	decon_init_bts_info(decon->bts.bw);
+	for (i = 0; i < BTS_DPP_MAX; ++i)
+		DPU_INFO_BTS("IDMA_TYPE(%d) -> BTS CH(%d)\n", i, decon->bts.bw[i].ch_num);
+
 	decon->bts.enabled = true;
 
 	DPU_INFO_BTS("decon%d bts feature is enabled\n", decon->id);
diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
index 626ea70a15e6..a15e15d0bd5e 100644
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
@@ -245,9 +245,17 @@ struct decon_window_regs {
 	enum decon_blending blend;
 };
 
+struct decon_bts_bw {
+	u32 val;
+	u32 ch_num;
+};
+
 u32 DPU_DMA2CH(u32 dma);
 u32 DPU_CH2DMA(u32 ch);
 int decon_check_supported_formats(enum decon_pixel_format format);
+#if defined(CONFIG_EXYNOS9610_BTS)
+void decon_init_bts_info(struct decon_bts_bw bw[BTS_DPP_MAX]);
+#endif
 
 /*************** DECON CAL APIs exposed to DECON driver ***************/
 /* DECON control */
diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
index 844869622c36..1b01a441b89b 100644
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
@@ -2212,3 +2212,9 @@ int decon_check_supported_formats(enum decon_pixel_format format)
 
 	return -EINVAL;
 }
+#if defined(CONFIG_EXYNOS9610_BTS)
+void decon_init_bts_info(struct decon_bts_bw bw[])
+{
+
+}
+#endif
diff --git a/drivers/video/fbdev/exynos/dpu20/decon.h b/drivers/video/fbdev/exynos/dpu20/decon.h
index d9ab75482fb3..b91648480fb5 100644
--- a/drivers/video/fbdev/exynos/dpu20/decon.h
+++ b/drivers/video/fbdev/exynos/dpu20/decon.h
@@ -807,7 +807,8 @@ struct decon_bts {
 	u32 max_disp_freq;
 	u32 prev_max_disp_freq;
 #if defined(CONFIG_EXYNOS9610_BTS)
-	u32 bw[BTS_DPP_MAX];
+	struct decon_bts_bw bw[BTS_DPP_MAX];
+
 	/* each decon must know other decon's BW to get overall BW */
 	u32 ch_bw[3][BTS_DPU_MAX];
 	enum bts_bw_type type;