From: Martin Blumenstingl Date: Sun, 4 Sep 2016 18:23:20 +0000 (+0200) Subject: ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=42bede64c834e29fda0bd126c61ef61bc9d71278;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver The Amlogic reference driver uses the "mc_val" devicetree property to configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic values for this configuration. According to the datasheet the PRG_ETHERNET_ADDR0 register is at address 0xc8834108. However, the reference driver uses 0xc8834540 instead. According to my tests, the value from the reference driver is correct. No changes are required to the board dts files because the only required configuration option is the phy-mode, which had to be configured correctly before as well. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 3b181939f437..f76a3cdd1b2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -500,13 +500,15 @@ }; ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; phy-mode = "rgmii"; status = "disabled"; };