From: Imre Deak Date: Thu, 9 Jan 2014 15:08:15 +0000 (+0200) Subject: drm/i915: vlv: make CRI clock enabling explicit during resume X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=404faabc3f1a0e38babd9d900134fef3d41e2ae7;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915: vlv: make CRI clock enabling explicit during resume intel_init_dpio() isn't called during resume, so we won't set the CRI clock enable bit during that time. Move the enabling to intel_reset_dpio() instead. Note that the HW reset value for this bit is 1, so probably this patch won't make any difference. We should still make the setting explicit, since BIOS could change things under us. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 554e83d043fe..7df05112951d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1364,10 +1364,6 @@ static void intel_init_dpio(struct drm_device *dev) if (!IS_VALLEYVIEW(dev)) return; - /* Enable the CRI clock source so we can get at the display */ - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | - DPLL_INTEGRATED_CRI_CLK_VLV); - DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; } @@ -1378,6 +1374,10 @@ static void intel_reset_dpio(struct drm_device *dev) if (!IS_VALLEYVIEW(dev)) return; + /* Enable the CRI clock source so we can get at the display */ + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | + DPLL_INTEGRATED_CRI_CLK_VLV); + /* * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - * 6. De-assert cmn_reset/side_reset. Same as VLV X0.