From: Kyungwoo Kang Date: Sat, 6 May 2017 03:13:37 +0000 (+0900) Subject: [COMMON] i2c: exynos5: Fix debug print info X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=3f08af51d3c4d606905303cca5372dfef06d56f0;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git [COMMON] i2c: exynos5: Fix debug print info Add Dev->i2c node to see which node debug information is printed Change-Id: Ibd2ff3f707175732fa4c1b28a576afe9fc5c4209 Signed-off-by: Kyungwoo Kang --- diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 10850f757b64..bcd30de656d1 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -393,8 +393,10 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) utemp = readl(i2c->regs + HSI2C_TIMING_HS1) & ~0x00FF0000; writel(utemp | (uTSTART_HD_HS << 16), i2c->regs + HSI2C_TIMING_HS1); - pr_info("%s nPclk = %d nOpClk = %d Div = %d Timing HS1 = %X TIMING HS2 = %X TIMING HS3 = %X\n",__func__, nPclk, nOpClk, uCLK_DIV_HS, - readl(i2c->regs + HSI2C_TIMING_HS1), readl(i2c->regs + HSI2C_TIMING_HS2),readl(i2c->regs + HSI2C_TIMING_HS3)); + dev_info(i2c->dev, "%s nPclk = %d nOpClk = %d Div = %d Timing HS1 = %X " + "TIMING HS2 = %X TIMING HS3 = %X\n",__func__, nPclk, nOpClk, uCLK_DIV_HS, + readl(i2c->regs + HSI2C_TIMING_HS1), readl(i2c->regs + HSI2C_TIMING_HS2), + readl(i2c->regs + HSI2C_TIMING_HS3)); } else { /* Fast speed mode */ @@ -418,8 +420,10 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) utemp = readl(i2c->regs + HSI2C_TIMING_FS1) & ~0x00FF0000; writel(utemp | (uTSTART_HD_FS << 16), i2c->regs + HSI2C_TIMING_FS1); - pr_info("%s nPclk = %d nOpClk = %d Div = %d Timing FS1 = %X TIMING FS2 = %X TIMING FS3 = %X\n",__func__, nPclk, nOpClk, uCLK_DIV_FS, - readl(i2c->regs + HSI2C_TIMING_FS1), readl(i2c->regs + HSI2C_TIMING_FS2),readl(i2c->regs + HSI2C_TIMING_FS3)); + dev_info(i2c->dev, "%s nPclk = %d nOpClk = %d Div = %d Timing FS1 = %X " + "TIMING FS2 = %X TIMING FS3 = %X\n",__func__, nPclk, nOpClk, uCLK_DIV_FS, + readl(i2c->regs + HSI2C_TIMING_FS1), readl(i2c->regs + HSI2C_TIMING_FS2), + readl(i2c->regs + HSI2C_TIMING_FS3)); } return 0;